2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
51 #include <asm/proto.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/hw_irq.h>
63 #include <asm/uv/uv_hub.h>
64 #include <asm/uv/uv_irq.h>
68 #define __apicdebuginit(type) static type __init
69 #define for_each_irq_pin(entry, head) \
70 for (entry = head; entry; entry = entry->next)
73 * Is the SiS APIC rmw bug present ?
74 * -1 = don't know, 0 = no, 1 = yes
76 int sis_apic_bug = -1;
78 static DEFINE_SPINLOCK(ioapic_lock);
79 static DEFINE_SPINLOCK(vector_lock);
82 * # of IRQ routing registers
84 int nr_ioapic_registers[MAX_IO_APICS];
86 /* I/O APIC entries */
87 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
90 /* MP IRQ source entries */
91 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
93 /* # of MP IRQ source entries */
96 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
97 int mp_bus_id_to_type[MAX_MP_BUSSES];
100 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
102 int skip_ioapic_setup;
104 void arch_disable_smp_support(void)
108 noioapicreroute = -1;
110 skip_ioapic_setup = 1;
113 static int __init parse_noapic(char *str)
115 /* disable IO-APIC */
116 arch_disable_smp_support();
119 early_param("noapic", parse_noapic);
121 struct irq_pin_list {
123 struct irq_pin_list *next;
126 static struct irq_pin_list *get_one_free_irq_2_pin(int node)
128 struct irq_pin_list *pin;
130 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
136 * This is performance-critical, we want to do it O(1)
138 * Most irqs are mapped 1:1 with pins.
141 struct irq_pin_list *irq_2_pin;
142 cpumask_var_t domain;
143 cpumask_var_t old_domain;
144 unsigned move_cleanup_count;
146 u8 move_in_progress : 1;
149 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
150 #ifdef CONFIG_SPARSE_IRQ
151 static struct irq_cfg irq_cfgx[] = {
153 static struct irq_cfg irq_cfgx[NR_IRQS] = {
155 [0] = { .vector = IRQ0_VECTOR, },
156 [1] = { .vector = IRQ1_VECTOR, },
157 [2] = { .vector = IRQ2_VECTOR, },
158 [3] = { .vector = IRQ3_VECTOR, },
159 [4] = { .vector = IRQ4_VECTOR, },
160 [5] = { .vector = IRQ5_VECTOR, },
161 [6] = { .vector = IRQ6_VECTOR, },
162 [7] = { .vector = IRQ7_VECTOR, },
163 [8] = { .vector = IRQ8_VECTOR, },
164 [9] = { .vector = IRQ9_VECTOR, },
165 [10] = { .vector = IRQ10_VECTOR, },
166 [11] = { .vector = IRQ11_VECTOR, },
167 [12] = { .vector = IRQ12_VECTOR, },
168 [13] = { .vector = IRQ13_VECTOR, },
169 [14] = { .vector = IRQ14_VECTOR, },
170 [15] = { .vector = IRQ15_VECTOR, },
173 int __init arch_early_irq_init(void)
176 struct irq_desc *desc;
182 count = ARRAY_SIZE(irq_cfgx);
183 node= cpu_to_node(boot_cpu_id);
185 for (i = 0; i < count; i++) {
186 desc = irq_to_desc(i);
187 desc->chip_data = &cfg[i];
188 zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node);
189 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node);
190 if (i < NR_IRQS_LEGACY)
191 cpumask_setall(cfg[i].domain);
197 #ifdef CONFIG_SPARSE_IRQ
198 static struct irq_cfg *irq_cfg(unsigned int irq)
200 struct irq_cfg *cfg = NULL;
201 struct irq_desc *desc;
203 desc = irq_to_desc(irq);
205 cfg = desc->chip_data;
210 static struct irq_cfg *get_one_free_irq_cfg(int node)
214 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
216 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
219 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
221 free_cpumask_var(cfg->domain);
225 cpumask_clear(cfg->domain);
226 cpumask_clear(cfg->old_domain);
233 int arch_init_chip_data(struct irq_desc *desc, int node)
237 cfg = desc->chip_data;
239 desc->chip_data = get_one_free_irq_cfg(node);
240 if (!desc->chip_data) {
241 printk(KERN_ERR "can not alloc irq_cfg\n");
249 /* for move_irq_desc */
251 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node)
253 struct irq_pin_list *old_entry, *head, *tail, *entry;
255 cfg->irq_2_pin = NULL;
256 old_entry = old_cfg->irq_2_pin;
260 entry = get_one_free_irq_2_pin(node);
264 entry->apic = old_entry->apic;
265 entry->pin = old_entry->pin;
268 old_entry = old_entry->next;
270 entry = get_one_free_irq_2_pin(node);
278 /* still use the old one */
281 entry->apic = old_entry->apic;
282 entry->pin = old_entry->pin;
285 old_entry = old_entry->next;
289 cfg->irq_2_pin = head;
292 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
294 struct irq_pin_list *entry, *next;
296 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
299 entry = old_cfg->irq_2_pin;
306 old_cfg->irq_2_pin = NULL;
309 void arch_init_copy_chip_data(struct irq_desc *old_desc,
310 struct irq_desc *desc, int node)
313 struct irq_cfg *old_cfg;
315 cfg = get_one_free_irq_cfg(node);
320 desc->chip_data = cfg;
322 old_cfg = old_desc->chip_data;
324 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
326 init_copy_irq_2_pin(old_cfg, cfg, node);
329 static void free_irq_cfg(struct irq_cfg *old_cfg)
334 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
336 struct irq_cfg *old_cfg, *cfg;
338 old_cfg = old_desc->chip_data;
339 cfg = desc->chip_data;
345 free_irq_2_pin(old_cfg, cfg);
346 free_irq_cfg(old_cfg);
347 old_desc->chip_data = NULL;
350 /* end for move_irq_desc */
353 static struct irq_cfg *irq_cfg(unsigned int irq)
355 return irq < nr_irqs ? irq_cfgx + irq : NULL;
362 unsigned int unused[3];
364 unsigned int unused2[11];
368 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
370 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
371 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
374 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
376 struct io_apic __iomem *io_apic = io_apic_base(apic);
377 writel(vector, &io_apic->eoi);
380 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
382 struct io_apic __iomem *io_apic = io_apic_base(apic);
383 writel(reg, &io_apic->index);
384 return readl(&io_apic->data);
387 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
389 struct io_apic __iomem *io_apic = io_apic_base(apic);
390 writel(reg, &io_apic->index);
391 writel(value, &io_apic->data);
395 * Re-write a value: to be used for read-modify-write
396 * cycles where the read already set up the index register.
398 * Older SiS APIC requires we rewrite the index register
400 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
402 struct io_apic __iomem *io_apic = io_apic_base(apic);
405 writel(reg, &io_apic->index);
406 writel(value, &io_apic->data);
409 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
411 struct irq_pin_list *entry;
414 spin_lock_irqsave(&ioapic_lock, flags);
415 for_each_irq_pin(entry, cfg->irq_2_pin) {
420 reg = io_apic_read(entry->apic, 0x10 + pin*2);
421 /* Is the remote IRR bit set? */
422 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
423 spin_unlock_irqrestore(&ioapic_lock, flags);
427 spin_unlock_irqrestore(&ioapic_lock, flags);
433 struct { u32 w1, w2; };
434 struct IO_APIC_route_entry entry;
437 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
439 union entry_union eu;
441 spin_lock_irqsave(&ioapic_lock, flags);
442 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
443 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
444 spin_unlock_irqrestore(&ioapic_lock, flags);
449 * When we write a new IO APIC routing entry, we need to write the high
450 * word first! If the mask bit in the low word is clear, we will enable
451 * the interrupt, and we need to make sure the entry is fully populated
452 * before that happens.
455 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
457 union entry_union eu = {{0, 0}};
460 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
461 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
464 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
467 spin_lock_irqsave(&ioapic_lock, flags);
468 __ioapic_write_entry(apic, pin, e);
469 spin_unlock_irqrestore(&ioapic_lock, flags);
473 * When we mask an IO APIC routing entry, we need to write the low
474 * word first, in order to set the mask bit before we change the
477 static void ioapic_mask_entry(int apic, int pin)
480 union entry_union eu = { .entry.mask = 1 };
482 spin_lock_irqsave(&ioapic_lock, flags);
483 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
484 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
485 spin_unlock_irqrestore(&ioapic_lock, flags);
489 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
490 * shared ISA-space IRQs, so we have to support them. We are super
491 * fast in the common case, and fast for shared ISA-space IRQs.
494 add_pin_to_irq_node_nopanic(struct irq_cfg *cfg, int node, int apic, int pin)
496 struct irq_pin_list **last, *entry;
498 /* don't allow duplicates */
499 last = &cfg->irq_2_pin;
500 for_each_irq_pin(entry, cfg->irq_2_pin) {
501 if (entry->apic == apic && entry->pin == pin)
506 entry = get_one_free_irq_2_pin(node);
508 printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
519 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
521 if (add_pin_to_irq_node_nopanic(cfg, node, apic, pin))
522 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
526 * Reroute an IRQ to a different pin.
528 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
529 int oldapic, int oldpin,
530 int newapic, int newpin)
532 struct irq_pin_list *entry;
534 for_each_irq_pin(entry, cfg->irq_2_pin) {
535 if (entry->apic == oldapic && entry->pin == oldpin) {
536 entry->apic = newapic;
538 /* every one is different, right? */
543 /* old apic/pin didn't exist, so just add new ones */
544 add_pin_to_irq_node(cfg, node, newapic, newpin);
547 static void io_apic_modify_irq(struct irq_cfg *cfg,
548 int mask_and, int mask_or,
549 void (*final)(struct irq_pin_list *entry))
552 struct irq_pin_list *entry;
554 for_each_irq_pin(entry, cfg->irq_2_pin) {
557 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
560 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
566 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
568 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
571 static void io_apic_sync(struct irq_pin_list *entry)
574 * Synchronize the IO-APIC and the CPU by doing
575 * a dummy read from the IO-APIC
577 struct io_apic __iomem *io_apic;
578 io_apic = io_apic_base(entry->apic);
579 readl(&io_apic->data);
582 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
584 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
587 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
589 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
590 IO_APIC_REDIR_MASKED, NULL);
593 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
595 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
596 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
599 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
601 struct irq_cfg *cfg = desc->chip_data;
606 spin_lock_irqsave(&ioapic_lock, flags);
607 __mask_IO_APIC_irq(cfg);
608 spin_unlock_irqrestore(&ioapic_lock, flags);
611 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
613 struct irq_cfg *cfg = desc->chip_data;
616 spin_lock_irqsave(&ioapic_lock, flags);
617 __unmask_IO_APIC_irq(cfg);
618 spin_unlock_irqrestore(&ioapic_lock, flags);
621 static void mask_IO_APIC_irq(unsigned int irq)
623 struct irq_desc *desc = irq_to_desc(irq);
625 mask_IO_APIC_irq_desc(desc);
627 static void unmask_IO_APIC_irq(unsigned int irq)
629 struct irq_desc *desc = irq_to_desc(irq);
631 unmask_IO_APIC_irq_desc(desc);
634 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
636 struct IO_APIC_route_entry entry;
638 /* Check delivery_mode to be sure we're not clearing an SMI pin */
639 entry = ioapic_read_entry(apic, pin);
640 if (entry.delivery_mode == dest_SMI)
643 * Disable it in the IO-APIC irq-routing table:
645 ioapic_mask_entry(apic, pin);
648 static void clear_IO_APIC (void)
652 for (apic = 0; apic < nr_ioapics; apic++)
653 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
654 clear_IO_APIC_pin(apic, pin);
659 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
660 * specific CPU-side IRQs.
664 static int pirq_entries[MAX_PIRQS] = {
665 [0 ... MAX_PIRQS - 1] = -1
668 static int __init ioapic_pirq_setup(char *str)
671 int ints[MAX_PIRQS+1];
673 get_options(str, ARRAY_SIZE(ints), ints);
675 apic_printk(APIC_VERBOSE, KERN_INFO
676 "PIRQ redirection, working around broken MP-BIOS.\n");
678 if (ints[0] < MAX_PIRQS)
681 for (i = 0; i < max; i++) {
682 apic_printk(APIC_VERBOSE, KERN_DEBUG
683 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
685 * PIRQs are mapped upside down, usually.
687 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
692 __setup("pirq=", ioapic_pirq_setup);
693 #endif /* CONFIG_X86_32 */
695 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
698 struct IO_APIC_route_entry **ioapic_entries;
700 ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
705 for (apic = 0; apic < nr_ioapics; apic++) {
706 ioapic_entries[apic] =
707 kzalloc(sizeof(struct IO_APIC_route_entry) *
708 nr_ioapic_registers[apic], GFP_ATOMIC);
709 if (!ioapic_entries[apic])
713 return ioapic_entries;
717 kfree(ioapic_entries[apic]);
718 kfree(ioapic_entries);
724 * Saves all the IO-APIC RTE's
726 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
733 for (apic = 0; apic < nr_ioapics; apic++) {
734 if (!ioapic_entries[apic])
737 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
738 ioapic_entries[apic][pin] =
739 ioapic_read_entry(apic, pin);
746 * Mask all IO APIC entries.
748 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
755 for (apic = 0; apic < nr_ioapics; apic++) {
756 if (!ioapic_entries[apic])
759 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
760 struct IO_APIC_route_entry entry;
762 entry = ioapic_entries[apic][pin];
765 ioapic_write_entry(apic, pin, entry);
772 * Restore IO APIC entries which was saved in ioapic_entries.
774 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
781 for (apic = 0; apic < nr_ioapics; apic++) {
782 if (!ioapic_entries[apic])
785 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
786 ioapic_write_entry(apic, pin,
787 ioapic_entries[apic][pin]);
792 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
796 for (apic = 0; apic < nr_ioapics; apic++)
797 kfree(ioapic_entries[apic]);
799 kfree(ioapic_entries);
803 * Find the IRQ entry number of a certain pin.
805 static int find_irq_entry(int apic, int pin, int type)
809 for (i = 0; i < mp_irq_entries; i++)
810 if (mp_irqs[i].irqtype == type &&
811 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
812 mp_irqs[i].dstapic == MP_APIC_ALL) &&
813 mp_irqs[i].dstirq == pin)
820 * Find the pin to which IRQ[irq] (ISA) is connected
822 static int __init find_isa_irq_pin(int irq, int type)
826 for (i = 0; i < mp_irq_entries; i++) {
827 int lbus = mp_irqs[i].srcbus;
829 if (test_bit(lbus, mp_bus_not_pci) &&
830 (mp_irqs[i].irqtype == type) &&
831 (mp_irqs[i].srcbusirq == irq))
833 return mp_irqs[i].dstirq;
838 static int __init find_isa_irq_apic(int irq, int type)
842 for (i = 0; i < mp_irq_entries; i++) {
843 int lbus = mp_irqs[i].srcbus;
845 if (test_bit(lbus, mp_bus_not_pci) &&
846 (mp_irqs[i].irqtype == type) &&
847 (mp_irqs[i].srcbusirq == irq))
850 if (i < mp_irq_entries) {
852 for(apic = 0; apic < nr_ioapics; apic++) {
853 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
861 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
863 * EISA Edge/Level control register, ELCR
865 static int EISA_ELCR(unsigned int irq)
867 if (irq < NR_IRQS_LEGACY) {
868 unsigned int port = 0x4d0 + (irq >> 3);
869 return (inb(port) >> (irq & 7)) & 1;
871 apic_printk(APIC_VERBOSE, KERN_INFO
872 "Broken MPtable reports ISA irq %d\n", irq);
878 /* ISA interrupts are always polarity zero edge triggered,
879 * when listed as conforming in the MP table. */
881 #define default_ISA_trigger(idx) (0)
882 #define default_ISA_polarity(idx) (0)
884 /* EISA interrupts are always polarity zero and can be edge or level
885 * trigger depending on the ELCR value. If an interrupt is listed as
886 * EISA conforming in the MP table, that means its trigger type must
887 * be read in from the ELCR */
889 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
890 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
892 /* PCI interrupts are always polarity one level triggered,
893 * when listed as conforming in the MP table. */
895 #define default_PCI_trigger(idx) (1)
896 #define default_PCI_polarity(idx) (1)
898 /* MCA interrupts are always polarity zero level triggered,
899 * when listed as conforming in the MP table. */
901 #define default_MCA_trigger(idx) (1)
902 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
904 static int MPBIOS_polarity(int idx)
906 int bus = mp_irqs[idx].srcbus;
910 * Determine IRQ line polarity (high active or low active):
912 switch (mp_irqs[idx].irqflag & 3)
914 case 0: /* conforms, ie. bus-type dependent polarity */
915 if (test_bit(bus, mp_bus_not_pci))
916 polarity = default_ISA_polarity(idx);
918 polarity = default_PCI_polarity(idx);
920 case 1: /* high active */
925 case 2: /* reserved */
927 printk(KERN_WARNING "broken BIOS!!\n");
931 case 3: /* low active */
936 default: /* invalid */
938 printk(KERN_WARNING "broken BIOS!!\n");
946 static int MPBIOS_trigger(int idx)
948 int bus = mp_irqs[idx].srcbus;
952 * Determine IRQ trigger mode (edge or level sensitive):
954 switch ((mp_irqs[idx].irqflag>>2) & 3)
956 case 0: /* conforms, ie. bus-type dependent */
957 if (test_bit(bus, mp_bus_not_pci))
958 trigger = default_ISA_trigger(idx);
960 trigger = default_PCI_trigger(idx);
961 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
962 switch (mp_bus_id_to_type[bus]) {
963 case MP_BUS_ISA: /* ISA pin */
965 /* set before the switch */
968 case MP_BUS_EISA: /* EISA pin */
970 trigger = default_EISA_trigger(idx);
973 case MP_BUS_PCI: /* PCI pin */
975 /* set before the switch */
978 case MP_BUS_MCA: /* MCA pin */
980 trigger = default_MCA_trigger(idx);
985 printk(KERN_WARNING "broken BIOS!!\n");
997 case 2: /* reserved */
999 printk(KERN_WARNING "broken BIOS!!\n");
1008 default: /* invalid */
1010 printk(KERN_WARNING "broken BIOS!!\n");
1018 static inline int irq_polarity(int idx)
1020 return MPBIOS_polarity(idx);
1023 static inline int irq_trigger(int idx)
1025 return MPBIOS_trigger(idx);
1028 int (*ioapic_renumber_irq)(int ioapic, int irq);
1029 static int pin_2_irq(int idx, int apic, int pin)
1032 int bus = mp_irqs[idx].srcbus;
1035 * Debugging check, we are in big trouble if this message pops up!
1037 if (mp_irqs[idx].dstirq != pin)
1038 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1040 if (test_bit(bus, mp_bus_not_pci)) {
1041 irq = mp_irqs[idx].srcbusirq;
1044 * PCI IRQs are mapped in order
1048 irq += nr_ioapic_registers[i++];
1051 * For MPS mode, so far only needed by ES7000 platform
1053 if (ioapic_renumber_irq)
1054 irq = ioapic_renumber_irq(apic, irq);
1057 #ifdef CONFIG_X86_32
1059 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1061 if ((pin >= 16) && (pin <= 23)) {
1062 if (pirq_entries[pin-16] != -1) {
1063 if (!pirq_entries[pin-16]) {
1064 apic_printk(APIC_VERBOSE, KERN_DEBUG
1065 "disabling PIRQ%d\n", pin-16);
1067 irq = pirq_entries[pin-16];
1068 apic_printk(APIC_VERBOSE, KERN_DEBUG
1069 "using PIRQ%d -> IRQ %d\n",
1080 * Find a specific PCI IRQ entry.
1081 * Not an __init, possibly needed by modules
1083 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1084 struct io_apic_irq_attr *irq_attr)
1086 int apic, i, best_guess = -1;
1088 apic_printk(APIC_DEBUG,
1089 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1091 if (test_bit(bus, mp_bus_not_pci)) {
1092 apic_printk(APIC_VERBOSE,
1093 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1096 for (i = 0; i < mp_irq_entries; i++) {
1097 int lbus = mp_irqs[i].srcbus;
1099 for (apic = 0; apic < nr_ioapics; apic++)
1100 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1101 mp_irqs[i].dstapic == MP_APIC_ALL)
1104 if (!test_bit(lbus, mp_bus_not_pci) &&
1105 !mp_irqs[i].irqtype &&
1107 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1108 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1110 if (!(apic || IO_APIC_IRQ(irq)))
1113 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1114 set_io_apic_irq_attr(irq_attr, apic,
1121 * Use the first all-but-pin matching entry as a
1122 * best-guess fuzzy result for broken mptables.
1124 if (best_guess < 0) {
1125 set_io_apic_irq_attr(irq_attr, apic,
1135 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1137 void lock_vector_lock(void)
1139 /* Used to the online set of cpus does not change
1140 * during assign_irq_vector.
1142 spin_lock(&vector_lock);
1145 void unlock_vector_lock(void)
1147 spin_unlock(&vector_lock);
1151 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1154 * NOTE! The local APIC isn't very good at handling
1155 * multiple interrupts at the same interrupt level.
1156 * As the interrupt level is determined by taking the
1157 * vector number and shifting that right by 4, we
1158 * want to spread these out a bit so that they don't
1159 * all fall in the same interrupt level.
1161 * Also, we've got to be careful not to trash gate
1162 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1164 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1165 unsigned int old_vector;
1167 cpumask_var_t tmp_mask;
1169 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1172 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1175 old_vector = cfg->vector;
1177 cpumask_and(tmp_mask, mask, cpu_online_mask);
1178 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1179 if (!cpumask_empty(tmp_mask)) {
1180 free_cpumask_var(tmp_mask);
1185 /* Only try and allocate irqs on cpus that are present */
1187 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1191 apic->vector_allocation_domain(cpu, tmp_mask);
1193 vector = current_vector;
1194 offset = current_offset;
1197 if (vector >= first_system_vector) {
1198 /* If out of vectors on large boxen, must share them. */
1199 offset = (offset + 1) % 8;
1200 vector = FIRST_DEVICE_VECTOR + offset;
1202 if (unlikely(current_vector == vector))
1205 if (test_bit(vector, used_vectors))
1208 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1209 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1212 current_vector = vector;
1213 current_offset = offset;
1215 cfg->move_in_progress = 1;
1216 cpumask_copy(cfg->old_domain, cfg->domain);
1218 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1219 per_cpu(vector_irq, new_cpu)[vector] = irq;
1220 cfg->vector = vector;
1221 cpumask_copy(cfg->domain, tmp_mask);
1225 free_cpumask_var(tmp_mask);
1230 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1233 unsigned long flags;
1235 spin_lock_irqsave(&vector_lock, flags);
1236 err = __assign_irq_vector(irq, cfg, mask);
1237 spin_unlock_irqrestore(&vector_lock, flags);
1241 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1245 BUG_ON(!cfg->vector);
1247 vector = cfg->vector;
1248 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1249 per_cpu(vector_irq, cpu)[vector] = -1;
1252 cpumask_clear(cfg->domain);
1254 if (likely(!cfg->move_in_progress))
1256 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1257 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1259 if (per_cpu(vector_irq, cpu)[vector] != irq)
1261 per_cpu(vector_irq, cpu)[vector] = -1;
1265 cfg->move_in_progress = 0;
1268 void __setup_vector_irq(int cpu)
1270 /* Initialize vector_irq on a new cpu */
1271 /* This function must be called with vector_lock held */
1273 struct irq_cfg *cfg;
1274 struct irq_desc *desc;
1276 /* Mark the inuse vectors */
1277 for_each_irq_desc(irq, desc) {
1278 cfg = desc->chip_data;
1279 if (!cpumask_test_cpu(cpu, cfg->domain))
1281 vector = cfg->vector;
1282 per_cpu(vector_irq, cpu)[vector] = irq;
1284 /* Mark the free vectors */
1285 for (vector = 0; vector < NR_VECTORS; ++vector) {
1286 irq = per_cpu(vector_irq, cpu)[vector];
1291 if (!cpumask_test_cpu(cpu, cfg->domain))
1292 per_cpu(vector_irq, cpu)[vector] = -1;
1296 static struct irq_chip ioapic_chip;
1297 static struct irq_chip ir_ioapic_chip;
1299 #define IOAPIC_AUTO -1
1300 #define IOAPIC_EDGE 0
1301 #define IOAPIC_LEVEL 1
1303 #ifdef CONFIG_X86_32
1304 static inline int IO_APIC_irq_trigger(int irq)
1308 for (apic = 0; apic < nr_ioapics; apic++) {
1309 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1310 idx = find_irq_entry(apic, pin, mp_INT);
1311 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1312 return irq_trigger(idx);
1316 * nonexistent IRQs are edge default
1321 static inline int IO_APIC_irq_trigger(int irq)
1327 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1330 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1331 trigger == IOAPIC_LEVEL)
1332 desc->status |= IRQ_LEVEL;
1334 desc->status &= ~IRQ_LEVEL;
1336 if (irq_remapped(irq)) {
1337 desc->status |= IRQ_MOVE_PCNTXT;
1339 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1343 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1344 handle_edge_irq, "edge");
1348 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1349 trigger == IOAPIC_LEVEL)
1350 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1354 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1355 handle_edge_irq, "edge");
1358 int setup_ioapic_entry(int apic_id, int irq,
1359 struct IO_APIC_route_entry *entry,
1360 unsigned int destination, int trigger,
1361 int polarity, int vector, int pin)
1364 * add it to the IO-APIC irq-routing table:
1366 memset(entry,0,sizeof(*entry));
1368 if (intr_remapping_enabled) {
1369 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1371 struct IR_IO_APIC_route_entry *ir_entry =
1372 (struct IR_IO_APIC_route_entry *) entry;
1376 panic("No mapping iommu for ioapic %d\n", apic_id);
1378 index = alloc_irte(iommu, irq, 1);
1380 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1382 memset(&irte, 0, sizeof(irte));
1385 irte.dst_mode = apic->irq_dest_mode;
1387 * Trigger mode in the IRTE will always be edge, and the
1388 * actual level or edge trigger will be setup in the IO-APIC
1389 * RTE. This will help simplify level triggered irq migration.
1390 * For more details, see the comments above explainig IO-APIC
1391 * irq migration in the presence of interrupt-remapping.
1393 irte.trigger_mode = 0;
1394 irte.dlvry_mode = apic->irq_delivery_mode;
1395 irte.vector = vector;
1396 irte.dest_id = IRTE_DEST(destination);
1398 /* Set source-id of interrupt request */
1399 set_ioapic_sid(&irte, apic_id);
1401 modify_irte(irq, &irte);
1403 ir_entry->index2 = (index >> 15) & 0x1;
1405 ir_entry->format = 1;
1406 ir_entry->index = (index & 0x7fff);
1408 * IO-APIC RTE will be configured with virtual vector.
1409 * irq handler will do the explicit EOI to the io-apic.
1411 ir_entry->vector = pin;
1413 entry->delivery_mode = apic->irq_delivery_mode;
1414 entry->dest_mode = apic->irq_dest_mode;
1415 entry->dest = destination;
1416 entry->vector = vector;
1419 entry->mask = 0; /* enable IRQ */
1420 entry->trigger = trigger;
1421 entry->polarity = polarity;
1423 /* Mask level triggered irqs.
1424 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1431 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1432 int trigger, int polarity)
1434 struct irq_cfg *cfg;
1435 struct IO_APIC_route_entry entry;
1438 if (!IO_APIC_IRQ(irq))
1441 cfg = desc->chip_data;
1443 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1446 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1448 apic_printk(APIC_VERBOSE,KERN_DEBUG
1449 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1450 "IRQ %d Mode:%i Active:%i)\n",
1451 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1452 irq, trigger, polarity);
1455 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1456 dest, trigger, polarity, cfg->vector, pin)) {
1457 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1458 mp_ioapics[apic_id].apicid, pin);
1459 __clear_irq_vector(irq, cfg);
1463 ioapic_register_intr(irq, desc, trigger);
1464 if (irq < NR_IRQS_LEGACY)
1465 disable_8259A_irq(irq);
1467 ioapic_write_entry(apic_id, pin, entry);
1471 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
1472 } mp_ioapic_routing[MAX_IO_APICS];
1474 static void __init setup_IO_APIC_irqs(void)
1476 int apic_id = 0, pin, idx, irq;
1478 struct irq_desc *desc;
1479 struct irq_cfg *cfg;
1480 int node = cpu_to_node(boot_cpu_id);
1482 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1485 if (!acpi_disabled && acpi_ioapic) {
1486 apic_id = mp_find_ioapic(0);
1492 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1493 idx = find_irq_entry(apic_id, pin, mp_INT);
1497 apic_printk(APIC_VERBOSE,
1498 KERN_DEBUG " %d-%d",
1499 mp_ioapics[apic_id].apicid, pin);
1501 apic_printk(APIC_VERBOSE, " %d-%d",
1502 mp_ioapics[apic_id].apicid, pin);
1506 apic_printk(APIC_VERBOSE,
1507 " (apicid-pin) not connected\n");
1511 irq = pin_2_irq(idx, apic_id, pin);
1514 * Skip the timer IRQ if there's a quirk handler
1515 * installed and if it returns 1:
1517 if (apic->multi_timer_check &&
1518 apic->multi_timer_check(apic_id, irq))
1521 desc = irq_to_desc_alloc_node(irq, node);
1523 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1526 cfg = desc->chip_data;
1527 add_pin_to_irq_node(cfg, node, apic_id, pin);
1529 * don't mark it in pin_programmed, so later acpi could
1530 * set it correctly when irq < 16
1532 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1533 irq_trigger(idx), irq_polarity(idx));
1537 apic_printk(APIC_VERBOSE,
1538 " (apicid-pin) not connected\n");
1542 * Set up the timer pin, possibly with the 8259A-master behind.
1544 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1547 struct IO_APIC_route_entry entry;
1549 if (intr_remapping_enabled)
1552 memset(&entry, 0, sizeof(entry));
1555 * We use logical delivery to get the timer IRQ
1558 entry.dest_mode = apic->irq_dest_mode;
1559 entry.mask = 0; /* don't mask IRQ for edge */
1560 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1561 entry.delivery_mode = apic->irq_delivery_mode;
1564 entry.vector = vector;
1567 * The timer IRQ doesn't have to know that behind the
1568 * scene we may have a 8259A-master in AEOI mode ...
1570 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1573 * Add it to the IO-APIC irq-routing table:
1575 ioapic_write_entry(apic_id, pin, entry);
1579 __apicdebuginit(void) print_IO_APIC(void)
1582 union IO_APIC_reg_00 reg_00;
1583 union IO_APIC_reg_01 reg_01;
1584 union IO_APIC_reg_02 reg_02;
1585 union IO_APIC_reg_03 reg_03;
1586 unsigned long flags;
1587 struct irq_cfg *cfg;
1588 struct irq_desc *desc;
1591 if (apic_verbosity == APIC_QUIET)
1594 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1595 for (i = 0; i < nr_ioapics; i++)
1596 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1597 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1600 * We are a bit conservative about what we expect. We have to
1601 * know about every hardware change ASAP.
1603 printk(KERN_INFO "testing the IO APIC.......................\n");
1605 for (apic = 0; apic < nr_ioapics; apic++) {
1607 spin_lock_irqsave(&ioapic_lock, flags);
1608 reg_00.raw = io_apic_read(apic, 0);
1609 reg_01.raw = io_apic_read(apic, 1);
1610 if (reg_01.bits.version >= 0x10)
1611 reg_02.raw = io_apic_read(apic, 2);
1612 if (reg_01.bits.version >= 0x20)
1613 reg_03.raw = io_apic_read(apic, 3);
1614 spin_unlock_irqrestore(&ioapic_lock, flags);
1617 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1618 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1619 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1620 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1621 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1623 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1624 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1626 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1627 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1630 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1631 * but the value of reg_02 is read as the previous read register
1632 * value, so ignore it if reg_02 == reg_01.
1634 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1635 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1636 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1640 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1641 * or reg_03, but the value of reg_0[23] is read as the previous read
1642 * register value, so ignore it if reg_03 == reg_0[12].
1644 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1645 reg_03.raw != reg_01.raw) {
1646 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1647 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1650 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1652 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1653 " Stat Dmod Deli Vect: \n");
1655 for (i = 0; i <= reg_01.bits.entries; i++) {
1656 struct IO_APIC_route_entry entry;
1658 entry = ioapic_read_entry(apic, i);
1660 printk(KERN_DEBUG " %02x %03X ",
1665 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1670 entry.delivery_status,
1672 entry.delivery_mode,
1677 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1678 for_each_irq_desc(irq, desc) {
1679 struct irq_pin_list *entry;
1681 cfg = desc->chip_data;
1682 entry = cfg->irq_2_pin;
1685 printk(KERN_DEBUG "IRQ%d ", irq);
1686 for_each_irq_pin(entry, cfg->irq_2_pin)
1687 printk("-> %d:%d", entry->apic, entry->pin);
1691 printk(KERN_INFO ".................................... done.\n");
1696 __apicdebuginit(void) print_APIC_field(int base)
1700 if (apic_verbosity == APIC_QUIET)
1705 for (i = 0; i < 8; i++)
1706 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1708 printk(KERN_CONT "\n");
1711 __apicdebuginit(void) print_local_APIC(void *dummy)
1713 unsigned int i, v, ver, maxlvt;
1716 if (apic_verbosity == APIC_QUIET)
1719 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1720 smp_processor_id(), hard_smp_processor_id());
1721 v = apic_read(APIC_ID);
1722 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1723 v = apic_read(APIC_LVR);
1724 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1725 ver = GET_APIC_VERSION(v);
1726 maxlvt = lapic_get_maxlvt();
1728 v = apic_read(APIC_TASKPRI);
1729 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1731 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1732 if (!APIC_XAPIC(ver)) {
1733 v = apic_read(APIC_ARBPRI);
1734 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1735 v & APIC_ARBPRI_MASK);
1737 v = apic_read(APIC_PROCPRI);
1738 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1742 * Remote read supported only in the 82489DX and local APIC for
1743 * Pentium processors.
1745 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1746 v = apic_read(APIC_RRR);
1747 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1750 v = apic_read(APIC_LDR);
1751 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1752 if (!x2apic_enabled()) {
1753 v = apic_read(APIC_DFR);
1754 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1756 v = apic_read(APIC_SPIV);
1757 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1759 printk(KERN_DEBUG "... APIC ISR field:\n");
1760 print_APIC_field(APIC_ISR);
1761 printk(KERN_DEBUG "... APIC TMR field:\n");
1762 print_APIC_field(APIC_TMR);
1763 printk(KERN_DEBUG "... APIC IRR field:\n");
1764 print_APIC_field(APIC_IRR);
1766 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1767 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1768 apic_write(APIC_ESR, 0);
1770 v = apic_read(APIC_ESR);
1771 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1774 icr = apic_icr_read();
1775 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1776 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1778 v = apic_read(APIC_LVTT);
1779 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1781 if (maxlvt > 3) { /* PC is LVT#4. */
1782 v = apic_read(APIC_LVTPC);
1783 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1785 v = apic_read(APIC_LVT0);
1786 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1787 v = apic_read(APIC_LVT1);
1788 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1790 if (maxlvt > 2) { /* ERR is LVT#3. */
1791 v = apic_read(APIC_LVTERR);
1792 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1795 v = apic_read(APIC_TMICT);
1796 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1797 v = apic_read(APIC_TMCCT);
1798 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1799 v = apic_read(APIC_TDCR);
1800 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1802 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1803 v = apic_read(APIC_EFEAT);
1804 maxlvt = (v >> 16) & 0xff;
1805 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1806 v = apic_read(APIC_ECTRL);
1807 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1808 for (i = 0; i < maxlvt; i++) {
1809 v = apic_read(APIC_EILVTn(i));
1810 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1816 __apicdebuginit(void) print_all_local_APICs(void)
1821 for_each_online_cpu(cpu)
1822 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1826 __apicdebuginit(void) print_PIC(void)
1829 unsigned long flags;
1831 if (apic_verbosity == APIC_QUIET)
1834 printk(KERN_DEBUG "\nprinting PIC contents\n");
1836 spin_lock_irqsave(&i8259A_lock, flags);
1838 v = inb(0xa1) << 8 | inb(0x21);
1839 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1841 v = inb(0xa0) << 8 | inb(0x20);
1842 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1846 v = inb(0xa0) << 8 | inb(0x20);
1850 spin_unlock_irqrestore(&i8259A_lock, flags);
1852 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1854 v = inb(0x4d1) << 8 | inb(0x4d0);
1855 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1858 __apicdebuginit(int) print_all_ICs(void)
1862 /* don't print out if apic is not there */
1863 if (!cpu_has_apic || disable_apic)
1866 print_all_local_APICs();
1872 fs_initcall(print_all_ICs);
1875 /* Where if anywhere is the i8259 connect in external int mode */
1876 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1878 void __init enable_IO_APIC(void)
1880 union IO_APIC_reg_01 reg_01;
1881 int i8259_apic, i8259_pin;
1883 unsigned long flags;
1886 * The number of IO-APIC IRQ registers (== #pins):
1888 for (apic = 0; apic < nr_ioapics; apic++) {
1889 spin_lock_irqsave(&ioapic_lock, flags);
1890 reg_01.raw = io_apic_read(apic, 1);
1891 spin_unlock_irqrestore(&ioapic_lock, flags);
1892 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1894 for(apic = 0; apic < nr_ioapics; apic++) {
1896 /* See if any of the pins is in ExtINT mode */
1897 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1898 struct IO_APIC_route_entry entry;
1899 entry = ioapic_read_entry(apic, pin);
1901 /* If the interrupt line is enabled and in ExtInt mode
1902 * I have found the pin where the i8259 is connected.
1904 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1905 ioapic_i8259.apic = apic;
1906 ioapic_i8259.pin = pin;
1912 /* Look to see what if the MP table has reported the ExtINT */
1913 /* If we could not find the appropriate pin by looking at the ioapic
1914 * the i8259 probably is not connected the ioapic but give the
1915 * mptable a chance anyway.
1917 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1918 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1919 /* Trust the MP table if nothing is setup in the hardware */
1920 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1921 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1922 ioapic_i8259.pin = i8259_pin;
1923 ioapic_i8259.apic = i8259_apic;
1925 /* Complain if the MP table and the hardware disagree */
1926 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1927 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1929 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1933 * Do not trust the IO-APIC being empty at bootup
1939 * Not an __init, needed by the reboot code
1941 void disable_IO_APIC(void)
1944 * Clear the IO-APIC before rebooting:
1949 * If the i8259 is routed through an IOAPIC
1950 * Put that IOAPIC in virtual wire mode
1951 * so legacy interrupts can be delivered.
1953 * With interrupt-remapping, for now we will use virtual wire A mode,
1954 * as virtual wire B is little complex (need to configure both
1955 * IOAPIC RTE aswell as interrupt-remapping table entry).
1956 * As this gets called during crash dump, keep this simple for now.
1958 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
1959 struct IO_APIC_route_entry entry;
1961 memset(&entry, 0, sizeof(entry));
1962 entry.mask = 0; /* Enabled */
1963 entry.trigger = 0; /* Edge */
1965 entry.polarity = 0; /* High */
1966 entry.delivery_status = 0;
1967 entry.dest_mode = 0; /* Physical */
1968 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1970 entry.dest = read_apic_id();
1973 * Add it to the IO-APIC irq-routing table:
1975 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1979 * Use virtual wire A mode when interrupt remapping is enabled.
1982 disconnect_bsp_APIC(!intr_remapping_enabled &&
1983 ioapic_i8259.pin != -1);
1986 #ifdef CONFIG_X86_32
1988 * function to set the IO-APIC physical IDs based on the
1989 * values stored in the MPC table.
1991 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1994 static void __init setup_ioapic_ids_from_mpc(void)
1996 union IO_APIC_reg_00 reg_00;
1997 physid_mask_t phys_id_present_map;
2000 unsigned char old_id;
2001 unsigned long flags;
2003 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2007 * Don't check I/O APIC IDs for xAPIC systems. They have
2008 * no meaning without the serial APIC bus.
2010 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2011 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2014 * This is broken; anything with a real cpu count has to
2015 * circumvent this idiocy regardless.
2017 phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
2020 * Set the IOAPIC ID to the value stored in the MPC table.
2022 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2024 /* Read the register 0 value */
2025 spin_lock_irqsave(&ioapic_lock, flags);
2026 reg_00.raw = io_apic_read(apic_id, 0);
2027 spin_unlock_irqrestore(&ioapic_lock, flags);
2029 old_id = mp_ioapics[apic_id].apicid;
2031 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2032 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2033 apic_id, mp_ioapics[apic_id].apicid);
2034 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2036 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2040 * Sanity check, is the ID really free? Every APIC in a
2041 * system must have a unique ID or we get lots of nice
2042 * 'stuck on smp_invalidate_needed IPI wait' messages.
2044 if (apic->check_apicid_used(phys_id_present_map,
2045 mp_ioapics[apic_id].apicid)) {
2046 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2047 apic_id, mp_ioapics[apic_id].apicid);
2048 for (i = 0; i < get_physical_broadcast(); i++)
2049 if (!physid_isset(i, phys_id_present_map))
2051 if (i >= get_physical_broadcast())
2052 panic("Max APIC ID exceeded!\n");
2053 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2055 physid_set(i, phys_id_present_map);
2056 mp_ioapics[apic_id].apicid = i;
2059 tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
2060 apic_printk(APIC_VERBOSE, "Setting %d in the "
2061 "phys_id_present_map\n",
2062 mp_ioapics[apic_id].apicid);
2063 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2068 * We need to adjust the IRQ routing table
2069 * if the ID changed.
2071 if (old_id != mp_ioapics[apic_id].apicid)
2072 for (i = 0; i < mp_irq_entries; i++)
2073 if (mp_irqs[i].dstapic == old_id)
2075 = mp_ioapics[apic_id].apicid;
2078 * Read the right value from the MPC table and
2079 * write it into the ID register.
2081 apic_printk(APIC_VERBOSE, KERN_INFO
2082 "...changing IO-APIC physical APIC ID to %d ...",
2083 mp_ioapics[apic_id].apicid);
2085 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2086 spin_lock_irqsave(&ioapic_lock, flags);
2087 io_apic_write(apic_id, 0, reg_00.raw);
2088 spin_unlock_irqrestore(&ioapic_lock, flags);
2093 spin_lock_irqsave(&ioapic_lock, flags);
2094 reg_00.raw = io_apic_read(apic_id, 0);
2095 spin_unlock_irqrestore(&ioapic_lock, flags);
2096 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2097 printk("could not set ID!\n");
2099 apic_printk(APIC_VERBOSE, " ok.\n");
2104 int no_timer_check __initdata;
2106 static int __init notimercheck(char *s)
2111 __setup("no_timer_check", notimercheck);
2114 * There is a nasty bug in some older SMP boards, their mptable lies
2115 * about the timer IRQ. We do the following to work around the situation:
2117 * - timer IRQ defaults to IO-APIC IRQ
2118 * - if this function detects that timer IRQs are defunct, then we fall
2119 * back to ISA timer IRQs
2121 static int __init timer_irq_works(void)
2123 unsigned long t1 = jiffies;
2124 unsigned long flags;
2129 local_save_flags(flags);
2131 /* Let ten ticks pass... */
2132 mdelay((10 * 1000) / HZ);
2133 local_irq_restore(flags);
2136 * Expect a few ticks at least, to be sure some possible
2137 * glue logic does not lock up after one or two first
2138 * ticks in a non-ExtINT mode. Also the local APIC
2139 * might have cached one ExtINT interrupt. Finally, at
2140 * least one tick may be lost due to delays.
2144 if (time_after(jiffies, t1 + 4))
2150 * In the SMP+IOAPIC case it might happen that there are an unspecified
2151 * number of pending IRQ events unhandled. These cases are very rare,
2152 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2153 * better to do it this way as thus we do not have to be aware of
2154 * 'pending' interrupts in the IRQ path, except at this point.
2157 * Edge triggered needs to resend any interrupt
2158 * that was delayed but this is now handled in the device
2163 * Starting up a edge-triggered IO-APIC interrupt is
2164 * nasty - we need to make sure that we get the edge.
2165 * If it is already asserted for some reason, we need
2166 * return 1 to indicate that is was pending.
2168 * This is not complete - we should be able to fake
2169 * an edge even if it isn't on the 8259A...
2172 static unsigned int startup_ioapic_irq(unsigned int irq)
2174 int was_pending = 0;
2175 unsigned long flags;
2176 struct irq_cfg *cfg;
2178 spin_lock_irqsave(&ioapic_lock, flags);
2179 if (irq < NR_IRQS_LEGACY) {
2180 disable_8259A_irq(irq);
2181 if (i8259A_irq_pending(irq))
2185 __unmask_IO_APIC_irq(cfg);
2186 spin_unlock_irqrestore(&ioapic_lock, flags);
2191 static int ioapic_retrigger_irq(unsigned int irq)
2194 struct irq_cfg *cfg = irq_cfg(irq);
2195 unsigned long flags;
2197 spin_lock_irqsave(&vector_lock, flags);
2198 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2199 spin_unlock_irqrestore(&vector_lock, flags);
2205 * Level and edge triggered IO-APIC interrupts need different handling,
2206 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2207 * handled with the level-triggered descriptor, but that one has slightly
2208 * more overhead. Level-triggered interrupts cannot be handled with the
2209 * edge-triggered handler, without risking IRQ storms and other ugly
2214 static void send_cleanup_vector(struct irq_cfg *cfg)
2216 cpumask_var_t cleanup_mask;
2218 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2220 cfg->move_cleanup_count = 0;
2221 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2222 cfg->move_cleanup_count++;
2223 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2224 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2226 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2227 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
2228 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2229 free_cpumask_var(cleanup_mask);
2231 cfg->move_in_progress = 0;
2234 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2237 struct irq_pin_list *entry;
2238 u8 vector = cfg->vector;
2240 for_each_irq_pin(entry, cfg->irq_2_pin) {
2246 * With interrupt-remapping, destination information comes
2247 * from interrupt-remapping table entry.
2249 if (!irq_remapped(irq))
2250 io_apic_write(apic, 0x11 + pin*2, dest);
2251 reg = io_apic_read(apic, 0x10 + pin*2);
2252 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2254 io_apic_modify(apic, 0x10 + pin*2, reg);
2259 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
2262 * Either sets desc->affinity to a valid value, and returns
2263 * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
2264 * leaves desc->affinity untouched.
2267 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
2269 struct irq_cfg *cfg;
2272 if (!cpumask_intersects(mask, cpu_online_mask))
2276 cfg = desc->chip_data;
2277 if (assign_irq_vector(irq, cfg, mask))
2280 cpumask_copy(desc->affinity, mask);
2282 return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
2286 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2288 struct irq_cfg *cfg;
2289 unsigned long flags;
2295 cfg = desc->chip_data;
2297 spin_lock_irqsave(&ioapic_lock, flags);
2298 dest = set_desc_affinity(desc, mask);
2299 if (dest != BAD_APICID) {
2300 /* Only the high 8 bits are valid. */
2301 dest = SET_APIC_LOGICAL_ID(dest);
2302 __target_IO_APIC_irq(irq, dest, cfg);
2305 spin_unlock_irqrestore(&ioapic_lock, flags);
2311 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
2313 struct irq_desc *desc;
2315 desc = irq_to_desc(irq);
2317 return set_ioapic_affinity_irq_desc(desc, mask);
2320 #ifdef CONFIG_INTR_REMAP
2323 * Migrate the IO-APIC irq in the presence of intr-remapping.
2325 * For both level and edge triggered, irq migration is a simple atomic
2326 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2328 * For level triggered, we eliminate the io-apic RTE modification (with the
2329 * updated vector information), by using a virtual vector (io-apic pin number).
2330 * Real vector that is used for interrupting cpu will be coming from
2331 * the interrupt-remapping table entry.
2334 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2336 struct irq_cfg *cfg;
2342 if (!cpumask_intersects(mask, cpu_online_mask))
2346 if (get_irte(irq, &irte))
2349 cfg = desc->chip_data;
2350 if (assign_irq_vector(irq, cfg, mask))
2353 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2355 irte.vector = cfg->vector;
2356 irte.dest_id = IRTE_DEST(dest);
2359 * Modified the IRTE and flushes the Interrupt entry cache.
2361 modify_irte(irq, &irte);
2363 if (cfg->move_in_progress)
2364 send_cleanup_vector(cfg);
2366 cpumask_copy(desc->affinity, mask);
2372 * Migrates the IRQ destination in the process context.
2374 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2375 const struct cpumask *mask)
2377 return migrate_ioapic_irq_desc(desc, mask);
2379 static int set_ir_ioapic_affinity_irq(unsigned int irq,
2380 const struct cpumask *mask)
2382 struct irq_desc *desc = irq_to_desc(irq);
2384 return set_ir_ioapic_affinity_irq_desc(desc, mask);
2387 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2388 const struct cpumask *mask)
2394 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2396 unsigned vector, me;
2402 me = smp_processor_id();
2403 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2406 struct irq_desc *desc;
2407 struct irq_cfg *cfg;
2408 irq = __get_cpu_var(vector_irq)[vector];
2413 desc = irq_to_desc(irq);
2418 spin_lock(&desc->lock);
2419 if (!cfg->move_cleanup_count)
2422 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2425 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2427 * Check if the vector that needs to be cleanedup is
2428 * registered at the cpu's IRR. If so, then this is not
2429 * the best time to clean it up. Lets clean it up in the
2430 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2433 if (irr & (1 << (vector % 32))) {
2434 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2437 __get_cpu_var(vector_irq)[vector] = -1;
2438 cfg->move_cleanup_count--;
2440 spin_unlock(&desc->lock);
2446 static void irq_complete_move(struct irq_desc **descp)
2448 struct irq_desc *desc = *descp;
2449 struct irq_cfg *cfg = desc->chip_data;
2450 unsigned vector, me;
2452 if (likely(!cfg->move_in_progress))
2455 vector = ~get_irq_regs()->orig_ax;
2456 me = smp_processor_id();
2458 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2459 send_cleanup_vector(cfg);
2462 static inline void irq_complete_move(struct irq_desc **descp) {}
2465 static void ack_apic_edge(unsigned int irq)
2467 struct irq_desc *desc = irq_to_desc(irq);
2469 irq_complete_move(&desc);
2470 move_native_irq(irq);
2474 atomic_t irq_mis_count;
2476 static void ack_apic_level(unsigned int irq)
2478 struct irq_desc *desc = irq_to_desc(irq);
2481 struct irq_cfg *cfg;
2482 int do_unmask_irq = 0;
2484 irq_complete_move(&desc);
2485 #ifdef CONFIG_GENERIC_PENDING_IRQ
2486 /* If we are moving the irq we need to mask it */
2487 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2489 mask_IO_APIC_irq_desc(desc);
2494 * It appears there is an erratum which affects at least version 0x11
2495 * of I/O APIC (that's the 82093AA and cores integrated into various
2496 * chipsets). Under certain conditions a level-triggered interrupt is
2497 * erroneously delivered as edge-triggered one but the respective IRR
2498 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2499 * message but it will never arrive and further interrupts are blocked
2500 * from the source. The exact reason is so far unknown, but the
2501 * phenomenon was observed when two consecutive interrupt requests
2502 * from a given source get delivered to the same CPU and the source is
2503 * temporarily disabled in between.
2505 * A workaround is to simulate an EOI message manually. We achieve it
2506 * by setting the trigger mode to edge and then to level when the edge
2507 * trigger mode gets detected in the TMR of a local APIC for a
2508 * level-triggered interrupt. We mask the source for the time of the
2509 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2510 * The idea is from Manfred Spraul. --macro
2512 cfg = desc->chip_data;
2514 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2517 * We must acknowledge the irq before we move it or the acknowledge will
2518 * not propagate properly.
2522 /* Now we can move and renable the irq */
2523 if (unlikely(do_unmask_irq)) {
2524 /* Only migrate the irq if the ack has been received.
2526 * On rare occasions the broadcast level triggered ack gets
2527 * delayed going to ioapics, and if we reprogram the
2528 * vector while Remote IRR is still set the irq will never
2531 * To prevent this scenario we read the Remote IRR bit
2532 * of the ioapic. This has two effects.
2533 * - On any sane system the read of the ioapic will
2534 * flush writes (and acks) going to the ioapic from
2536 * - We get to see if the ACK has actually been delivered.
2538 * Based on failed experiments of reprogramming the
2539 * ioapic entry from outside of irq context starting
2540 * with masking the ioapic entry and then polling until
2541 * Remote IRR was clear before reprogramming the
2542 * ioapic I don't trust the Remote IRR bit to be
2543 * completey accurate.
2545 * However there appears to be no other way to plug
2546 * this race, so if the Remote IRR bit is not
2547 * accurate and is causing problems then it is a hardware bug
2548 * and you can go talk to the chipset vendor about it.
2550 cfg = desc->chip_data;
2551 if (!io_apic_level_ack_pending(cfg))
2552 move_masked_irq(irq);
2553 unmask_IO_APIC_irq_desc(desc);
2556 /* Tail end of version 0x11 I/O APIC bug workaround */
2557 if (!(v & (1 << (i & 0x1f)))) {
2558 atomic_inc(&irq_mis_count);
2559 spin_lock(&ioapic_lock);
2560 __mask_and_edge_IO_APIC_irq(cfg);
2561 __unmask_and_level_IO_APIC_irq(cfg);
2562 spin_unlock(&ioapic_lock);
2566 #ifdef CONFIG_INTR_REMAP
2567 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2569 struct irq_pin_list *entry;
2571 for_each_irq_pin(entry, cfg->irq_2_pin)
2572 io_apic_eoi(entry->apic, entry->pin);
2576 eoi_ioapic_irq(struct irq_desc *desc)
2578 struct irq_cfg *cfg;
2579 unsigned long flags;
2583 cfg = desc->chip_data;
2585 spin_lock_irqsave(&ioapic_lock, flags);
2586 __eoi_ioapic_irq(irq, cfg);
2587 spin_unlock_irqrestore(&ioapic_lock, flags);
2590 static void ir_ack_apic_edge(unsigned int irq)
2595 static void ir_ack_apic_level(unsigned int irq)
2597 struct irq_desc *desc = irq_to_desc(irq);
2600 eoi_ioapic_irq(desc);
2602 #endif /* CONFIG_INTR_REMAP */
2604 static struct irq_chip ioapic_chip __read_mostly = {
2606 .startup = startup_ioapic_irq,
2607 .mask = mask_IO_APIC_irq,
2608 .unmask = unmask_IO_APIC_irq,
2609 .ack = ack_apic_edge,
2610 .eoi = ack_apic_level,
2612 .set_affinity = set_ioapic_affinity_irq,
2614 .retrigger = ioapic_retrigger_irq,
2617 static struct irq_chip ir_ioapic_chip __read_mostly = {
2618 .name = "IR-IO-APIC",
2619 .startup = startup_ioapic_irq,
2620 .mask = mask_IO_APIC_irq,
2621 .unmask = unmask_IO_APIC_irq,
2622 #ifdef CONFIG_INTR_REMAP
2623 .ack = ir_ack_apic_edge,
2624 .eoi = ir_ack_apic_level,
2626 .set_affinity = set_ir_ioapic_affinity_irq,
2629 .retrigger = ioapic_retrigger_irq,
2632 static inline void init_IO_APIC_traps(void)
2635 struct irq_desc *desc;
2636 struct irq_cfg *cfg;
2639 * NOTE! The local APIC isn't very good at handling
2640 * multiple interrupts at the same interrupt level.
2641 * As the interrupt level is determined by taking the
2642 * vector number and shifting that right by 4, we
2643 * want to spread these out a bit so that they don't
2644 * all fall in the same interrupt level.
2646 * Also, we've got to be careful not to trash gate
2647 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2649 for_each_irq_desc(irq, desc) {
2650 cfg = desc->chip_data;
2651 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2653 * Hmm.. We don't have an entry for this,
2654 * so default to an old-fashioned 8259
2655 * interrupt if we can..
2657 if (irq < NR_IRQS_LEGACY)
2658 make_8259A_irq(irq);
2660 /* Strange. Oh, well.. */
2661 desc->chip = &no_irq_chip;
2667 * The local APIC irq-chip implementation:
2670 static void mask_lapic_irq(unsigned int irq)
2674 v = apic_read(APIC_LVT0);
2675 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2678 static void unmask_lapic_irq(unsigned int irq)
2682 v = apic_read(APIC_LVT0);
2683 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2686 static void ack_lapic_irq(unsigned int irq)
2691 static struct irq_chip lapic_chip __read_mostly = {
2692 .name = "local-APIC",
2693 .mask = mask_lapic_irq,
2694 .unmask = unmask_lapic_irq,
2695 .ack = ack_lapic_irq,
2698 static void lapic_register_intr(int irq, struct irq_desc *desc)
2700 desc->status &= ~IRQ_LEVEL;
2701 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2705 static void __init setup_nmi(void)
2708 * Dirty trick to enable the NMI watchdog ...
2709 * We put the 8259A master into AEOI mode and
2710 * unmask on all local APICs LVT0 as NMI.
2712 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2713 * is from Maciej W. Rozycki - so we do not have to EOI from
2714 * the NMI handler or the timer interrupt.
2716 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2718 enable_NMI_through_LVT0();
2720 apic_printk(APIC_VERBOSE, " done.\n");
2724 * This looks a bit hackish but it's about the only one way of sending
2725 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2726 * not support the ExtINT mode, unfortunately. We need to send these
2727 * cycles as some i82489DX-based boards have glue logic that keeps the
2728 * 8259A interrupt line asserted until INTA. --macro
2730 static inline void __init unlock_ExtINT_logic(void)
2733 struct IO_APIC_route_entry entry0, entry1;
2734 unsigned char save_control, save_freq_select;
2736 pin = find_isa_irq_pin(8, mp_INT);
2741 apic = find_isa_irq_apic(8, mp_INT);
2747 entry0 = ioapic_read_entry(apic, pin);
2748 clear_IO_APIC_pin(apic, pin);
2750 memset(&entry1, 0, sizeof(entry1));
2752 entry1.dest_mode = 0; /* physical delivery */
2753 entry1.mask = 0; /* unmask IRQ now */
2754 entry1.dest = hard_smp_processor_id();
2755 entry1.delivery_mode = dest_ExtINT;
2756 entry1.polarity = entry0.polarity;
2760 ioapic_write_entry(apic, pin, entry1);
2762 save_control = CMOS_READ(RTC_CONTROL);
2763 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2764 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2766 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2771 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2775 CMOS_WRITE(save_control, RTC_CONTROL);
2776 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2777 clear_IO_APIC_pin(apic, pin);
2779 ioapic_write_entry(apic, pin, entry0);
2782 static int disable_timer_pin_1 __initdata;
2783 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2784 static int __init disable_timer_pin_setup(char *arg)
2786 disable_timer_pin_1 = 1;
2789 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2791 int timer_through_8259 __initdata;
2794 * This code may look a bit paranoid, but it's supposed to cooperate with
2795 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2796 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2797 * fanatically on his truly buggy board.
2799 * FIXME: really need to revamp this for all platforms.
2801 static inline void __init check_timer(void)
2803 struct irq_desc *desc = irq_to_desc(0);
2804 struct irq_cfg *cfg = desc->chip_data;
2805 int node = cpu_to_node(boot_cpu_id);
2806 int apic1, pin1, apic2, pin2;
2807 unsigned long flags;
2810 local_irq_save(flags);
2813 * get/set the timer IRQ vector:
2815 disable_8259A_irq(0);
2816 assign_irq_vector(0, cfg, apic->target_cpus());
2819 * As IRQ0 is to be enabled in the 8259A, the virtual
2820 * wire has to be disabled in the local APIC. Also
2821 * timer interrupts need to be acknowledged manually in
2822 * the 8259A for the i82489DX when using the NMI
2823 * watchdog as that APIC treats NMIs as level-triggered.
2824 * The AEOI mode will finish them in the 8259A
2827 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2829 #ifdef CONFIG_X86_32
2833 ver = apic_read(APIC_LVR);
2834 ver = GET_APIC_VERSION(ver);
2835 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2839 pin1 = find_isa_irq_pin(0, mp_INT);
2840 apic1 = find_isa_irq_apic(0, mp_INT);
2841 pin2 = ioapic_i8259.pin;
2842 apic2 = ioapic_i8259.apic;
2844 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2845 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2846 cfg->vector, apic1, pin1, apic2, pin2);
2849 * Some BIOS writers are clueless and report the ExtINTA
2850 * I/O APIC input from the cascaded 8259A as the timer
2851 * interrupt input. So just in case, if only one pin
2852 * was found above, try it both directly and through the
2856 if (intr_remapping_enabled)
2857 panic("BIOS bug: timer not connected to IO-APIC");
2861 } else if (pin2 == -1) {
2868 * Ok, does IRQ0 through the IOAPIC work?
2871 add_pin_to_irq_node(cfg, node, apic1, pin1);
2872 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2874 /* for edge trigger, setup_IO_APIC_irq already
2875 * leave it unmasked.
2876 * so only need to unmask if it is level-trigger
2877 * do we really have level trigger timer?
2880 idx = find_irq_entry(apic1, pin1, mp_INT);
2881 if (idx != -1 && irq_trigger(idx))
2882 unmask_IO_APIC_irq_desc(desc);
2884 if (timer_irq_works()) {
2885 if (nmi_watchdog == NMI_IO_APIC) {
2887 enable_8259A_irq(0);
2889 if (disable_timer_pin_1 > 0)
2890 clear_IO_APIC_pin(0, pin1);
2893 if (intr_remapping_enabled)
2894 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2895 local_irq_disable();
2896 clear_IO_APIC_pin(apic1, pin1);
2898 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2899 "8254 timer not connected to IO-APIC\n");
2901 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2902 "(IRQ0) through the 8259A ...\n");
2903 apic_printk(APIC_QUIET, KERN_INFO
2904 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2906 * legacy devices should be connected to IO APIC #0
2908 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2909 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2910 enable_8259A_irq(0);
2911 if (timer_irq_works()) {
2912 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2913 timer_through_8259 = 1;
2914 if (nmi_watchdog == NMI_IO_APIC) {
2915 disable_8259A_irq(0);
2917 enable_8259A_irq(0);
2922 * Cleanup, just in case ...
2924 local_irq_disable();
2925 disable_8259A_irq(0);
2926 clear_IO_APIC_pin(apic2, pin2);
2927 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2930 if (nmi_watchdog == NMI_IO_APIC) {
2931 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2932 "through the IO-APIC - disabling NMI Watchdog!\n");
2933 nmi_watchdog = NMI_NONE;
2935 #ifdef CONFIG_X86_32
2939 apic_printk(APIC_QUIET, KERN_INFO
2940 "...trying to set up timer as Virtual Wire IRQ...\n");
2942 lapic_register_intr(0, desc);
2943 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2944 enable_8259A_irq(0);
2946 if (timer_irq_works()) {
2947 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2950 local_irq_disable();
2951 disable_8259A_irq(0);
2952 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2953 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2955 apic_printk(APIC_QUIET, KERN_INFO
2956 "...trying to set up timer as ExtINT IRQ...\n");
2960 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2962 unlock_ExtINT_logic();
2964 if (timer_irq_works()) {
2965 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2968 local_irq_disable();
2969 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2970 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2971 "report. Then try booting with the 'noapic' option.\n");
2973 local_irq_restore(flags);
2977 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2978 * to devices. However there may be an I/O APIC pin available for
2979 * this interrupt regardless. The pin may be left unconnected, but
2980 * typically it will be reused as an ExtINT cascade interrupt for
2981 * the master 8259A. In the MPS case such a pin will normally be
2982 * reported as an ExtINT interrupt in the MP table. With ACPI
2983 * there is no provision for ExtINT interrupts, and in the absence
2984 * of an override it would be treated as an ordinary ISA I/O APIC
2985 * interrupt, that is edge-triggered and unmasked by default. We
2986 * used to do this, but it caused problems on some systems because
2987 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2988 * the same ExtINT cascade interrupt to drive the local APIC of the
2989 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2990 * the I/O APIC in all cases now. No actual device should request
2991 * it anyway. --macro
2993 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2995 void __init setup_IO_APIC(void)
2999 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3002 io_apic_irqs = ~PIC_IRQS;
3004 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3006 * Set up IO-APIC IRQ routing.
3008 #ifdef CONFIG_X86_32
3010 setup_ioapic_ids_from_mpc();
3013 setup_IO_APIC_irqs();
3014 init_IO_APIC_traps();
3019 * Called after all the initialization is done. If we didnt find any
3020 * APIC bugs then we can allow the modify fast path
3023 static int __init io_apic_bug_finalize(void)
3025 if (sis_apic_bug == -1)
3030 late_initcall(io_apic_bug_finalize);
3032 struct sysfs_ioapic_data {
3033 struct sys_device dev;
3034 struct IO_APIC_route_entry entry[0];
3036 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3038 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3040 struct IO_APIC_route_entry *entry;
3041 struct sysfs_ioapic_data *data;
3044 data = container_of(dev, struct sysfs_ioapic_data, dev);
3045 entry = data->entry;
3046 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3047 *entry = ioapic_read_entry(dev->id, i);
3052 static int ioapic_resume(struct sys_device *dev)
3054 struct IO_APIC_route_entry *entry;
3055 struct sysfs_ioapic_data *data;
3056 unsigned long flags;
3057 union IO_APIC_reg_00 reg_00;
3060 data = container_of(dev, struct sysfs_ioapic_data, dev);
3061 entry = data->entry;
3063 spin_lock_irqsave(&ioapic_lock, flags);
3064 reg_00.raw = io_apic_read(dev->id, 0);
3065 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3066 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3067 io_apic_write(dev->id, 0, reg_00.raw);
3069 spin_unlock_irqrestore(&ioapic_lock, flags);
3070 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3071 ioapic_write_entry(dev->id, i, entry[i]);
3076 static struct sysdev_class ioapic_sysdev_class = {
3078 .suspend = ioapic_suspend,
3079 .resume = ioapic_resume,
3082 static int __init ioapic_init_sysfs(void)
3084 struct sys_device * dev;
3087 error = sysdev_class_register(&ioapic_sysdev_class);
3091 for (i = 0; i < nr_ioapics; i++ ) {
3092 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3093 * sizeof(struct IO_APIC_route_entry);
3094 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3095 if (!mp_ioapic_data[i]) {
3096 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3099 dev = &mp_ioapic_data[i]->dev;
3101 dev->cls = &ioapic_sysdev_class;
3102 error = sysdev_register(dev);
3104 kfree(mp_ioapic_data[i]);
3105 mp_ioapic_data[i] = NULL;
3106 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3114 device_initcall(ioapic_init_sysfs);
3116 static int nr_irqs_gsi = NR_IRQS_LEGACY;
3118 * Dynamic irq allocate and deallocation
3120 unsigned int create_irq_nr(unsigned int irq_want, int node)
3122 /* Allocate an unused irq */
3125 unsigned long flags;
3126 struct irq_cfg *cfg_new = NULL;
3127 struct irq_desc *desc_new = NULL;
3130 if (irq_want < nr_irqs_gsi)
3131 irq_want = nr_irqs_gsi;
3133 spin_lock_irqsave(&vector_lock, flags);
3134 for (new = irq_want; new < nr_irqs; new++) {
3135 desc_new = irq_to_desc_alloc_node(new, node);
3137 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3140 cfg_new = desc_new->chip_data;
3142 if (cfg_new->vector != 0)
3145 desc_new = move_irq_desc(desc_new, node);
3147 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3151 spin_unlock_irqrestore(&vector_lock, flags);
3154 dynamic_irq_init(irq);
3155 /* restore it, in case dynamic_irq_init clear it */
3157 desc_new->chip_data = cfg_new;
3162 int create_irq(void)
3164 int node = cpu_to_node(boot_cpu_id);
3165 unsigned int irq_want;
3168 irq_want = nr_irqs_gsi;
3169 irq = create_irq_nr(irq_want, node);
3177 void destroy_irq(unsigned int irq)
3179 unsigned long flags;
3180 struct irq_cfg *cfg;
3181 struct irq_desc *desc;
3183 /* store it, in case dynamic_irq_cleanup clear it */
3184 desc = irq_to_desc(irq);
3185 cfg = desc->chip_data;
3186 dynamic_irq_cleanup(irq);
3187 /* connect back irq_cfg */
3188 desc->chip_data = cfg;
3191 spin_lock_irqsave(&vector_lock, flags);
3192 __clear_irq_vector(irq, cfg);
3193 spin_unlock_irqrestore(&vector_lock, flags);
3197 * MSI message composition
3199 #ifdef CONFIG_PCI_MSI
3200 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3202 struct irq_cfg *cfg;
3210 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3214 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3216 if (irq_remapped(irq)) {
3221 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3222 BUG_ON(ir_index == -1);
3224 memset (&irte, 0, sizeof(irte));
3227 irte.dst_mode = apic->irq_dest_mode;
3228 irte.trigger_mode = 0; /* edge */
3229 irte.dlvry_mode = apic->irq_delivery_mode;
3230 irte.vector = cfg->vector;
3231 irte.dest_id = IRTE_DEST(dest);
3233 /* Set source-id of interrupt request */
3234 set_msi_sid(&irte, pdev);
3236 modify_irte(irq, &irte);
3238 msg->address_hi = MSI_ADDR_BASE_HI;
3239 msg->data = sub_handle;
3240 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3242 MSI_ADDR_IR_INDEX1(ir_index) |
3243 MSI_ADDR_IR_INDEX2(ir_index);
3245 if (x2apic_enabled())
3246 msg->address_hi = MSI_ADDR_BASE_HI |
3247 MSI_ADDR_EXT_DEST_ID(dest);
3249 msg->address_hi = MSI_ADDR_BASE_HI;
3253 ((apic->irq_dest_mode == 0) ?
3254 MSI_ADDR_DEST_MODE_PHYSICAL:
3255 MSI_ADDR_DEST_MODE_LOGICAL) |
3256 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3257 MSI_ADDR_REDIRECTION_CPU:
3258 MSI_ADDR_REDIRECTION_LOWPRI) |
3259 MSI_ADDR_DEST_ID(dest);
3262 MSI_DATA_TRIGGER_EDGE |
3263 MSI_DATA_LEVEL_ASSERT |
3264 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3265 MSI_DATA_DELIVERY_FIXED:
3266 MSI_DATA_DELIVERY_LOWPRI) |
3267 MSI_DATA_VECTOR(cfg->vector);
3273 static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3275 struct irq_desc *desc = irq_to_desc(irq);
3276 struct irq_cfg *cfg;
3280 dest = set_desc_affinity(desc, mask);
3281 if (dest == BAD_APICID)
3284 cfg = desc->chip_data;
3286 read_msi_msg_desc(desc, &msg);
3288 msg.data &= ~MSI_DATA_VECTOR_MASK;
3289 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3290 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3291 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3293 write_msi_msg_desc(desc, &msg);
3297 #ifdef CONFIG_INTR_REMAP
3299 * Migrate the MSI irq to another cpumask. This migration is
3300 * done in the process context using interrupt-remapping hardware.
3303 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3305 struct irq_desc *desc = irq_to_desc(irq);
3306 struct irq_cfg *cfg = desc->chip_data;
3310 if (get_irte(irq, &irte))
3313 dest = set_desc_affinity(desc, mask);
3314 if (dest == BAD_APICID)
3317 irte.vector = cfg->vector;
3318 irte.dest_id = IRTE_DEST(dest);
3321 * atomically update the IRTE with the new destination and vector.
3323 modify_irte(irq, &irte);
3326 * After this point, all the interrupts will start arriving
3327 * at the new destination. So, time to cleanup the previous
3328 * vector allocation.
3330 if (cfg->move_in_progress)
3331 send_cleanup_vector(cfg);
3337 #endif /* CONFIG_SMP */
3340 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3341 * which implement the MSI or MSI-X Capability Structure.
3343 static struct irq_chip msi_chip = {
3345 .unmask = unmask_msi_irq,
3346 .mask = mask_msi_irq,
3347 .ack = ack_apic_edge,
3349 .set_affinity = set_msi_irq_affinity,
3351 .retrigger = ioapic_retrigger_irq,
3354 static struct irq_chip msi_ir_chip = {
3355 .name = "IR-PCI-MSI",
3356 .unmask = unmask_msi_irq,
3357 .mask = mask_msi_irq,
3358 #ifdef CONFIG_INTR_REMAP
3359 .ack = ir_ack_apic_edge,
3361 .set_affinity = ir_set_msi_irq_affinity,
3364 .retrigger = ioapic_retrigger_irq,
3368 * Map the PCI dev to the corresponding remapping hardware unit
3369 * and allocate 'nvec' consecutive interrupt-remapping table entries
3372 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3374 struct intel_iommu *iommu;
3377 iommu = map_dev_to_ir(dev);
3380 "Unable to map PCI %s to iommu\n", pci_name(dev));
3384 index = alloc_irte(iommu, irq, nvec);
3387 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3394 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3399 ret = msi_compose_msg(dev, irq, &msg);
3403 set_irq_msi(irq, msidesc);
3404 write_msi_msg(irq, &msg);
3406 if (irq_remapped(irq)) {
3407 struct irq_desc *desc = irq_to_desc(irq);
3409 * irq migration in process context
3411 desc->status |= IRQ_MOVE_PCNTXT;
3412 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3414 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3416 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3421 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3424 int ret, sub_handle;
3425 struct msi_desc *msidesc;
3426 unsigned int irq_want;
3427 struct intel_iommu *iommu = NULL;
3431 /* x86 doesn't support multiple MSI yet */
3432 if (type == PCI_CAP_ID_MSI && nvec > 1)
3435 node = dev_to_node(&dev->dev);
3436 irq_want = nr_irqs_gsi;
3438 list_for_each_entry(msidesc, &dev->msi_list, list) {
3439 irq = create_irq_nr(irq_want, node);
3443 if (!intr_remapping_enabled)
3448 * allocate the consecutive block of IRTE's
3451 index = msi_alloc_irte(dev, irq, nvec);
3457 iommu = map_dev_to_ir(dev);
3463 * setup the mapping between the irq and the IRTE
3464 * base index, the sub_handle pointing to the
3465 * appropriate interrupt remap table entry.
3467 set_irte_irq(irq, iommu, index, sub_handle);
3470 ret = setup_msi_irq(dev, msidesc, irq);
3482 void arch_teardown_msi_irq(unsigned int irq)
3487 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3489 static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3491 struct irq_desc *desc = irq_to_desc(irq);
3492 struct irq_cfg *cfg;
3496 dest = set_desc_affinity(desc, mask);
3497 if (dest == BAD_APICID)
3500 cfg = desc->chip_data;
3502 dmar_msi_read(irq, &msg);
3504 msg.data &= ~MSI_DATA_VECTOR_MASK;
3505 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3506 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3507 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3509 dmar_msi_write(irq, &msg);
3514 #endif /* CONFIG_SMP */
3516 static struct irq_chip dmar_msi_type = {
3518 .unmask = dmar_msi_unmask,
3519 .mask = dmar_msi_mask,
3520 .ack = ack_apic_edge,
3522 .set_affinity = dmar_msi_set_affinity,
3524 .retrigger = ioapic_retrigger_irq,
3527 int arch_setup_dmar_msi(unsigned int irq)
3532 ret = msi_compose_msg(NULL, irq, &msg);
3535 dmar_msi_write(irq, &msg);
3536 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3542 #ifdef CONFIG_HPET_TIMER
3545 static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3547 struct irq_desc *desc = irq_to_desc(irq);
3548 struct irq_cfg *cfg;
3552 dest = set_desc_affinity(desc, mask);
3553 if (dest == BAD_APICID)
3556 cfg = desc->chip_data;
3558 hpet_msi_read(irq, &msg);
3560 msg.data &= ~MSI_DATA_VECTOR_MASK;
3561 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3562 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3563 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3565 hpet_msi_write(irq, &msg);
3570 #endif /* CONFIG_SMP */
3572 static struct irq_chip hpet_msi_type = {
3574 .unmask = hpet_msi_unmask,
3575 .mask = hpet_msi_mask,
3576 .ack = ack_apic_edge,
3578 .set_affinity = hpet_msi_set_affinity,
3580 .retrigger = ioapic_retrigger_irq,
3583 int arch_setup_hpet_msi(unsigned int irq)
3587 struct irq_desc *desc = irq_to_desc(irq);
3589 ret = msi_compose_msg(NULL, irq, &msg);
3593 hpet_msi_write(irq, &msg);
3594 desc->status |= IRQ_MOVE_PCNTXT;
3595 set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3602 #endif /* CONFIG_PCI_MSI */
3604 * Hypertransport interrupt support
3606 #ifdef CONFIG_HT_IRQ
3610 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3612 struct ht_irq_msg msg;
3613 fetch_ht_irq_msg(irq, &msg);
3615 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3616 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3618 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3619 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3621 write_ht_irq_msg(irq, &msg);
3624 static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3626 struct irq_desc *desc = irq_to_desc(irq);
3627 struct irq_cfg *cfg;
3630 dest = set_desc_affinity(desc, mask);
3631 if (dest == BAD_APICID)
3634 cfg = desc->chip_data;
3636 target_ht_irq(irq, dest, cfg->vector);
3643 static struct irq_chip ht_irq_chip = {
3645 .mask = mask_ht_irq,
3646 .unmask = unmask_ht_irq,
3647 .ack = ack_apic_edge,
3649 .set_affinity = set_ht_irq_affinity,
3651 .retrigger = ioapic_retrigger_irq,
3654 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3656 struct irq_cfg *cfg;
3663 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3665 struct ht_irq_msg msg;
3668 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3669 apic->target_cpus());
3671 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3675 HT_IRQ_LOW_DEST_ID(dest) |
3676 HT_IRQ_LOW_VECTOR(cfg->vector) |
3677 ((apic->irq_dest_mode == 0) ?
3678 HT_IRQ_LOW_DM_PHYSICAL :
3679 HT_IRQ_LOW_DM_LOGICAL) |
3680 HT_IRQ_LOW_RQEOI_EDGE |
3681 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3682 HT_IRQ_LOW_MT_FIXED :
3683 HT_IRQ_LOW_MT_ARBITRATED) |
3684 HT_IRQ_LOW_IRQ_MASKED;
3686 write_ht_irq_msg(irq, &msg);
3688 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3689 handle_edge_irq, "edge");
3691 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3695 #endif /* CONFIG_HT_IRQ */
3697 #ifdef CONFIG_X86_UV
3699 * Re-target the irq to the specified CPU and enable the specified MMR located
3700 * on the specified blade to allow the sending of MSIs to the specified CPU.
3702 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3703 unsigned long mmr_offset)
3705 const struct cpumask *eligible_cpu = cpumask_of(cpu);
3706 struct irq_cfg *cfg;
3708 unsigned long mmr_value;
3709 struct uv_IO_APIC_route_entry *entry;
3710 unsigned long flags;
3713 BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3717 err = assign_irq_vector(irq, cfg, eligible_cpu);
3721 spin_lock_irqsave(&vector_lock, flags);
3722 set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3724 spin_unlock_irqrestore(&vector_lock, flags);
3727 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3728 entry->vector = cfg->vector;
3729 entry->delivery_mode = apic->irq_delivery_mode;
3730 entry->dest_mode = apic->irq_dest_mode;
3731 entry->polarity = 0;
3734 entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
3736 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3737 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3743 * Disable the specified MMR located on the specified blade so that MSIs are
3744 * longer allowed to be sent.
3746 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3748 unsigned long mmr_value;
3749 struct uv_IO_APIC_route_entry *entry;
3752 BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3755 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3758 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3759 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3761 #endif /* CONFIG_X86_64 */
3763 int __init io_apic_get_redir_entries (int ioapic)
3765 union IO_APIC_reg_01 reg_01;
3766 unsigned long flags;
3768 spin_lock_irqsave(&ioapic_lock, flags);
3769 reg_01.raw = io_apic_read(ioapic, 1);
3770 spin_unlock_irqrestore(&ioapic_lock, flags);
3772 return reg_01.bits.entries;
3775 void __init probe_nr_irqs_gsi(void)
3779 nr = acpi_probe_gsi();
3780 if (nr > nr_irqs_gsi) {
3783 /* for acpi=off or acpi is not compiled in */
3787 for (idx = 0; idx < nr_ioapics; idx++)
3788 nr += io_apic_get_redir_entries(idx) + 1;
3790 if (nr > nr_irqs_gsi)
3794 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3797 #ifdef CONFIG_SPARSE_IRQ
3798 int __init arch_probe_nr_irqs(void)
3802 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3803 nr_irqs = NR_VECTORS * nr_cpu_ids;
3805 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3806 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3808 * for MSI and HT dyn irq
3810 nr += nr_irqs_gsi * 16;
3819 static int __io_apic_set_pci_routing(struct device *dev, int irq,
3820 struct io_apic_irq_attr *irq_attr)
3822 struct irq_desc *desc;
3823 struct irq_cfg *cfg;
3826 int trigger, polarity;
3828 ioapic = irq_attr->ioapic;
3829 if (!IO_APIC_IRQ(irq)) {
3830 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3836 node = dev_to_node(dev);
3838 node = cpu_to_node(boot_cpu_id);
3840 desc = irq_to_desc_alloc_node(irq, node);
3842 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3846 pin = irq_attr->ioapic_pin;
3847 trigger = irq_attr->trigger;
3848 polarity = irq_attr->polarity;
3851 * IRQs < 16 are already in the irq_2_pin[] map
3853 if (irq >= NR_IRQS_LEGACY) {
3854 cfg = desc->chip_data;
3855 if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) {
3856 printk(KERN_INFO "can not add pin %d for irq %d\n",
3862 setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity);
3867 int io_apic_set_pci_routing(struct device *dev, int irq,
3868 struct io_apic_irq_attr *irq_attr)
3872 * Avoid pin reprogramming. PRTs typically include entries
3873 * with redundant pin->gsi mappings (but unique PCI devices);
3874 * we only program the IOAPIC on the first.
3876 ioapic = irq_attr->ioapic;
3877 pin = irq_attr->ioapic_pin;
3878 if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) {
3879 pr_debug("Pin %d-%d already programmed\n",
3880 mp_ioapics[ioapic].apicid, pin);
3883 set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed);
3885 return __io_apic_set_pci_routing(dev, irq, irq_attr);
3888 /* --------------------------------------------------------------------------
3889 ACPI-based IOAPIC Configuration
3890 -------------------------------------------------------------------------- */
3894 #ifdef CONFIG_X86_32
3895 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3897 union IO_APIC_reg_00 reg_00;
3898 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3900 unsigned long flags;
3904 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3905 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3906 * supports up to 16 on one shared APIC bus.
3908 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3909 * advantage of new APIC bus architecture.
3912 if (physids_empty(apic_id_map))
3913 apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
3915 spin_lock_irqsave(&ioapic_lock, flags);
3916 reg_00.raw = io_apic_read(ioapic, 0);
3917 spin_unlock_irqrestore(&ioapic_lock, flags);
3919 if (apic_id >= get_physical_broadcast()) {
3920 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3921 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3922 apic_id = reg_00.bits.ID;
3926 * Every APIC in a system must have a unique ID or we get lots of nice
3927 * 'stuck on smp_invalidate_needed IPI wait' messages.
3929 if (apic->check_apicid_used(apic_id_map, apic_id)) {
3931 for (i = 0; i < get_physical_broadcast(); i++) {
3932 if (!apic->check_apicid_used(apic_id_map, i))
3936 if (i == get_physical_broadcast())
3937 panic("Max apic_id exceeded!\n");
3939 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3940 "trying %d\n", ioapic, apic_id, i);
3945 tmp = apic->apicid_to_cpu_present(apic_id);
3946 physids_or(apic_id_map, apic_id_map, tmp);
3948 if (reg_00.bits.ID != apic_id) {
3949 reg_00.bits.ID = apic_id;
3951 spin_lock_irqsave(&ioapic_lock, flags);
3952 io_apic_write(ioapic, 0, reg_00.raw);
3953 reg_00.raw = io_apic_read(ioapic, 0);
3954 spin_unlock_irqrestore(&ioapic_lock, flags);
3957 if (reg_00.bits.ID != apic_id) {
3958 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3963 apic_printk(APIC_VERBOSE, KERN_INFO
3964 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3970 int __init io_apic_get_version(int ioapic)
3972 union IO_APIC_reg_01 reg_01;
3973 unsigned long flags;
3975 spin_lock_irqsave(&ioapic_lock, flags);
3976 reg_01.raw = io_apic_read(ioapic, 1);
3977 spin_unlock_irqrestore(&ioapic_lock, flags);
3979 return reg_01.bits.version;
3982 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3986 if (skip_ioapic_setup)
3989 for (i = 0; i < mp_irq_entries; i++)
3990 if (mp_irqs[i].irqtype == mp_INT &&
3991 mp_irqs[i].srcbusirq == bus_irq)
3993 if (i >= mp_irq_entries)
3996 *trigger = irq_trigger(i);
3997 *polarity = irq_polarity(i);
4001 #endif /* CONFIG_ACPI */
4004 * This function currently is only a helper for the i386 smp boot process where
4005 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4006 * so mask in all cases should simply be apic->target_cpus()
4009 void __init setup_ioapic_dest(void)
4011 int pin, ioapic = 0, irq, irq_entry;
4012 struct irq_desc *desc;
4013 const struct cpumask *mask;
4015 if (skip_ioapic_setup == 1)
4019 if (!acpi_disabled && acpi_ioapic) {
4020 ioapic = mp_find_ioapic(0);
4026 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4027 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4028 if (irq_entry == -1)
4030 irq = pin_2_irq(irq_entry, ioapic, pin);
4032 desc = irq_to_desc(irq);
4035 * Honour affinities which have been set in early boot
4038 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4039 mask = desc->affinity;
4041 mask = apic->target_cpus();
4043 if (intr_remapping_enabled)
4044 set_ir_ioapic_affinity_irq_desc(desc, mask);
4046 set_ioapic_affinity_irq_desc(desc, mask);
4052 #define IOAPIC_RESOURCE_NAME_SIZE 11
4054 static struct resource *ioapic_resources;
4056 static struct resource * __init ioapic_setup_resources(int nr_ioapics)
4059 struct resource *res;
4063 if (nr_ioapics <= 0)
4066 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4069 mem = alloc_bootmem(n);
4072 mem += sizeof(struct resource) * nr_ioapics;
4074 for (i = 0; i < nr_ioapics; i++) {
4076 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4077 sprintf(mem, "IOAPIC %u", i);
4078 mem += IOAPIC_RESOURCE_NAME_SIZE;
4081 ioapic_resources = res;
4086 void __init ioapic_init_mappings(void)
4088 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4089 struct resource *ioapic_res;
4092 ioapic_res = ioapic_setup_resources(nr_ioapics);
4093 for (i = 0; i < nr_ioapics; i++) {
4094 if (smp_found_config) {
4095 ioapic_phys = mp_ioapics[i].apicaddr;
4096 #ifdef CONFIG_X86_32
4099 "WARNING: bogus zero IO-APIC "
4100 "address found in MPTABLE, "
4101 "disabling IO/APIC support!\n");
4102 smp_found_config = 0;
4103 skip_ioapic_setup = 1;
4104 goto fake_ioapic_page;
4108 #ifdef CONFIG_X86_32
4111 ioapic_phys = (unsigned long)
4112 alloc_bootmem_pages(PAGE_SIZE);
4113 ioapic_phys = __pa(ioapic_phys);
4115 set_fixmap_nocache(idx, ioapic_phys);
4116 apic_printk(APIC_VERBOSE,
4117 "mapped IOAPIC to %08lx (%08lx)\n",
4118 __fix_to_virt(idx), ioapic_phys);
4121 ioapic_res->start = ioapic_phys;
4122 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4127 static int __init ioapic_insert_resources(void)
4130 struct resource *r = ioapic_resources;
4133 if (nr_ioapics > 0) {
4135 "IO APIC resources couldn't be allocated.\n");
4141 for (i = 0; i < nr_ioapics; i++) {
4142 insert_resource(&iomem_resource, r);
4149 /* Insert the IO APIC resources after PCI initialization has occured to handle
4150 * IO APICS that are mapped in on a BAR in PCI space. */
4151 late_initcall(ioapic_insert_resources);