2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
51 #include <asm/proto.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/hw_irq.h>
63 #include <asm/uv/uv_hub.h>
64 #include <asm/uv/uv_irq.h>
68 #define __apicdebuginit(type) static type __init
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug = -1;
76 static DEFINE_SPINLOCK(ioapic_lock);
77 static DEFINE_SPINLOCK(vector_lock);
80 * # of IRQ routing registers
82 int nr_ioapic_registers[MAX_IO_APICS];
84 /* I/O APIC entries */
85 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
88 /* MP IRQ source entries */
89 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
91 /* # of MP IRQ source entries */
94 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
95 int mp_bus_id_to_type[MAX_MP_BUSSES];
98 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
100 int skip_ioapic_setup;
102 void arch_disable_smp_support(void)
106 noioapicreroute = -1;
108 skip_ioapic_setup = 1;
111 static int __init parse_noapic(char *str)
113 /* disable IO-APIC */
114 arch_disable_smp_support();
117 early_param("noapic", parse_noapic);
122 * This is performance-critical, we want to do it O(1)
124 * the indexing order of this array favors 1:1 mappings
125 * between pins and IRQs.
128 struct irq_pin_list {
130 struct irq_pin_list *next;
133 static struct irq_pin_list *get_one_free_irq_2_pin(int cpu)
135 struct irq_pin_list *pin;
138 node = cpu_to_node(cpu);
140 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
146 struct irq_pin_list *irq_2_pin;
147 cpumask_var_t domain;
148 cpumask_var_t old_domain;
149 unsigned move_cleanup_count;
151 u8 move_in_progress : 1;
152 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
153 u8 move_desc_pending : 1;
157 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
158 #ifdef CONFIG_SPARSE_IRQ
159 static struct irq_cfg irq_cfgx[] = {
161 static struct irq_cfg irq_cfgx[NR_IRQS] = {
163 [0] = { .vector = IRQ0_VECTOR, },
164 [1] = { .vector = IRQ1_VECTOR, },
165 [2] = { .vector = IRQ2_VECTOR, },
166 [3] = { .vector = IRQ3_VECTOR, },
167 [4] = { .vector = IRQ4_VECTOR, },
168 [5] = { .vector = IRQ5_VECTOR, },
169 [6] = { .vector = IRQ6_VECTOR, },
170 [7] = { .vector = IRQ7_VECTOR, },
171 [8] = { .vector = IRQ8_VECTOR, },
172 [9] = { .vector = IRQ9_VECTOR, },
173 [10] = { .vector = IRQ10_VECTOR, },
174 [11] = { .vector = IRQ11_VECTOR, },
175 [12] = { .vector = IRQ12_VECTOR, },
176 [13] = { .vector = IRQ13_VECTOR, },
177 [14] = { .vector = IRQ14_VECTOR, },
178 [15] = { .vector = IRQ15_VECTOR, },
181 int __init arch_early_irq_init(void)
184 struct irq_desc *desc;
189 count = ARRAY_SIZE(irq_cfgx);
191 for (i = 0; i < count; i++) {
192 desc = irq_to_desc(i);
193 desc->chip_data = &cfg[i];
194 alloc_bootmem_cpumask_var(&cfg[i].domain);
195 alloc_bootmem_cpumask_var(&cfg[i].old_domain);
196 if (i < NR_IRQS_LEGACY)
197 cpumask_setall(cfg[i].domain);
203 #ifdef CONFIG_SPARSE_IRQ
204 static struct irq_cfg *irq_cfg(unsigned int irq)
206 struct irq_cfg *cfg = NULL;
207 struct irq_desc *desc;
209 desc = irq_to_desc(irq);
211 cfg = desc->chip_data;
216 static struct irq_cfg *get_one_free_irq_cfg(int cpu)
221 node = cpu_to_node(cpu);
223 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
225 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
228 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
230 free_cpumask_var(cfg->domain);
234 cpumask_clear(cfg->domain);
235 cpumask_clear(cfg->old_domain);
242 int arch_init_chip_data(struct irq_desc *desc, int cpu)
246 cfg = desc->chip_data;
248 desc->chip_data = get_one_free_irq_cfg(cpu);
249 if (!desc->chip_data) {
250 printk(KERN_ERR "can not alloc irq_cfg\n");
258 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
261 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu)
263 struct irq_pin_list *old_entry, *head, *tail, *entry;
265 cfg->irq_2_pin = NULL;
266 old_entry = old_cfg->irq_2_pin;
270 entry = get_one_free_irq_2_pin(cpu);
274 entry->apic = old_entry->apic;
275 entry->pin = old_entry->pin;
278 old_entry = old_entry->next;
280 entry = get_one_free_irq_2_pin(cpu);
288 /* still use the old one */
291 entry->apic = old_entry->apic;
292 entry->pin = old_entry->pin;
295 old_entry = old_entry->next;
299 cfg->irq_2_pin = head;
302 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
304 struct irq_pin_list *entry, *next;
306 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
309 entry = old_cfg->irq_2_pin;
316 old_cfg->irq_2_pin = NULL;
319 void arch_init_copy_chip_data(struct irq_desc *old_desc,
320 struct irq_desc *desc, int cpu)
323 struct irq_cfg *old_cfg;
325 cfg = get_one_free_irq_cfg(cpu);
330 desc->chip_data = cfg;
332 old_cfg = old_desc->chip_data;
334 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
336 init_copy_irq_2_pin(old_cfg, cfg, cpu);
339 static void free_irq_cfg(struct irq_cfg *old_cfg)
344 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
346 struct irq_cfg *old_cfg, *cfg;
348 old_cfg = old_desc->chip_data;
349 cfg = desc->chip_data;
355 free_irq_2_pin(old_cfg, cfg);
356 free_irq_cfg(old_cfg);
357 old_desc->chip_data = NULL;
362 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
364 struct irq_cfg *cfg = desc->chip_data;
366 if (!cfg->move_in_progress) {
367 /* it means that domain is not changed */
368 if (!cpumask_intersects(desc->affinity, mask))
369 cfg->move_desc_pending = 1;
375 static struct irq_cfg *irq_cfg(unsigned int irq)
377 return irq < nr_irqs ? irq_cfgx + irq : NULL;
382 #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
384 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
391 unsigned int unused[3];
393 unsigned int unused2[11];
397 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
399 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
400 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
403 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
405 struct io_apic __iomem *io_apic = io_apic_base(apic);
406 writel(vector, &io_apic->eoi);
409 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
411 struct io_apic __iomem *io_apic = io_apic_base(apic);
412 writel(reg, &io_apic->index);
413 return readl(&io_apic->data);
416 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
418 struct io_apic __iomem *io_apic = io_apic_base(apic);
419 writel(reg, &io_apic->index);
420 writel(value, &io_apic->data);
424 * Re-write a value: to be used for read-modify-write
425 * cycles where the read already set up the index register.
427 * Older SiS APIC requires we rewrite the index register
429 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
431 struct io_apic __iomem *io_apic = io_apic_base(apic);
434 writel(reg, &io_apic->index);
435 writel(value, &io_apic->data);
438 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
440 struct irq_pin_list *entry;
443 spin_lock_irqsave(&ioapic_lock, flags);
444 entry = cfg->irq_2_pin;
452 reg = io_apic_read(entry->apic, 0x10 + pin*2);
453 /* Is the remote IRR bit set? */
454 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
455 spin_unlock_irqrestore(&ioapic_lock, flags);
462 spin_unlock_irqrestore(&ioapic_lock, flags);
468 struct { u32 w1, w2; };
469 struct IO_APIC_route_entry entry;
472 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
474 union entry_union eu;
476 spin_lock_irqsave(&ioapic_lock, flags);
477 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
478 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
479 spin_unlock_irqrestore(&ioapic_lock, flags);
484 * When we write a new IO APIC routing entry, we need to write the high
485 * word first! If the mask bit in the low word is clear, we will enable
486 * the interrupt, and we need to make sure the entry is fully populated
487 * before that happens.
490 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
492 union entry_union eu;
494 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
495 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
498 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
501 spin_lock_irqsave(&ioapic_lock, flags);
502 __ioapic_write_entry(apic, pin, e);
503 spin_unlock_irqrestore(&ioapic_lock, flags);
507 * When we mask an IO APIC routing entry, we need to write the low
508 * word first, in order to set the mask bit before we change the
511 static void ioapic_mask_entry(int apic, int pin)
514 union entry_union eu = { .entry.mask = 1 };
516 spin_lock_irqsave(&ioapic_lock, flags);
517 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
518 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
519 spin_unlock_irqrestore(&ioapic_lock, flags);
523 static void send_cleanup_vector(struct irq_cfg *cfg)
525 cpumask_var_t cleanup_mask;
527 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
529 cfg->move_cleanup_count = 0;
530 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
531 cfg->move_cleanup_count++;
532 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
533 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
535 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
536 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
537 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
538 free_cpumask_var(cleanup_mask);
540 cfg->move_in_progress = 0;
543 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
546 struct irq_pin_list *entry;
547 u8 vector = cfg->vector;
549 entry = cfg->irq_2_pin;
559 * With interrupt-remapping, destination information comes
560 * from interrupt-remapping table entry.
562 if (!irq_remapped(irq))
563 io_apic_write(apic, 0x11 + pin*2, dest);
564 reg = io_apic_read(apic, 0x10 + pin*2);
565 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
567 io_apic_modify(apic, 0x10 + pin*2, reg);
575 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
578 * Either sets desc->affinity to a valid value, and returns
579 * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
580 * leaves desc->affinity untouched.
583 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
588 if (!cpumask_intersects(mask, cpu_online_mask))
592 cfg = desc->chip_data;
593 if (assign_irq_vector(irq, cfg, mask))
596 /* check that before desc->addinity get updated */
597 set_extra_move_desc(desc, mask);
599 cpumask_copy(desc->affinity, mask);
601 return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
605 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
613 cfg = desc->chip_data;
615 spin_lock_irqsave(&ioapic_lock, flags);
616 dest = set_desc_affinity(desc, mask);
617 if (dest != BAD_APICID) {
618 /* Only the high 8 bits are valid. */
619 dest = SET_APIC_LOGICAL_ID(dest);
620 __target_IO_APIC_irq(irq, dest, cfg);
622 spin_unlock_irqrestore(&ioapic_lock, flags);
626 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
628 struct irq_desc *desc;
630 desc = irq_to_desc(irq);
632 set_ioapic_affinity_irq_desc(desc, mask);
634 #endif /* CONFIG_SMP */
637 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
638 * shared ISA-space IRQs, so we have to support them. We are super
639 * fast in the common case, and fast for shared ISA-space IRQs.
641 static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin)
643 struct irq_pin_list *entry;
645 entry = cfg->irq_2_pin;
647 entry = get_one_free_irq_2_pin(cpu);
649 printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
653 cfg->irq_2_pin = entry;
659 while (entry->next) {
660 /* not again, please */
661 if (entry->apic == apic && entry->pin == pin)
667 entry->next = get_one_free_irq_2_pin(cpu);
674 * Reroute an IRQ to a different pin.
676 static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu,
677 int oldapic, int oldpin,
678 int newapic, int newpin)
680 struct irq_pin_list *entry = cfg->irq_2_pin;
684 if (entry->apic == oldapic && entry->pin == oldpin) {
685 entry->apic = newapic;
688 /* every one is different, right? */
694 /* why? call replace before add? */
696 add_pin_to_irq_cpu(cfg, cpu, newapic, newpin);
699 static inline void io_apic_modify_irq(struct irq_cfg *cfg,
700 int mask_and, int mask_or,
701 void (*final)(struct irq_pin_list *entry))
704 struct irq_pin_list *entry;
706 for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
709 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
712 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
718 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
720 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
724 static void io_apic_sync(struct irq_pin_list *entry)
727 * Synchronize the IO-APIC and the CPU by doing
728 * a dummy read from the IO-APIC
730 struct io_apic __iomem *io_apic;
731 io_apic = io_apic_base(entry->apic);
732 readl(&io_apic->data);
735 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
737 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
739 #else /* CONFIG_X86_32 */
740 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
742 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL);
745 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
747 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
748 IO_APIC_REDIR_MASKED, NULL);
751 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
753 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
754 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
756 #endif /* CONFIG_X86_32 */
758 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
760 struct irq_cfg *cfg = desc->chip_data;
765 spin_lock_irqsave(&ioapic_lock, flags);
766 __mask_IO_APIC_irq(cfg);
767 spin_unlock_irqrestore(&ioapic_lock, flags);
770 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
772 struct irq_cfg *cfg = desc->chip_data;
775 spin_lock_irqsave(&ioapic_lock, flags);
776 __unmask_IO_APIC_irq(cfg);
777 spin_unlock_irqrestore(&ioapic_lock, flags);
780 static void mask_IO_APIC_irq(unsigned int irq)
782 struct irq_desc *desc = irq_to_desc(irq);
784 mask_IO_APIC_irq_desc(desc);
786 static void unmask_IO_APIC_irq(unsigned int irq)
788 struct irq_desc *desc = irq_to_desc(irq);
790 unmask_IO_APIC_irq_desc(desc);
793 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
795 struct IO_APIC_route_entry entry;
797 /* Check delivery_mode to be sure we're not clearing an SMI pin */
798 entry = ioapic_read_entry(apic, pin);
799 if (entry.delivery_mode == dest_SMI)
802 * Disable it in the IO-APIC irq-routing table:
804 ioapic_mask_entry(apic, pin);
807 static void clear_IO_APIC (void)
811 for (apic = 0; apic < nr_ioapics; apic++)
812 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
813 clear_IO_APIC_pin(apic, pin);
818 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
819 * specific CPU-side IRQs.
823 static int pirq_entries[MAX_PIRQS] = {
824 [0 ... MAX_PIRQS - 1] = -1
827 static int __init ioapic_pirq_setup(char *str)
830 int ints[MAX_PIRQS+1];
832 get_options(str, ARRAY_SIZE(ints), ints);
834 apic_printk(APIC_VERBOSE, KERN_INFO
835 "PIRQ redirection, working around broken MP-BIOS.\n");
837 if (ints[0] < MAX_PIRQS)
840 for (i = 0; i < max; i++) {
841 apic_printk(APIC_VERBOSE, KERN_DEBUG
842 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
844 * PIRQs are mapped upside down, usually.
846 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
851 __setup("pirq=", ioapic_pirq_setup);
852 #endif /* CONFIG_X86_32 */
854 #ifdef CONFIG_INTR_REMAP
855 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
858 struct IO_APIC_route_entry **ioapic_entries;
860 ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
865 for (apic = 0; apic < nr_ioapics; apic++) {
866 ioapic_entries[apic] =
867 kzalloc(sizeof(struct IO_APIC_route_entry) *
868 nr_ioapic_registers[apic], GFP_ATOMIC);
869 if (!ioapic_entries[apic])
873 return ioapic_entries;
877 kfree(ioapic_entries[apic]);
878 kfree(ioapic_entries);
884 * Saves all the IO-APIC RTE's
886 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
893 for (apic = 0; apic < nr_ioapics; apic++) {
894 if (!ioapic_entries[apic])
897 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
898 ioapic_entries[apic][pin] =
899 ioapic_read_entry(apic, pin);
906 * Mask all IO APIC entries.
908 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
915 for (apic = 0; apic < nr_ioapics; apic++) {
916 if (!ioapic_entries[apic])
919 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
920 struct IO_APIC_route_entry entry;
922 entry = ioapic_entries[apic][pin];
925 ioapic_write_entry(apic, pin, entry);
932 * Restore IO APIC entries which was saved in ioapic_entries.
934 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
941 for (apic = 0; apic < nr_ioapics; apic++) {
942 if (!ioapic_entries[apic])
945 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
946 ioapic_write_entry(apic, pin,
947 ioapic_entries[apic][pin]);
952 void reinit_intr_remapped_IO_APIC(int intr_remapping,
953 struct IO_APIC_route_entry **ioapic_entries)
957 * for now plain restore of previous settings.
958 * TBD: In the case of OS enabling interrupt-remapping,
959 * IO-APIC RTE's need to be setup to point to interrupt-remapping
960 * table entries. for now, do a plain restore, and wait for
961 * the setup_IO_APIC_irqs() to do proper initialization.
963 restore_IO_APIC_setup(ioapic_entries);
966 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
970 for (apic = 0; apic < nr_ioapics; apic++)
971 kfree(ioapic_entries[apic]);
973 kfree(ioapic_entries);
978 * Find the IRQ entry number of a certain pin.
980 static int find_irq_entry(int apic, int pin, int type)
984 for (i = 0; i < mp_irq_entries; i++)
985 if (mp_irqs[i].irqtype == type &&
986 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
987 mp_irqs[i].dstapic == MP_APIC_ALL) &&
988 mp_irqs[i].dstirq == pin)
995 * Find the pin to which IRQ[irq] (ISA) is connected
997 static int __init find_isa_irq_pin(int irq, int type)
1001 for (i = 0; i < mp_irq_entries; i++) {
1002 int lbus = mp_irqs[i].srcbus;
1004 if (test_bit(lbus, mp_bus_not_pci) &&
1005 (mp_irqs[i].irqtype == type) &&
1006 (mp_irqs[i].srcbusirq == irq))
1008 return mp_irqs[i].dstirq;
1013 static int __init find_isa_irq_apic(int irq, int type)
1017 for (i = 0; i < mp_irq_entries; i++) {
1018 int lbus = mp_irqs[i].srcbus;
1020 if (test_bit(lbus, mp_bus_not_pci) &&
1021 (mp_irqs[i].irqtype == type) &&
1022 (mp_irqs[i].srcbusirq == irq))
1025 if (i < mp_irq_entries) {
1027 for(apic = 0; apic < nr_ioapics; apic++) {
1028 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
1037 * Find a specific PCI IRQ entry.
1038 * Not an __init, possibly needed by modules
1040 static int pin_2_irq(int idx, int apic, int pin);
1042 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1044 int apic, i, best_guess = -1;
1046 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1048 if (test_bit(bus, mp_bus_not_pci)) {
1049 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1052 for (i = 0; i < mp_irq_entries; i++) {
1053 int lbus = mp_irqs[i].srcbus;
1055 for (apic = 0; apic < nr_ioapics; apic++)
1056 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1057 mp_irqs[i].dstapic == MP_APIC_ALL)
1060 if (!test_bit(lbus, mp_bus_not_pci) &&
1061 !mp_irqs[i].irqtype &&
1063 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1064 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1066 if (!(apic || IO_APIC_IRQ(irq)))
1069 if (pin == (mp_irqs[i].srcbusirq & 3))
1072 * Use the first all-but-pin matching entry as a
1073 * best-guess fuzzy result for broken mptables.
1082 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1084 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1086 * EISA Edge/Level control register, ELCR
1088 static int EISA_ELCR(unsigned int irq)
1090 if (irq < NR_IRQS_LEGACY) {
1091 unsigned int port = 0x4d0 + (irq >> 3);
1092 return (inb(port) >> (irq & 7)) & 1;
1094 apic_printk(APIC_VERBOSE, KERN_INFO
1095 "Broken MPtable reports ISA irq %d\n", irq);
1101 /* ISA interrupts are always polarity zero edge triggered,
1102 * when listed as conforming in the MP table. */
1104 #define default_ISA_trigger(idx) (0)
1105 #define default_ISA_polarity(idx) (0)
1107 /* EISA interrupts are always polarity zero and can be edge or level
1108 * trigger depending on the ELCR value. If an interrupt is listed as
1109 * EISA conforming in the MP table, that means its trigger type must
1110 * be read in from the ELCR */
1112 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
1113 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
1115 /* PCI interrupts are always polarity one level triggered,
1116 * when listed as conforming in the MP table. */
1118 #define default_PCI_trigger(idx) (1)
1119 #define default_PCI_polarity(idx) (1)
1121 /* MCA interrupts are always polarity zero level triggered,
1122 * when listed as conforming in the MP table. */
1124 #define default_MCA_trigger(idx) (1)
1125 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
1127 static int MPBIOS_polarity(int idx)
1129 int bus = mp_irqs[idx].srcbus;
1133 * Determine IRQ line polarity (high active or low active):
1135 switch (mp_irqs[idx].irqflag & 3)
1137 case 0: /* conforms, ie. bus-type dependent polarity */
1138 if (test_bit(bus, mp_bus_not_pci))
1139 polarity = default_ISA_polarity(idx);
1141 polarity = default_PCI_polarity(idx);
1143 case 1: /* high active */
1148 case 2: /* reserved */
1150 printk(KERN_WARNING "broken BIOS!!\n");
1154 case 3: /* low active */
1159 default: /* invalid */
1161 printk(KERN_WARNING "broken BIOS!!\n");
1169 static int MPBIOS_trigger(int idx)
1171 int bus = mp_irqs[idx].srcbus;
1175 * Determine IRQ trigger mode (edge or level sensitive):
1177 switch ((mp_irqs[idx].irqflag>>2) & 3)
1179 case 0: /* conforms, ie. bus-type dependent */
1180 if (test_bit(bus, mp_bus_not_pci))
1181 trigger = default_ISA_trigger(idx);
1183 trigger = default_PCI_trigger(idx);
1184 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1185 switch (mp_bus_id_to_type[bus]) {
1186 case MP_BUS_ISA: /* ISA pin */
1188 /* set before the switch */
1191 case MP_BUS_EISA: /* EISA pin */
1193 trigger = default_EISA_trigger(idx);
1196 case MP_BUS_PCI: /* PCI pin */
1198 /* set before the switch */
1201 case MP_BUS_MCA: /* MCA pin */
1203 trigger = default_MCA_trigger(idx);
1208 printk(KERN_WARNING "broken BIOS!!\n");
1220 case 2: /* reserved */
1222 printk(KERN_WARNING "broken BIOS!!\n");
1231 default: /* invalid */
1233 printk(KERN_WARNING "broken BIOS!!\n");
1241 static inline int irq_polarity(int idx)
1243 return MPBIOS_polarity(idx);
1246 static inline int irq_trigger(int idx)
1248 return MPBIOS_trigger(idx);
1251 int (*ioapic_renumber_irq)(int ioapic, int irq);
1252 static int pin_2_irq(int idx, int apic, int pin)
1255 int bus = mp_irqs[idx].srcbus;
1258 * Debugging check, we are in big trouble if this message pops up!
1260 if (mp_irqs[idx].dstirq != pin)
1261 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1263 if (test_bit(bus, mp_bus_not_pci)) {
1264 irq = mp_irqs[idx].srcbusirq;
1267 * PCI IRQs are mapped in order
1271 irq += nr_ioapic_registers[i++];
1274 * For MPS mode, so far only needed by ES7000 platform
1276 if (ioapic_renumber_irq)
1277 irq = ioapic_renumber_irq(apic, irq);
1280 #ifdef CONFIG_X86_32
1282 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1284 if ((pin >= 16) && (pin <= 23)) {
1285 if (pirq_entries[pin-16] != -1) {
1286 if (!pirq_entries[pin-16]) {
1287 apic_printk(APIC_VERBOSE, KERN_DEBUG
1288 "disabling PIRQ%d\n", pin-16);
1290 irq = pirq_entries[pin-16];
1291 apic_printk(APIC_VERBOSE, KERN_DEBUG
1292 "using PIRQ%d -> IRQ %d\n",
1302 void lock_vector_lock(void)
1304 /* Used to the online set of cpus does not change
1305 * during assign_irq_vector.
1307 spin_lock(&vector_lock);
1310 void unlock_vector_lock(void)
1312 spin_unlock(&vector_lock);
1316 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1319 * NOTE! The local APIC isn't very good at handling
1320 * multiple interrupts at the same interrupt level.
1321 * As the interrupt level is determined by taking the
1322 * vector number and shifting that right by 4, we
1323 * want to spread these out a bit so that they don't
1324 * all fall in the same interrupt level.
1326 * Also, we've got to be careful not to trash gate
1327 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1329 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1330 unsigned int old_vector;
1332 cpumask_var_t tmp_mask;
1334 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1337 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1340 old_vector = cfg->vector;
1342 cpumask_and(tmp_mask, mask, cpu_online_mask);
1343 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1344 if (!cpumask_empty(tmp_mask)) {
1345 free_cpumask_var(tmp_mask);
1350 /* Only try and allocate irqs on cpus that are present */
1352 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1356 apic->vector_allocation_domain(cpu, tmp_mask);
1358 vector = current_vector;
1359 offset = current_offset;
1362 if (vector >= first_system_vector) {
1363 /* If out of vectors on large boxen, must share them. */
1364 offset = (offset + 1) % 8;
1365 vector = FIRST_DEVICE_VECTOR + offset;
1367 if (unlikely(current_vector == vector))
1370 if (test_bit(vector, used_vectors))
1373 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1374 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1377 current_vector = vector;
1378 current_offset = offset;
1380 cfg->move_in_progress = 1;
1381 cpumask_copy(cfg->old_domain, cfg->domain);
1383 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1384 per_cpu(vector_irq, new_cpu)[vector] = irq;
1385 cfg->vector = vector;
1386 cpumask_copy(cfg->domain, tmp_mask);
1390 free_cpumask_var(tmp_mask);
1395 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1398 unsigned long flags;
1400 spin_lock_irqsave(&vector_lock, flags);
1401 err = __assign_irq_vector(irq, cfg, mask);
1402 spin_unlock_irqrestore(&vector_lock, flags);
1406 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1410 BUG_ON(!cfg->vector);
1412 vector = cfg->vector;
1413 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1414 per_cpu(vector_irq, cpu)[vector] = -1;
1417 cpumask_clear(cfg->domain);
1419 if (likely(!cfg->move_in_progress))
1421 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1422 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1424 if (per_cpu(vector_irq, cpu)[vector] != irq)
1426 per_cpu(vector_irq, cpu)[vector] = -1;
1430 cfg->move_in_progress = 0;
1433 void __setup_vector_irq(int cpu)
1435 /* Initialize vector_irq on a new cpu */
1436 /* This function must be called with vector_lock held */
1438 struct irq_cfg *cfg;
1439 struct irq_desc *desc;
1441 /* Mark the inuse vectors */
1442 for_each_irq_desc(irq, desc) {
1443 cfg = desc->chip_data;
1444 if (!cpumask_test_cpu(cpu, cfg->domain))
1446 vector = cfg->vector;
1447 per_cpu(vector_irq, cpu)[vector] = irq;
1449 /* Mark the free vectors */
1450 for (vector = 0; vector < NR_VECTORS; ++vector) {
1451 irq = per_cpu(vector_irq, cpu)[vector];
1456 if (!cpumask_test_cpu(cpu, cfg->domain))
1457 per_cpu(vector_irq, cpu)[vector] = -1;
1461 static struct irq_chip ioapic_chip;
1462 static struct irq_chip ir_ioapic_chip;
1464 #define IOAPIC_AUTO -1
1465 #define IOAPIC_EDGE 0
1466 #define IOAPIC_LEVEL 1
1468 #ifdef CONFIG_X86_32
1469 static inline int IO_APIC_irq_trigger(int irq)
1473 for (apic = 0; apic < nr_ioapics; apic++) {
1474 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1475 idx = find_irq_entry(apic, pin, mp_INT);
1476 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1477 return irq_trigger(idx);
1481 * nonexistent IRQs are edge default
1486 static inline int IO_APIC_irq_trigger(int irq)
1492 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1495 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1496 trigger == IOAPIC_LEVEL)
1497 desc->status |= IRQ_LEVEL;
1499 desc->status &= ~IRQ_LEVEL;
1501 if (irq_remapped(irq)) {
1502 desc->status |= IRQ_MOVE_PCNTXT;
1504 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1508 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1509 handle_edge_irq, "edge");
1513 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1514 trigger == IOAPIC_LEVEL)
1515 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1519 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1520 handle_edge_irq, "edge");
1523 int setup_ioapic_entry(int apic_id, int irq,
1524 struct IO_APIC_route_entry *entry,
1525 unsigned int destination, int trigger,
1526 int polarity, int vector, int pin)
1529 * add it to the IO-APIC irq-routing table:
1531 memset(entry,0,sizeof(*entry));
1533 if (intr_remapping_enabled) {
1534 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1536 struct IR_IO_APIC_route_entry *ir_entry =
1537 (struct IR_IO_APIC_route_entry *) entry;
1541 panic("No mapping iommu for ioapic %d\n", apic_id);
1543 index = alloc_irte(iommu, irq, 1);
1545 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1547 memset(&irte, 0, sizeof(irte));
1550 irte.dst_mode = apic->irq_dest_mode;
1552 * Trigger mode in the IRTE will always be edge, and the
1553 * actual level or edge trigger will be setup in the IO-APIC
1554 * RTE. This will help simplify level triggered irq migration.
1555 * For more details, see the comments above explainig IO-APIC
1556 * irq migration in the presence of interrupt-remapping.
1558 irte.trigger_mode = 0;
1559 irte.dlvry_mode = apic->irq_delivery_mode;
1560 irte.vector = vector;
1561 irte.dest_id = IRTE_DEST(destination);
1563 modify_irte(irq, &irte);
1565 ir_entry->index2 = (index >> 15) & 0x1;
1567 ir_entry->format = 1;
1568 ir_entry->index = (index & 0x7fff);
1570 * IO-APIC RTE will be configured with virtual vector.
1571 * irq handler will do the explicit EOI to the io-apic.
1573 ir_entry->vector = pin;
1575 entry->delivery_mode = apic->irq_delivery_mode;
1576 entry->dest_mode = apic->irq_dest_mode;
1577 entry->dest = destination;
1578 entry->vector = vector;
1581 entry->mask = 0; /* enable IRQ */
1582 entry->trigger = trigger;
1583 entry->polarity = polarity;
1585 /* Mask level triggered irqs.
1586 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1593 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1594 int trigger, int polarity)
1596 struct irq_cfg *cfg;
1597 struct IO_APIC_route_entry entry;
1600 if (!IO_APIC_IRQ(irq))
1603 cfg = desc->chip_data;
1605 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1608 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1610 apic_printk(APIC_VERBOSE,KERN_DEBUG
1611 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1612 "IRQ %d Mode:%i Active:%i)\n",
1613 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1614 irq, trigger, polarity);
1617 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1618 dest, trigger, polarity, cfg->vector, pin)) {
1619 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1620 mp_ioapics[apic_id].apicid, pin);
1621 __clear_irq_vector(irq, cfg);
1625 ioapic_register_intr(irq, desc, trigger);
1626 if (irq < NR_IRQS_LEGACY)
1627 disable_8259A_irq(irq);
1629 ioapic_write_entry(apic_id, pin, entry);
1632 static void __init setup_IO_APIC_irqs(void)
1634 int apic_id, pin, idx, irq;
1636 struct irq_desc *desc;
1637 struct irq_cfg *cfg;
1638 int cpu = boot_cpu_id;
1640 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1642 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
1643 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1645 idx = find_irq_entry(apic_id, pin, mp_INT);
1649 apic_printk(APIC_VERBOSE,
1650 KERN_DEBUG " %d-%d",
1651 mp_ioapics[apic_id].apicid, pin);
1653 apic_printk(APIC_VERBOSE, " %d-%d",
1654 mp_ioapics[apic_id].apicid, pin);
1658 apic_printk(APIC_VERBOSE,
1659 " (apicid-pin) not connected\n");
1663 irq = pin_2_irq(idx, apic_id, pin);
1666 * Skip the timer IRQ if there's a quirk handler
1667 * installed and if it returns 1:
1669 if (apic->multi_timer_check &&
1670 apic->multi_timer_check(apic_id, irq))
1673 desc = irq_to_desc_alloc_cpu(irq, cpu);
1675 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1678 cfg = desc->chip_data;
1679 add_pin_to_irq_cpu(cfg, cpu, apic_id, pin);
1681 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1682 irq_trigger(idx), irq_polarity(idx));
1687 apic_printk(APIC_VERBOSE,
1688 " (apicid-pin) not connected\n");
1692 * Set up the timer pin, possibly with the 8259A-master behind.
1694 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1697 struct IO_APIC_route_entry entry;
1699 if (intr_remapping_enabled)
1702 memset(&entry, 0, sizeof(entry));
1705 * We use logical delivery to get the timer IRQ
1708 entry.dest_mode = apic->irq_dest_mode;
1709 entry.mask = 0; /* don't mask IRQ for edge */
1710 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1711 entry.delivery_mode = apic->irq_delivery_mode;
1714 entry.vector = vector;
1717 * The timer IRQ doesn't have to know that behind the
1718 * scene we may have a 8259A-master in AEOI mode ...
1720 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1723 * Add it to the IO-APIC irq-routing table:
1725 ioapic_write_entry(apic_id, pin, entry);
1729 __apicdebuginit(void) print_IO_APIC(void)
1732 union IO_APIC_reg_00 reg_00;
1733 union IO_APIC_reg_01 reg_01;
1734 union IO_APIC_reg_02 reg_02;
1735 union IO_APIC_reg_03 reg_03;
1736 unsigned long flags;
1737 struct irq_cfg *cfg;
1738 struct irq_desc *desc;
1741 if (apic_verbosity == APIC_QUIET)
1744 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1745 for (i = 0; i < nr_ioapics; i++)
1746 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1747 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1750 * We are a bit conservative about what we expect. We have to
1751 * know about every hardware change ASAP.
1753 printk(KERN_INFO "testing the IO APIC.......................\n");
1755 for (apic = 0; apic < nr_ioapics; apic++) {
1757 spin_lock_irqsave(&ioapic_lock, flags);
1758 reg_00.raw = io_apic_read(apic, 0);
1759 reg_01.raw = io_apic_read(apic, 1);
1760 if (reg_01.bits.version >= 0x10)
1761 reg_02.raw = io_apic_read(apic, 2);
1762 if (reg_01.bits.version >= 0x20)
1763 reg_03.raw = io_apic_read(apic, 3);
1764 spin_unlock_irqrestore(&ioapic_lock, flags);
1767 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1768 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1769 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1770 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1771 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1773 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1774 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1776 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1777 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1780 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1781 * but the value of reg_02 is read as the previous read register
1782 * value, so ignore it if reg_02 == reg_01.
1784 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1785 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1786 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1790 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1791 * or reg_03, but the value of reg_0[23] is read as the previous read
1792 * register value, so ignore it if reg_03 == reg_0[12].
1794 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1795 reg_03.raw != reg_01.raw) {
1796 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1797 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1800 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1802 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1803 " Stat Dmod Deli Vect: \n");
1805 for (i = 0; i <= reg_01.bits.entries; i++) {
1806 struct IO_APIC_route_entry entry;
1808 entry = ioapic_read_entry(apic, i);
1810 printk(KERN_DEBUG " %02x %03X ",
1815 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1820 entry.delivery_status,
1822 entry.delivery_mode,
1827 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1828 for_each_irq_desc(irq, desc) {
1829 struct irq_pin_list *entry;
1831 cfg = desc->chip_data;
1832 entry = cfg->irq_2_pin;
1835 printk(KERN_DEBUG "IRQ%d ", irq);
1837 printk("-> %d:%d", entry->apic, entry->pin);
1840 entry = entry->next;
1845 printk(KERN_INFO ".................................... done.\n");
1850 __apicdebuginit(void) print_APIC_bitfield(int base)
1855 if (apic_verbosity == APIC_QUIET)
1858 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1859 for (i = 0; i < 8; i++) {
1860 v = apic_read(base + i*0x10);
1861 for (j = 0; j < 32; j++) {
1871 __apicdebuginit(void) print_local_APIC(void *dummy)
1873 unsigned int v, ver, maxlvt;
1876 if (apic_verbosity == APIC_QUIET)
1879 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1880 smp_processor_id(), hard_smp_processor_id());
1881 v = apic_read(APIC_ID);
1882 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1883 v = apic_read(APIC_LVR);
1884 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1885 ver = GET_APIC_VERSION(v);
1886 maxlvt = lapic_get_maxlvt();
1888 v = apic_read(APIC_TASKPRI);
1889 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1891 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1892 if (!APIC_XAPIC(ver)) {
1893 v = apic_read(APIC_ARBPRI);
1894 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1895 v & APIC_ARBPRI_MASK);
1897 v = apic_read(APIC_PROCPRI);
1898 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1902 * Remote read supported only in the 82489DX and local APIC for
1903 * Pentium processors.
1905 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1906 v = apic_read(APIC_RRR);
1907 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1910 v = apic_read(APIC_LDR);
1911 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1912 if (!x2apic_enabled()) {
1913 v = apic_read(APIC_DFR);
1914 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1916 v = apic_read(APIC_SPIV);
1917 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1919 printk(KERN_DEBUG "... APIC ISR field:\n");
1920 print_APIC_bitfield(APIC_ISR);
1921 printk(KERN_DEBUG "... APIC TMR field:\n");
1922 print_APIC_bitfield(APIC_TMR);
1923 printk(KERN_DEBUG "... APIC IRR field:\n");
1924 print_APIC_bitfield(APIC_IRR);
1926 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1927 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1928 apic_write(APIC_ESR, 0);
1930 v = apic_read(APIC_ESR);
1931 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1934 icr = apic_icr_read();
1935 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1936 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1938 v = apic_read(APIC_LVTT);
1939 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1941 if (maxlvt > 3) { /* PC is LVT#4. */
1942 v = apic_read(APIC_LVTPC);
1943 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1945 v = apic_read(APIC_LVT0);
1946 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1947 v = apic_read(APIC_LVT1);
1948 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1950 if (maxlvt > 2) { /* ERR is LVT#3. */
1951 v = apic_read(APIC_LVTERR);
1952 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1955 v = apic_read(APIC_TMICT);
1956 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1957 v = apic_read(APIC_TMCCT);
1958 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1959 v = apic_read(APIC_TDCR);
1960 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1964 __apicdebuginit(void) print_all_local_APICs(void)
1969 for_each_online_cpu(cpu)
1970 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1974 __apicdebuginit(void) print_PIC(void)
1977 unsigned long flags;
1979 if (apic_verbosity == APIC_QUIET)
1982 printk(KERN_DEBUG "\nprinting PIC contents\n");
1984 spin_lock_irqsave(&i8259A_lock, flags);
1986 v = inb(0xa1) << 8 | inb(0x21);
1987 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1989 v = inb(0xa0) << 8 | inb(0x20);
1990 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1994 v = inb(0xa0) << 8 | inb(0x20);
1998 spin_unlock_irqrestore(&i8259A_lock, flags);
2000 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
2002 v = inb(0x4d1) << 8 | inb(0x4d0);
2003 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
2006 __apicdebuginit(int) print_all_ICs(void)
2009 print_all_local_APICs();
2015 fs_initcall(print_all_ICs);
2018 /* Where if anywhere is the i8259 connect in external int mode */
2019 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
2021 void __init enable_IO_APIC(void)
2023 union IO_APIC_reg_01 reg_01;
2024 int i8259_apic, i8259_pin;
2026 unsigned long flags;
2029 * The number of IO-APIC IRQ registers (== #pins):
2031 for (apic = 0; apic < nr_ioapics; apic++) {
2032 spin_lock_irqsave(&ioapic_lock, flags);
2033 reg_01.raw = io_apic_read(apic, 1);
2034 spin_unlock_irqrestore(&ioapic_lock, flags);
2035 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
2037 for(apic = 0; apic < nr_ioapics; apic++) {
2039 /* See if any of the pins is in ExtINT mode */
2040 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
2041 struct IO_APIC_route_entry entry;
2042 entry = ioapic_read_entry(apic, pin);
2044 /* If the interrupt line is enabled and in ExtInt mode
2045 * I have found the pin where the i8259 is connected.
2047 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
2048 ioapic_i8259.apic = apic;
2049 ioapic_i8259.pin = pin;
2055 /* Look to see what if the MP table has reported the ExtINT */
2056 /* If we could not find the appropriate pin by looking at the ioapic
2057 * the i8259 probably is not connected the ioapic but give the
2058 * mptable a chance anyway.
2060 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
2061 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
2062 /* Trust the MP table if nothing is setup in the hardware */
2063 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
2064 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
2065 ioapic_i8259.pin = i8259_pin;
2066 ioapic_i8259.apic = i8259_apic;
2068 /* Complain if the MP table and the hardware disagree */
2069 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
2070 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
2072 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
2076 * Do not trust the IO-APIC being empty at bootup
2082 * Not an __init, needed by the reboot code
2084 void disable_IO_APIC(void)
2087 * Clear the IO-APIC before rebooting:
2092 * If the i8259 is routed through an IOAPIC
2093 * Put that IOAPIC in virtual wire mode
2094 * so legacy interrupts can be delivered.
2096 * With interrupt-remapping, for now we will use virtual wire A mode,
2097 * as virtual wire B is little complex (need to configure both
2098 * IOAPIC RTE aswell as interrupt-remapping table entry).
2099 * As this gets called during crash dump, keep this simple for now.
2101 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
2102 struct IO_APIC_route_entry entry;
2104 memset(&entry, 0, sizeof(entry));
2105 entry.mask = 0; /* Enabled */
2106 entry.trigger = 0; /* Edge */
2108 entry.polarity = 0; /* High */
2109 entry.delivery_status = 0;
2110 entry.dest_mode = 0; /* Physical */
2111 entry.delivery_mode = dest_ExtINT; /* ExtInt */
2113 entry.dest = read_apic_id();
2116 * Add it to the IO-APIC irq-routing table:
2118 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2122 * Use virtual wire A mode when interrupt remapping is enabled.
2124 disconnect_bsp_APIC(!intr_remapping_enabled && ioapic_i8259.pin != -1);
2127 #ifdef CONFIG_X86_32
2129 * function to set the IO-APIC physical IDs based on the
2130 * values stored in the MPC table.
2132 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2135 static void __init setup_ioapic_ids_from_mpc(void)
2137 union IO_APIC_reg_00 reg_00;
2138 physid_mask_t phys_id_present_map;
2141 unsigned char old_id;
2142 unsigned long flags;
2144 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2148 * Don't check I/O APIC IDs for xAPIC systems. They have
2149 * no meaning without the serial APIC bus.
2151 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2152 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2155 * This is broken; anything with a real cpu count has to
2156 * circumvent this idiocy regardless.
2158 phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
2161 * Set the IOAPIC ID to the value stored in the MPC table.
2163 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2165 /* Read the register 0 value */
2166 spin_lock_irqsave(&ioapic_lock, flags);
2167 reg_00.raw = io_apic_read(apic_id, 0);
2168 spin_unlock_irqrestore(&ioapic_lock, flags);
2170 old_id = mp_ioapics[apic_id].apicid;
2172 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2173 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2174 apic_id, mp_ioapics[apic_id].apicid);
2175 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2177 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2181 * Sanity check, is the ID really free? Every APIC in a
2182 * system must have a unique ID or we get lots of nice
2183 * 'stuck on smp_invalidate_needed IPI wait' messages.
2185 if (apic->check_apicid_used(phys_id_present_map,
2186 mp_ioapics[apic_id].apicid)) {
2187 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2188 apic_id, mp_ioapics[apic_id].apicid);
2189 for (i = 0; i < get_physical_broadcast(); i++)
2190 if (!physid_isset(i, phys_id_present_map))
2192 if (i >= get_physical_broadcast())
2193 panic("Max APIC ID exceeded!\n");
2194 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2196 physid_set(i, phys_id_present_map);
2197 mp_ioapics[apic_id].apicid = i;
2200 tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
2201 apic_printk(APIC_VERBOSE, "Setting %d in the "
2202 "phys_id_present_map\n",
2203 mp_ioapics[apic_id].apicid);
2204 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2209 * We need to adjust the IRQ routing table
2210 * if the ID changed.
2212 if (old_id != mp_ioapics[apic_id].apicid)
2213 for (i = 0; i < mp_irq_entries; i++)
2214 if (mp_irqs[i].dstapic == old_id)
2216 = mp_ioapics[apic_id].apicid;
2219 * Read the right value from the MPC table and
2220 * write it into the ID register.
2222 apic_printk(APIC_VERBOSE, KERN_INFO
2223 "...changing IO-APIC physical APIC ID to %d ...",
2224 mp_ioapics[apic_id].apicid);
2226 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2227 spin_lock_irqsave(&ioapic_lock, flags);
2228 io_apic_write(apic_id, 0, reg_00.raw);
2229 spin_unlock_irqrestore(&ioapic_lock, flags);
2234 spin_lock_irqsave(&ioapic_lock, flags);
2235 reg_00.raw = io_apic_read(apic_id, 0);
2236 spin_unlock_irqrestore(&ioapic_lock, flags);
2237 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2238 printk("could not set ID!\n");
2240 apic_printk(APIC_VERBOSE, " ok.\n");
2245 int no_timer_check __initdata;
2247 static int __init notimercheck(char *s)
2252 __setup("no_timer_check", notimercheck);
2255 * There is a nasty bug in some older SMP boards, their mptable lies
2256 * about the timer IRQ. We do the following to work around the situation:
2258 * - timer IRQ defaults to IO-APIC IRQ
2259 * - if this function detects that timer IRQs are defunct, then we fall
2260 * back to ISA timer IRQs
2262 static int __init timer_irq_works(void)
2264 unsigned long t1 = jiffies;
2265 unsigned long flags;
2270 local_save_flags(flags);
2272 /* Let ten ticks pass... */
2273 mdelay((10 * 1000) / HZ);
2274 local_irq_restore(flags);
2277 * Expect a few ticks at least, to be sure some possible
2278 * glue logic does not lock up after one or two first
2279 * ticks in a non-ExtINT mode. Also the local APIC
2280 * might have cached one ExtINT interrupt. Finally, at
2281 * least one tick may be lost due to delays.
2285 if (time_after(jiffies, t1 + 4))
2291 * In the SMP+IOAPIC case it might happen that there are an unspecified
2292 * number of pending IRQ events unhandled. These cases are very rare,
2293 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2294 * better to do it this way as thus we do not have to be aware of
2295 * 'pending' interrupts in the IRQ path, except at this point.
2298 * Edge triggered needs to resend any interrupt
2299 * that was delayed but this is now handled in the device
2304 * Starting up a edge-triggered IO-APIC interrupt is
2305 * nasty - we need to make sure that we get the edge.
2306 * If it is already asserted for some reason, we need
2307 * return 1 to indicate that is was pending.
2309 * This is not complete - we should be able to fake
2310 * an edge even if it isn't on the 8259A...
2313 static unsigned int startup_ioapic_irq(unsigned int irq)
2315 int was_pending = 0;
2316 unsigned long flags;
2317 struct irq_cfg *cfg;
2319 spin_lock_irqsave(&ioapic_lock, flags);
2320 if (irq < NR_IRQS_LEGACY) {
2321 disable_8259A_irq(irq);
2322 if (i8259A_irq_pending(irq))
2326 __unmask_IO_APIC_irq(cfg);
2327 spin_unlock_irqrestore(&ioapic_lock, flags);
2332 #ifdef CONFIG_X86_64
2333 static int ioapic_retrigger_irq(unsigned int irq)
2336 struct irq_cfg *cfg = irq_cfg(irq);
2337 unsigned long flags;
2339 spin_lock_irqsave(&vector_lock, flags);
2340 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2341 spin_unlock_irqrestore(&vector_lock, flags);
2346 static int ioapic_retrigger_irq(unsigned int irq)
2348 apic->send_IPI_self(irq_cfg(irq)->vector);
2355 * Level and edge triggered IO-APIC interrupts need different handling,
2356 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2357 * handled with the level-triggered descriptor, but that one has slightly
2358 * more overhead. Level-triggered interrupts cannot be handled with the
2359 * edge-triggered handler, without risking IRQ storms and other ugly
2365 #ifdef CONFIG_INTR_REMAP
2368 * Migrate the IO-APIC irq in the presence of intr-remapping.
2370 * For both level and edge triggered, irq migration is a simple atomic
2371 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2373 * For level triggered, we eliminate the io-apic RTE modification (with the
2374 * updated vector information), by using a virtual vector (io-apic pin number).
2375 * Real vector that is used for interrupting cpu will be coming from
2376 * the interrupt-remapping table entry.
2379 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2381 struct irq_cfg *cfg;
2386 if (!cpumask_intersects(mask, cpu_online_mask))
2390 if (get_irte(irq, &irte))
2393 cfg = desc->chip_data;
2394 if (assign_irq_vector(irq, cfg, mask))
2397 set_extra_move_desc(desc, mask);
2399 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2401 irte.vector = cfg->vector;
2402 irte.dest_id = IRTE_DEST(dest);
2405 * Modified the IRTE and flushes the Interrupt entry cache.
2407 modify_irte(irq, &irte);
2409 if (cfg->move_in_progress)
2410 send_cleanup_vector(cfg);
2412 cpumask_copy(desc->affinity, mask);
2416 * Migrates the IRQ destination in the process context.
2418 static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2419 const struct cpumask *mask)
2421 migrate_ioapic_irq_desc(desc, mask);
2423 static void set_ir_ioapic_affinity_irq(unsigned int irq,
2424 const struct cpumask *mask)
2426 struct irq_desc *desc = irq_to_desc(irq);
2428 set_ir_ioapic_affinity_irq_desc(desc, mask);
2431 static inline void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2432 const struct cpumask *mask)
2437 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2439 unsigned vector, me;
2445 me = smp_processor_id();
2446 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2449 struct irq_desc *desc;
2450 struct irq_cfg *cfg;
2451 irq = __get_cpu_var(vector_irq)[vector];
2456 desc = irq_to_desc(irq);
2461 spin_lock(&desc->lock);
2462 if (!cfg->move_cleanup_count)
2465 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2468 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2470 * Check if the vector that needs to be cleanedup is
2471 * registered at the cpu's IRR. If so, then this is not
2472 * the best time to clean it up. Lets clean it up in the
2473 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2476 if (irr & (1 << (vector % 32))) {
2477 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2480 __get_cpu_var(vector_irq)[vector] = -1;
2481 cfg->move_cleanup_count--;
2483 spin_unlock(&desc->lock);
2489 static void irq_complete_move(struct irq_desc **descp)
2491 struct irq_desc *desc = *descp;
2492 struct irq_cfg *cfg = desc->chip_data;
2493 unsigned vector, me;
2495 if (likely(!cfg->move_in_progress)) {
2496 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2497 if (likely(!cfg->move_desc_pending))
2500 /* domain has not changed, but affinity did */
2501 me = smp_processor_id();
2502 if (cpumask_test_cpu(me, desc->affinity)) {
2503 *descp = desc = move_irq_desc(desc, me);
2504 /* get the new one */
2505 cfg = desc->chip_data;
2506 cfg->move_desc_pending = 0;
2512 vector = ~get_irq_regs()->orig_ax;
2513 me = smp_processor_id();
2515 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) {
2516 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2517 *descp = desc = move_irq_desc(desc, me);
2518 /* get the new one */
2519 cfg = desc->chip_data;
2521 send_cleanup_vector(cfg);
2525 static inline void irq_complete_move(struct irq_desc **descp) {}
2528 #ifdef CONFIG_X86_X2APIC
2529 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2532 struct irq_pin_list *entry;
2534 entry = cfg->irq_2_pin;
2542 io_apic_eoi(apic, pin);
2543 entry = entry->next;
2548 eoi_ioapic_irq(struct irq_desc *desc)
2550 struct irq_cfg *cfg;
2551 unsigned long flags;
2555 cfg = desc->chip_data;
2557 spin_lock_irqsave(&ioapic_lock, flags);
2558 __eoi_ioapic_irq(irq, cfg);
2559 spin_unlock_irqrestore(&ioapic_lock, flags);
2562 static void ack_x2apic_level(unsigned int irq)
2564 struct irq_desc *desc = irq_to_desc(irq);
2566 eoi_ioapic_irq(desc);
2569 static void ack_x2apic_edge(unsigned int irq)
2575 static void ack_apic_edge(unsigned int irq)
2577 struct irq_desc *desc = irq_to_desc(irq);
2579 irq_complete_move(&desc);
2580 move_native_irq(irq);
2584 atomic_t irq_mis_count;
2586 static void ack_apic_level(unsigned int irq)
2588 struct irq_desc *desc = irq_to_desc(irq);
2590 #ifdef CONFIG_X86_32
2594 struct irq_cfg *cfg;
2595 int do_unmask_irq = 0;
2597 irq_complete_move(&desc);
2598 #ifdef CONFIG_GENERIC_PENDING_IRQ
2599 /* If we are moving the irq we need to mask it */
2600 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2602 mask_IO_APIC_irq_desc(desc);
2606 #ifdef CONFIG_X86_32
2608 * It appears there is an erratum which affects at least version 0x11
2609 * of I/O APIC (that's the 82093AA and cores integrated into various
2610 * chipsets). Under certain conditions a level-triggered interrupt is
2611 * erroneously delivered as edge-triggered one but the respective IRR
2612 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2613 * message but it will never arrive and further interrupts are blocked
2614 * from the source. The exact reason is so far unknown, but the
2615 * phenomenon was observed when two consecutive interrupt requests
2616 * from a given source get delivered to the same CPU and the source is
2617 * temporarily disabled in between.
2619 * A workaround is to simulate an EOI message manually. We achieve it
2620 * by setting the trigger mode to edge and then to level when the edge
2621 * trigger mode gets detected in the TMR of a local APIC for a
2622 * level-triggered interrupt. We mask the source for the time of the
2623 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2624 * The idea is from Manfred Spraul. --macro
2626 cfg = desc->chip_data;
2629 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2633 * We must acknowledge the irq before we move it or the acknowledge will
2634 * not propagate properly.
2638 /* Now we can move and renable the irq */
2639 if (unlikely(do_unmask_irq)) {
2640 /* Only migrate the irq if the ack has been received.
2642 * On rare occasions the broadcast level triggered ack gets
2643 * delayed going to ioapics, and if we reprogram the
2644 * vector while Remote IRR is still set the irq will never
2647 * To prevent this scenario we read the Remote IRR bit
2648 * of the ioapic. This has two effects.
2649 * - On any sane system the read of the ioapic will
2650 * flush writes (and acks) going to the ioapic from
2652 * - We get to see if the ACK has actually been delivered.
2654 * Based on failed experiments of reprogramming the
2655 * ioapic entry from outside of irq context starting
2656 * with masking the ioapic entry and then polling until
2657 * Remote IRR was clear before reprogramming the
2658 * ioapic I don't trust the Remote IRR bit to be
2659 * completey accurate.
2661 * However there appears to be no other way to plug
2662 * this race, so if the Remote IRR bit is not
2663 * accurate and is causing problems then it is a hardware bug
2664 * and you can go talk to the chipset vendor about it.
2666 cfg = desc->chip_data;
2667 if (!io_apic_level_ack_pending(cfg))
2668 move_masked_irq(irq);
2669 unmask_IO_APIC_irq_desc(desc);
2672 #ifdef CONFIG_X86_32
2673 if (!(v & (1 << (i & 0x1f)))) {
2674 atomic_inc(&irq_mis_count);
2675 spin_lock(&ioapic_lock);
2676 __mask_and_edge_IO_APIC_irq(cfg);
2677 __unmask_and_level_IO_APIC_irq(cfg);
2678 spin_unlock(&ioapic_lock);
2683 #ifdef CONFIG_INTR_REMAP
2684 static void ir_ack_apic_edge(unsigned int irq)
2686 #ifdef CONFIG_X86_X2APIC
2687 if (x2apic_enabled())
2688 return ack_x2apic_edge(irq);
2690 return ack_apic_edge(irq);
2693 static void ir_ack_apic_level(unsigned int irq)
2695 #ifdef CONFIG_X86_X2APIC
2696 if (x2apic_enabled())
2697 return ack_x2apic_level(irq);
2699 return ack_apic_level(irq);
2701 #endif /* CONFIG_INTR_REMAP */
2703 static struct irq_chip ioapic_chip __read_mostly = {
2705 .startup = startup_ioapic_irq,
2706 .mask = mask_IO_APIC_irq,
2707 .unmask = unmask_IO_APIC_irq,
2708 .ack = ack_apic_edge,
2709 .eoi = ack_apic_level,
2711 .set_affinity = set_ioapic_affinity_irq,
2713 .retrigger = ioapic_retrigger_irq,
2716 static struct irq_chip ir_ioapic_chip __read_mostly = {
2717 .name = "IR-IO-APIC",
2718 .startup = startup_ioapic_irq,
2719 .mask = mask_IO_APIC_irq,
2720 .unmask = unmask_IO_APIC_irq,
2721 #ifdef CONFIG_INTR_REMAP
2722 .ack = ir_ack_apic_edge,
2723 .eoi = ir_ack_apic_level,
2725 .set_affinity = set_ir_ioapic_affinity_irq,
2728 .retrigger = ioapic_retrigger_irq,
2731 static inline void init_IO_APIC_traps(void)
2734 struct irq_desc *desc;
2735 struct irq_cfg *cfg;
2738 * NOTE! The local APIC isn't very good at handling
2739 * multiple interrupts at the same interrupt level.
2740 * As the interrupt level is determined by taking the
2741 * vector number and shifting that right by 4, we
2742 * want to spread these out a bit so that they don't
2743 * all fall in the same interrupt level.
2745 * Also, we've got to be careful not to trash gate
2746 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2748 for_each_irq_desc(irq, desc) {
2749 cfg = desc->chip_data;
2750 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2752 * Hmm.. We don't have an entry for this,
2753 * so default to an old-fashioned 8259
2754 * interrupt if we can..
2756 if (irq < NR_IRQS_LEGACY)
2757 make_8259A_irq(irq);
2759 /* Strange. Oh, well.. */
2760 desc->chip = &no_irq_chip;
2766 * The local APIC irq-chip implementation:
2769 static void mask_lapic_irq(unsigned int irq)
2773 v = apic_read(APIC_LVT0);
2774 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2777 static void unmask_lapic_irq(unsigned int irq)
2781 v = apic_read(APIC_LVT0);
2782 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2785 static void ack_lapic_irq(unsigned int irq)
2790 static struct irq_chip lapic_chip __read_mostly = {
2791 .name = "local-APIC",
2792 .mask = mask_lapic_irq,
2793 .unmask = unmask_lapic_irq,
2794 .ack = ack_lapic_irq,
2797 static void lapic_register_intr(int irq, struct irq_desc *desc)
2799 desc->status &= ~IRQ_LEVEL;
2800 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2804 static void __init setup_nmi(void)
2807 * Dirty trick to enable the NMI watchdog ...
2808 * We put the 8259A master into AEOI mode and
2809 * unmask on all local APICs LVT0 as NMI.
2811 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2812 * is from Maciej W. Rozycki - so we do not have to EOI from
2813 * the NMI handler or the timer interrupt.
2815 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2817 enable_NMI_through_LVT0();
2819 apic_printk(APIC_VERBOSE, " done.\n");
2823 * This looks a bit hackish but it's about the only one way of sending
2824 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2825 * not support the ExtINT mode, unfortunately. We need to send these
2826 * cycles as some i82489DX-based boards have glue logic that keeps the
2827 * 8259A interrupt line asserted until INTA. --macro
2829 static inline void __init unlock_ExtINT_logic(void)
2832 struct IO_APIC_route_entry entry0, entry1;
2833 unsigned char save_control, save_freq_select;
2835 pin = find_isa_irq_pin(8, mp_INT);
2840 apic = find_isa_irq_apic(8, mp_INT);
2846 entry0 = ioapic_read_entry(apic, pin);
2847 clear_IO_APIC_pin(apic, pin);
2849 memset(&entry1, 0, sizeof(entry1));
2851 entry1.dest_mode = 0; /* physical delivery */
2852 entry1.mask = 0; /* unmask IRQ now */
2853 entry1.dest = hard_smp_processor_id();
2854 entry1.delivery_mode = dest_ExtINT;
2855 entry1.polarity = entry0.polarity;
2859 ioapic_write_entry(apic, pin, entry1);
2861 save_control = CMOS_READ(RTC_CONTROL);
2862 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2863 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2865 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2870 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2874 CMOS_WRITE(save_control, RTC_CONTROL);
2875 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2876 clear_IO_APIC_pin(apic, pin);
2878 ioapic_write_entry(apic, pin, entry0);
2881 static int disable_timer_pin_1 __initdata;
2882 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2883 static int __init disable_timer_pin_setup(char *arg)
2885 disable_timer_pin_1 = 1;
2888 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2890 int timer_through_8259 __initdata;
2893 * This code may look a bit paranoid, but it's supposed to cooperate with
2894 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2895 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2896 * fanatically on his truly buggy board.
2898 * FIXME: really need to revamp this for all platforms.
2900 static inline void __init check_timer(void)
2902 struct irq_desc *desc = irq_to_desc(0);
2903 struct irq_cfg *cfg = desc->chip_data;
2904 int cpu = boot_cpu_id;
2905 int apic1, pin1, apic2, pin2;
2906 unsigned long flags;
2909 local_irq_save(flags);
2912 * get/set the timer IRQ vector:
2914 disable_8259A_irq(0);
2915 assign_irq_vector(0, cfg, apic->target_cpus());
2918 * As IRQ0 is to be enabled in the 8259A, the virtual
2919 * wire has to be disabled in the local APIC. Also
2920 * timer interrupts need to be acknowledged manually in
2921 * the 8259A for the i82489DX when using the NMI
2922 * watchdog as that APIC treats NMIs as level-triggered.
2923 * The AEOI mode will finish them in the 8259A
2926 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2928 #ifdef CONFIG_X86_32
2932 ver = apic_read(APIC_LVR);
2933 ver = GET_APIC_VERSION(ver);
2934 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2938 pin1 = find_isa_irq_pin(0, mp_INT);
2939 apic1 = find_isa_irq_apic(0, mp_INT);
2940 pin2 = ioapic_i8259.pin;
2941 apic2 = ioapic_i8259.apic;
2943 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2944 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2945 cfg->vector, apic1, pin1, apic2, pin2);
2948 * Some BIOS writers are clueless and report the ExtINTA
2949 * I/O APIC input from the cascaded 8259A as the timer
2950 * interrupt input. So just in case, if only one pin
2951 * was found above, try it both directly and through the
2955 if (intr_remapping_enabled)
2956 panic("BIOS bug: timer not connected to IO-APIC");
2960 } else if (pin2 == -1) {
2967 * Ok, does IRQ0 through the IOAPIC work?
2970 add_pin_to_irq_cpu(cfg, cpu, apic1, pin1);
2971 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2973 /* for edge trigger, setup_IO_APIC_irq already
2974 * leave it unmasked.
2975 * so only need to unmask if it is level-trigger
2976 * do we really have level trigger timer?
2979 idx = find_irq_entry(apic1, pin1, mp_INT);
2980 if (idx != -1 && irq_trigger(idx))
2981 unmask_IO_APIC_irq_desc(desc);
2983 if (timer_irq_works()) {
2984 if (nmi_watchdog == NMI_IO_APIC) {
2986 enable_8259A_irq(0);
2988 if (disable_timer_pin_1 > 0)
2989 clear_IO_APIC_pin(0, pin1);
2992 if (intr_remapping_enabled)
2993 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2994 local_irq_disable();
2995 clear_IO_APIC_pin(apic1, pin1);
2997 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2998 "8254 timer not connected to IO-APIC\n");
3000 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
3001 "(IRQ0) through the 8259A ...\n");
3002 apic_printk(APIC_QUIET, KERN_INFO
3003 "..... (found apic %d pin %d) ...\n", apic2, pin2);
3005 * legacy devices should be connected to IO APIC #0
3007 replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2);
3008 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
3009 enable_8259A_irq(0);
3010 if (timer_irq_works()) {
3011 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
3012 timer_through_8259 = 1;
3013 if (nmi_watchdog == NMI_IO_APIC) {
3014 disable_8259A_irq(0);
3016 enable_8259A_irq(0);
3021 * Cleanup, just in case ...
3023 local_irq_disable();
3024 disable_8259A_irq(0);
3025 clear_IO_APIC_pin(apic2, pin2);
3026 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
3029 if (nmi_watchdog == NMI_IO_APIC) {
3030 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
3031 "through the IO-APIC - disabling NMI Watchdog!\n");
3032 nmi_watchdog = NMI_NONE;
3034 #ifdef CONFIG_X86_32
3038 apic_printk(APIC_QUIET, KERN_INFO
3039 "...trying to set up timer as Virtual Wire IRQ...\n");
3041 lapic_register_intr(0, desc);
3042 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
3043 enable_8259A_irq(0);
3045 if (timer_irq_works()) {
3046 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3049 local_irq_disable();
3050 disable_8259A_irq(0);
3051 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3052 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3054 apic_printk(APIC_QUIET, KERN_INFO
3055 "...trying to set up timer as ExtINT IRQ...\n");
3059 apic_write(APIC_LVT0, APIC_DM_EXTINT);
3061 unlock_ExtINT_logic();
3063 if (timer_irq_works()) {
3064 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3067 local_irq_disable();
3068 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3069 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3070 "report. Then try booting with the 'noapic' option.\n");
3072 local_irq_restore(flags);
3076 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3077 * to devices. However there may be an I/O APIC pin available for
3078 * this interrupt regardless. The pin may be left unconnected, but
3079 * typically it will be reused as an ExtINT cascade interrupt for
3080 * the master 8259A. In the MPS case such a pin will normally be
3081 * reported as an ExtINT interrupt in the MP table. With ACPI
3082 * there is no provision for ExtINT interrupts, and in the absence
3083 * of an override it would be treated as an ordinary ISA I/O APIC
3084 * interrupt, that is edge-triggered and unmasked by default. We
3085 * used to do this, but it caused problems on some systems because
3086 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3087 * the same ExtINT cascade interrupt to drive the local APIC of the
3088 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3089 * the I/O APIC in all cases now. No actual device should request
3090 * it anyway. --macro
3092 #define PIC_IRQS (1 << PIC_CASCADE_IR)
3094 void __init setup_IO_APIC(void)
3098 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3101 io_apic_irqs = ~PIC_IRQS;
3103 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3105 * Set up IO-APIC IRQ routing.
3107 #ifdef CONFIG_X86_32
3109 setup_ioapic_ids_from_mpc();
3112 setup_IO_APIC_irqs();
3113 init_IO_APIC_traps();
3118 * Called after all the initialization is done. If we didnt find any
3119 * APIC bugs then we can allow the modify fast path
3122 static int __init io_apic_bug_finalize(void)
3124 if (sis_apic_bug == -1)
3129 late_initcall(io_apic_bug_finalize);
3131 struct sysfs_ioapic_data {
3132 struct sys_device dev;
3133 struct IO_APIC_route_entry entry[0];
3135 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3137 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3139 struct IO_APIC_route_entry *entry;
3140 struct sysfs_ioapic_data *data;
3143 data = container_of(dev, struct sysfs_ioapic_data, dev);
3144 entry = data->entry;
3145 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3146 *entry = ioapic_read_entry(dev->id, i);
3151 static int ioapic_resume(struct sys_device *dev)
3153 struct IO_APIC_route_entry *entry;
3154 struct sysfs_ioapic_data *data;
3155 unsigned long flags;
3156 union IO_APIC_reg_00 reg_00;
3159 data = container_of(dev, struct sysfs_ioapic_data, dev);
3160 entry = data->entry;
3162 spin_lock_irqsave(&ioapic_lock, flags);
3163 reg_00.raw = io_apic_read(dev->id, 0);
3164 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3165 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3166 io_apic_write(dev->id, 0, reg_00.raw);
3168 spin_unlock_irqrestore(&ioapic_lock, flags);
3169 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3170 ioapic_write_entry(dev->id, i, entry[i]);
3175 static struct sysdev_class ioapic_sysdev_class = {
3177 .suspend = ioapic_suspend,
3178 .resume = ioapic_resume,
3181 static int __init ioapic_init_sysfs(void)
3183 struct sys_device * dev;
3186 error = sysdev_class_register(&ioapic_sysdev_class);
3190 for (i = 0; i < nr_ioapics; i++ ) {
3191 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3192 * sizeof(struct IO_APIC_route_entry);
3193 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3194 if (!mp_ioapic_data[i]) {
3195 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3198 dev = &mp_ioapic_data[i]->dev;
3200 dev->cls = &ioapic_sysdev_class;
3201 error = sysdev_register(dev);
3203 kfree(mp_ioapic_data[i]);
3204 mp_ioapic_data[i] = NULL;
3205 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3213 device_initcall(ioapic_init_sysfs);
3215 static int nr_irqs_gsi = NR_IRQS_LEGACY;
3217 * Dynamic irq allocate and deallocation
3219 unsigned int create_irq_nr(unsigned int irq_want)
3221 /* Allocate an unused irq */
3224 unsigned long flags;
3225 struct irq_cfg *cfg_new = NULL;
3226 int cpu = boot_cpu_id;
3227 struct irq_desc *desc_new = NULL;
3230 if (irq_want < nr_irqs_gsi)
3231 irq_want = nr_irqs_gsi;
3233 spin_lock_irqsave(&vector_lock, flags);
3234 for (new = irq_want; new < nr_irqs; new++) {
3235 desc_new = irq_to_desc_alloc_cpu(new, cpu);
3237 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3240 cfg_new = desc_new->chip_data;
3242 if (cfg_new->vector != 0)
3244 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3248 spin_unlock_irqrestore(&vector_lock, flags);
3251 dynamic_irq_init(irq);
3252 /* restore it, in case dynamic_irq_init clear it */
3254 desc_new->chip_data = cfg_new;
3259 int create_irq(void)
3261 unsigned int irq_want;
3264 irq_want = nr_irqs_gsi;
3265 irq = create_irq_nr(irq_want);
3273 void destroy_irq(unsigned int irq)
3275 unsigned long flags;
3276 struct irq_cfg *cfg;
3277 struct irq_desc *desc;
3279 /* store it, in case dynamic_irq_cleanup clear it */
3280 desc = irq_to_desc(irq);
3281 cfg = desc->chip_data;
3282 dynamic_irq_cleanup(irq);
3283 /* connect back irq_cfg */
3285 desc->chip_data = cfg;
3288 spin_lock_irqsave(&vector_lock, flags);
3289 __clear_irq_vector(irq, cfg);
3290 spin_unlock_irqrestore(&vector_lock, flags);
3294 * MSI message composition
3296 #ifdef CONFIG_PCI_MSI
3297 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3299 struct irq_cfg *cfg;
3307 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3311 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3313 if (irq_remapped(irq)) {
3318 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3319 BUG_ON(ir_index == -1);
3321 memset (&irte, 0, sizeof(irte));
3324 irte.dst_mode = apic->irq_dest_mode;
3325 irte.trigger_mode = 0; /* edge */
3326 irte.dlvry_mode = apic->irq_delivery_mode;
3327 irte.vector = cfg->vector;
3328 irte.dest_id = IRTE_DEST(dest);
3330 modify_irte(irq, &irte);
3332 msg->address_hi = MSI_ADDR_BASE_HI;
3333 msg->data = sub_handle;
3334 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3336 MSI_ADDR_IR_INDEX1(ir_index) |
3337 MSI_ADDR_IR_INDEX2(ir_index);
3339 if (x2apic_enabled())
3340 msg->address_hi = MSI_ADDR_BASE_HI |
3341 MSI_ADDR_EXT_DEST_ID(dest);
3343 msg->address_hi = MSI_ADDR_BASE_HI;
3347 ((apic->irq_dest_mode == 0) ?
3348 MSI_ADDR_DEST_MODE_PHYSICAL:
3349 MSI_ADDR_DEST_MODE_LOGICAL) |
3350 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3351 MSI_ADDR_REDIRECTION_CPU:
3352 MSI_ADDR_REDIRECTION_LOWPRI) |
3353 MSI_ADDR_DEST_ID(dest);
3356 MSI_DATA_TRIGGER_EDGE |
3357 MSI_DATA_LEVEL_ASSERT |
3358 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3359 MSI_DATA_DELIVERY_FIXED:
3360 MSI_DATA_DELIVERY_LOWPRI) |
3361 MSI_DATA_VECTOR(cfg->vector);
3367 static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3369 struct irq_desc *desc = irq_to_desc(irq);
3370 struct irq_cfg *cfg;
3374 dest = set_desc_affinity(desc, mask);
3375 if (dest == BAD_APICID)
3378 cfg = desc->chip_data;
3380 read_msi_msg_desc(desc, &msg);
3382 msg.data &= ~MSI_DATA_VECTOR_MASK;
3383 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3384 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3385 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3387 write_msi_msg_desc(desc, &msg);
3389 #ifdef CONFIG_INTR_REMAP
3391 * Migrate the MSI irq to another cpumask. This migration is
3392 * done in the process context using interrupt-remapping hardware.
3395 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3397 struct irq_desc *desc = irq_to_desc(irq);
3398 struct irq_cfg *cfg = desc->chip_data;
3402 if (get_irte(irq, &irte))
3405 dest = set_desc_affinity(desc, mask);
3406 if (dest == BAD_APICID)
3409 irte.vector = cfg->vector;
3410 irte.dest_id = IRTE_DEST(dest);
3413 * atomically update the IRTE with the new destination and vector.
3415 modify_irte(irq, &irte);
3418 * After this point, all the interrupts will start arriving
3419 * at the new destination. So, time to cleanup the previous
3420 * vector allocation.
3422 if (cfg->move_in_progress)
3423 send_cleanup_vector(cfg);
3427 #endif /* CONFIG_SMP */
3430 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3431 * which implement the MSI or MSI-X Capability Structure.
3433 static struct irq_chip msi_chip = {
3435 .unmask = unmask_msi_irq,
3436 .mask = mask_msi_irq,
3437 .ack = ack_apic_edge,
3439 .set_affinity = set_msi_irq_affinity,
3441 .retrigger = ioapic_retrigger_irq,
3444 static struct irq_chip msi_ir_chip = {
3445 .name = "IR-PCI-MSI",
3446 .unmask = unmask_msi_irq,
3447 .mask = mask_msi_irq,
3448 #ifdef CONFIG_INTR_REMAP
3449 .ack = ir_ack_apic_edge,
3451 .set_affinity = ir_set_msi_irq_affinity,
3454 .retrigger = ioapic_retrigger_irq,
3458 * Map the PCI dev to the corresponding remapping hardware unit
3459 * and allocate 'nvec' consecutive interrupt-remapping table entries
3462 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3464 struct intel_iommu *iommu;
3467 iommu = map_dev_to_ir(dev);
3470 "Unable to map PCI %s to iommu\n", pci_name(dev));
3474 index = alloc_irte(iommu, irq, nvec);
3477 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3484 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3489 ret = msi_compose_msg(dev, irq, &msg);
3493 set_irq_msi(irq, msidesc);
3494 write_msi_msg(irq, &msg);
3496 if (irq_remapped(irq)) {
3497 struct irq_desc *desc = irq_to_desc(irq);
3499 * irq migration in process context
3501 desc->status |= IRQ_MOVE_PCNTXT;
3502 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3504 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3506 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3511 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3514 int ret, sub_handle;
3515 struct msi_desc *msidesc;
3516 unsigned int irq_want;
3517 struct intel_iommu *iommu = NULL;
3520 /* x86 doesn't support multiple MSI yet */
3521 if (type == PCI_CAP_ID_MSI && nvec > 1)
3524 irq_want = nr_irqs_gsi;
3526 list_for_each_entry(msidesc, &dev->msi_list, list) {
3527 irq = create_irq_nr(irq_want);
3531 if (!intr_remapping_enabled)
3536 * allocate the consecutive block of IRTE's
3539 index = msi_alloc_irte(dev, irq, nvec);
3545 iommu = map_dev_to_ir(dev);
3551 * setup the mapping between the irq and the IRTE
3552 * base index, the sub_handle pointing to the
3553 * appropriate interrupt remap table entry.
3555 set_irte_irq(irq, iommu, index, sub_handle);
3558 ret = setup_msi_irq(dev, msidesc, irq);
3570 void arch_teardown_msi_irq(unsigned int irq)
3575 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3577 static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3579 struct irq_desc *desc = irq_to_desc(irq);
3580 struct irq_cfg *cfg;
3584 dest = set_desc_affinity(desc, mask);
3585 if (dest == BAD_APICID)
3588 cfg = desc->chip_data;
3590 dmar_msi_read(irq, &msg);
3592 msg.data &= ~MSI_DATA_VECTOR_MASK;
3593 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3594 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3595 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3597 dmar_msi_write(irq, &msg);
3600 #endif /* CONFIG_SMP */
3602 struct irq_chip dmar_msi_type = {
3604 .unmask = dmar_msi_unmask,
3605 .mask = dmar_msi_mask,
3606 .ack = ack_apic_edge,
3608 .set_affinity = dmar_msi_set_affinity,
3610 .retrigger = ioapic_retrigger_irq,
3613 int arch_setup_dmar_msi(unsigned int irq)
3618 ret = msi_compose_msg(NULL, irq, &msg);
3621 dmar_msi_write(irq, &msg);
3622 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3628 #ifdef CONFIG_HPET_TIMER
3631 static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3633 struct irq_desc *desc = irq_to_desc(irq);
3634 struct irq_cfg *cfg;
3638 dest = set_desc_affinity(desc, mask);
3639 if (dest == BAD_APICID)
3642 cfg = desc->chip_data;
3644 hpet_msi_read(irq, &msg);
3646 msg.data &= ~MSI_DATA_VECTOR_MASK;
3647 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3648 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3649 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3651 hpet_msi_write(irq, &msg);
3654 #endif /* CONFIG_SMP */
3656 static struct irq_chip hpet_msi_type = {
3658 .unmask = hpet_msi_unmask,
3659 .mask = hpet_msi_mask,
3660 .ack = ack_apic_edge,
3662 .set_affinity = hpet_msi_set_affinity,
3664 .retrigger = ioapic_retrigger_irq,
3667 int arch_setup_hpet_msi(unsigned int irq)
3672 ret = msi_compose_msg(NULL, irq, &msg);
3676 hpet_msi_write(irq, &msg);
3677 set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3684 #endif /* CONFIG_PCI_MSI */
3686 * Hypertransport interrupt support
3688 #ifdef CONFIG_HT_IRQ
3692 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3694 struct ht_irq_msg msg;
3695 fetch_ht_irq_msg(irq, &msg);
3697 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3698 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3700 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3701 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3703 write_ht_irq_msg(irq, &msg);
3706 static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3708 struct irq_desc *desc = irq_to_desc(irq);
3709 struct irq_cfg *cfg;
3712 dest = set_desc_affinity(desc, mask);
3713 if (dest == BAD_APICID)
3716 cfg = desc->chip_data;
3718 target_ht_irq(irq, dest, cfg->vector);
3723 static struct irq_chip ht_irq_chip = {
3725 .mask = mask_ht_irq,
3726 .unmask = unmask_ht_irq,
3727 .ack = ack_apic_edge,
3729 .set_affinity = set_ht_irq_affinity,
3731 .retrigger = ioapic_retrigger_irq,
3734 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3736 struct irq_cfg *cfg;
3743 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3745 struct ht_irq_msg msg;
3748 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3749 apic->target_cpus());
3751 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3755 HT_IRQ_LOW_DEST_ID(dest) |
3756 HT_IRQ_LOW_VECTOR(cfg->vector) |
3757 ((apic->irq_dest_mode == 0) ?
3758 HT_IRQ_LOW_DM_PHYSICAL :
3759 HT_IRQ_LOW_DM_LOGICAL) |
3760 HT_IRQ_LOW_RQEOI_EDGE |
3761 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3762 HT_IRQ_LOW_MT_FIXED :
3763 HT_IRQ_LOW_MT_ARBITRATED) |
3764 HT_IRQ_LOW_IRQ_MASKED;
3766 write_ht_irq_msg(irq, &msg);
3768 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3769 handle_edge_irq, "edge");
3771 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3775 #endif /* CONFIG_HT_IRQ */
3777 #ifdef CONFIG_X86_UV
3779 * Re-target the irq to the specified CPU and enable the specified MMR located
3780 * on the specified blade to allow the sending of MSIs to the specified CPU.
3782 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3783 unsigned long mmr_offset)
3785 const struct cpumask *eligible_cpu = cpumask_of(cpu);
3786 struct irq_cfg *cfg;
3788 unsigned long mmr_value;
3789 struct uv_IO_APIC_route_entry *entry;
3790 unsigned long flags;
3795 err = assign_irq_vector(irq, cfg, eligible_cpu);
3799 spin_lock_irqsave(&vector_lock, flags);
3800 set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3802 spin_unlock_irqrestore(&vector_lock, flags);
3805 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3806 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3808 entry->vector = cfg->vector;
3809 entry->delivery_mode = apic->irq_delivery_mode;
3810 entry->dest_mode = apic->irq_dest_mode;
3811 entry->polarity = 0;
3814 entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
3816 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3817 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3823 * Disable the specified MMR located on the specified blade so that MSIs are
3824 * longer allowed to be sent.
3826 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3828 unsigned long mmr_value;
3829 struct uv_IO_APIC_route_entry *entry;
3833 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3834 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3838 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3839 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3841 #endif /* CONFIG_X86_64 */
3843 int __init io_apic_get_redir_entries (int ioapic)
3845 union IO_APIC_reg_01 reg_01;
3846 unsigned long flags;
3848 spin_lock_irqsave(&ioapic_lock, flags);
3849 reg_01.raw = io_apic_read(ioapic, 1);
3850 spin_unlock_irqrestore(&ioapic_lock, flags);
3852 return reg_01.bits.entries;
3855 void __init probe_nr_irqs_gsi(void)
3859 nr = acpi_probe_gsi();
3860 if (nr > nr_irqs_gsi) {
3863 /* for acpi=off or acpi is not compiled in */
3867 for (idx = 0; idx < nr_ioapics; idx++)
3868 nr += io_apic_get_redir_entries(idx) + 1;
3870 if (nr > nr_irqs_gsi)
3874 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3877 #ifdef CONFIG_SPARSE_IRQ
3878 int __init arch_probe_nr_irqs(void)
3882 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3883 nr_irqs = NR_VECTORS * nr_cpu_ids;
3885 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3886 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3888 * for MSI and HT dyn irq
3890 nr += nr_irqs_gsi * 16;
3899 /* --------------------------------------------------------------------------
3900 ACPI-based IOAPIC Configuration
3901 -------------------------------------------------------------------------- */
3905 #ifdef CONFIG_X86_32
3906 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3908 union IO_APIC_reg_00 reg_00;
3909 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3911 unsigned long flags;
3915 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3916 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3917 * supports up to 16 on one shared APIC bus.
3919 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3920 * advantage of new APIC bus architecture.
3923 if (physids_empty(apic_id_map))
3924 apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
3926 spin_lock_irqsave(&ioapic_lock, flags);
3927 reg_00.raw = io_apic_read(ioapic, 0);
3928 spin_unlock_irqrestore(&ioapic_lock, flags);
3930 if (apic_id >= get_physical_broadcast()) {
3931 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3932 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3933 apic_id = reg_00.bits.ID;
3937 * Every APIC in a system must have a unique ID or we get lots of nice
3938 * 'stuck on smp_invalidate_needed IPI wait' messages.
3940 if (apic->check_apicid_used(apic_id_map, apic_id)) {
3942 for (i = 0; i < get_physical_broadcast(); i++) {
3943 if (!apic->check_apicid_used(apic_id_map, i))
3947 if (i == get_physical_broadcast())
3948 panic("Max apic_id exceeded!\n");
3950 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3951 "trying %d\n", ioapic, apic_id, i);
3956 tmp = apic->apicid_to_cpu_present(apic_id);
3957 physids_or(apic_id_map, apic_id_map, tmp);
3959 if (reg_00.bits.ID != apic_id) {
3960 reg_00.bits.ID = apic_id;
3962 spin_lock_irqsave(&ioapic_lock, flags);
3963 io_apic_write(ioapic, 0, reg_00.raw);
3964 reg_00.raw = io_apic_read(ioapic, 0);
3965 spin_unlock_irqrestore(&ioapic_lock, flags);
3968 if (reg_00.bits.ID != apic_id) {
3969 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3974 apic_printk(APIC_VERBOSE, KERN_INFO
3975 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3980 int __init io_apic_get_version(int ioapic)
3982 union IO_APIC_reg_01 reg_01;
3983 unsigned long flags;
3985 spin_lock_irqsave(&ioapic_lock, flags);
3986 reg_01.raw = io_apic_read(ioapic, 1);
3987 spin_unlock_irqrestore(&ioapic_lock, flags);
3989 return reg_01.bits.version;
3993 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3995 struct irq_desc *desc;
3996 struct irq_cfg *cfg;
3997 int cpu = boot_cpu_id;
3999 if (!IO_APIC_IRQ(irq)) {
4000 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
4005 desc = irq_to_desc_alloc_cpu(irq, cpu);
4007 printk(KERN_INFO "can not get irq_desc %d\n", irq);
4012 * IRQs < 16 are already in the irq_2_pin[] map
4014 if (irq >= NR_IRQS_LEGACY) {
4015 cfg = desc->chip_data;
4016 add_pin_to_irq_cpu(cfg, cpu, ioapic, pin);
4019 setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity);
4025 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
4029 if (skip_ioapic_setup)
4032 for (i = 0; i < mp_irq_entries; i++)
4033 if (mp_irqs[i].irqtype == mp_INT &&
4034 mp_irqs[i].srcbusirq == bus_irq)
4036 if (i >= mp_irq_entries)
4039 *trigger = irq_trigger(i);
4040 *polarity = irq_polarity(i);
4044 #endif /* CONFIG_ACPI */
4047 * This function currently is only a helper for the i386 smp boot process where
4048 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4049 * so mask in all cases should simply be apic->target_cpus()
4052 void __init setup_ioapic_dest(void)
4054 int pin, ioapic, irq, irq_entry;
4055 struct irq_desc *desc;
4056 struct irq_cfg *cfg;
4057 const struct cpumask *mask;
4059 if (skip_ioapic_setup == 1)
4062 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
4063 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4064 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4065 if (irq_entry == -1)
4067 irq = pin_2_irq(irq_entry, ioapic, pin);
4069 /* setup_IO_APIC_irqs could fail to get vector for some device
4070 * when you have too many devices, because at that time only boot
4073 desc = irq_to_desc(irq);
4074 cfg = desc->chip_data;
4076 setup_IO_APIC_irq(ioapic, pin, irq, desc,
4077 irq_trigger(irq_entry),
4078 irq_polarity(irq_entry));
4084 * Honour affinities which have been set in early boot
4087 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4088 mask = desc->affinity;
4090 mask = apic->target_cpus();
4092 if (intr_remapping_enabled)
4093 set_ir_ioapic_affinity_irq_desc(desc, mask);
4095 set_ioapic_affinity_irq_desc(desc, mask);
4102 #define IOAPIC_RESOURCE_NAME_SIZE 11
4104 static struct resource *ioapic_resources;
4106 static struct resource * __init ioapic_setup_resources(void)
4109 struct resource *res;
4113 if (nr_ioapics <= 0)
4116 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4119 mem = alloc_bootmem(n);
4123 mem += sizeof(struct resource) * nr_ioapics;
4125 for (i = 0; i < nr_ioapics; i++) {
4127 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4128 sprintf(mem, "IOAPIC %u", i);
4129 mem += IOAPIC_RESOURCE_NAME_SIZE;
4133 ioapic_resources = res;
4138 void __init ioapic_init_mappings(void)
4140 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4141 struct resource *ioapic_res;
4144 ioapic_res = ioapic_setup_resources();
4145 for (i = 0; i < nr_ioapics; i++) {
4146 if (smp_found_config) {
4147 ioapic_phys = mp_ioapics[i].apicaddr;
4148 #ifdef CONFIG_X86_32
4151 "WARNING: bogus zero IO-APIC "
4152 "address found in MPTABLE, "
4153 "disabling IO/APIC support!\n");
4154 smp_found_config = 0;
4155 skip_ioapic_setup = 1;
4156 goto fake_ioapic_page;
4160 #ifdef CONFIG_X86_32
4163 ioapic_phys = (unsigned long)
4164 alloc_bootmem_pages(PAGE_SIZE);
4165 ioapic_phys = __pa(ioapic_phys);
4167 set_fixmap_nocache(idx, ioapic_phys);
4168 apic_printk(APIC_VERBOSE,
4169 "mapped IOAPIC to %08lx (%08lx)\n",
4170 __fix_to_virt(idx), ioapic_phys);
4173 if (ioapic_res != NULL) {
4174 ioapic_res->start = ioapic_phys;
4175 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4181 static int __init ioapic_insert_resources(void)
4184 struct resource *r = ioapic_resources;
4187 if (nr_ioapics > 0) {
4189 "IO APIC resources couldn't be allocated.\n");
4195 for (i = 0; i < nr_ioapics; i++) {
4196 insert_resource(&iomem_resource, r);
4203 /* Insert the IO APIC resources after PCI initialization has occured to handle
4204 * IO APICS that are mapped in on a BAR in PCI space. */
4205 late_initcall(ioapic_insert_resources);