2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
51 #include <asm/proto.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/hw_irq.h>
63 #include <asm/uv/uv_hub.h>
64 #include <asm/uv/uv_irq.h>
68 #define __apicdebuginit(type) static type __init
69 #define for_each_irq_pin(entry, head) \
70 for (entry = head; entry; entry = entry->next)
73 * Is the SiS APIC rmw bug present ?
74 * -1 = don't know, 0 = no, 1 = yes
76 int sis_apic_bug = -1;
78 static DEFINE_SPINLOCK(ioapic_lock);
79 static DEFINE_SPINLOCK(vector_lock);
82 * # of IRQ routing registers
84 int nr_ioapic_registers[MAX_IO_APICS];
86 /* I/O APIC entries */
87 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
90 /* MP IRQ source entries */
91 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
93 /* # of MP IRQ source entries */
96 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
97 int mp_bus_id_to_type[MAX_MP_BUSSES];
100 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
102 int skip_ioapic_setup;
104 void arch_disable_smp_support(void)
108 noioapicreroute = -1;
110 skip_ioapic_setup = 1;
113 static int __init parse_noapic(char *str)
115 /* disable IO-APIC */
116 arch_disable_smp_support();
119 early_param("noapic", parse_noapic);
121 struct irq_pin_list {
123 struct irq_pin_list *next;
126 static struct irq_pin_list *get_one_free_irq_2_pin(int node)
128 struct irq_pin_list *pin;
130 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
136 * This is performance-critical, we want to do it O(1)
138 * Most irqs are mapped 1:1 with pins.
141 struct irq_pin_list *irq_2_pin;
142 cpumask_var_t domain;
143 cpumask_var_t old_domain;
144 unsigned move_cleanup_count;
146 u8 move_in_progress : 1;
149 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
150 #ifdef CONFIG_SPARSE_IRQ
151 static struct irq_cfg irq_cfgx[] = {
153 static struct irq_cfg irq_cfgx[NR_IRQS] = {
155 [0] = { .vector = IRQ0_VECTOR, },
156 [1] = { .vector = IRQ1_VECTOR, },
157 [2] = { .vector = IRQ2_VECTOR, },
158 [3] = { .vector = IRQ3_VECTOR, },
159 [4] = { .vector = IRQ4_VECTOR, },
160 [5] = { .vector = IRQ5_VECTOR, },
161 [6] = { .vector = IRQ6_VECTOR, },
162 [7] = { .vector = IRQ7_VECTOR, },
163 [8] = { .vector = IRQ8_VECTOR, },
164 [9] = { .vector = IRQ9_VECTOR, },
165 [10] = { .vector = IRQ10_VECTOR, },
166 [11] = { .vector = IRQ11_VECTOR, },
167 [12] = { .vector = IRQ12_VECTOR, },
168 [13] = { .vector = IRQ13_VECTOR, },
169 [14] = { .vector = IRQ14_VECTOR, },
170 [15] = { .vector = IRQ15_VECTOR, },
173 int __init arch_early_irq_init(void)
176 struct irq_desc *desc;
182 count = ARRAY_SIZE(irq_cfgx);
183 node= cpu_to_node(boot_cpu_id);
185 for (i = 0; i < count; i++) {
186 desc = irq_to_desc(i);
187 desc->chip_data = &cfg[i];
188 zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node);
189 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node);
190 if (i < NR_IRQS_LEGACY)
191 cpumask_setall(cfg[i].domain);
197 #ifdef CONFIG_SPARSE_IRQ
198 static struct irq_cfg *irq_cfg(unsigned int irq)
200 struct irq_cfg *cfg = NULL;
201 struct irq_desc *desc;
203 desc = irq_to_desc(irq);
205 cfg = desc->chip_data;
210 static struct irq_cfg *get_one_free_irq_cfg(int node)
214 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
216 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
219 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
221 free_cpumask_var(cfg->domain);
225 cpumask_clear(cfg->domain);
226 cpumask_clear(cfg->old_domain);
233 int arch_init_chip_data(struct irq_desc *desc, int node)
237 cfg = desc->chip_data;
239 desc->chip_data = get_one_free_irq_cfg(node);
240 if (!desc->chip_data) {
241 printk(KERN_ERR "can not alloc irq_cfg\n");
249 /* for move_irq_desc */
251 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node)
253 struct irq_pin_list *old_entry, *head, *tail, *entry;
255 cfg->irq_2_pin = NULL;
256 old_entry = old_cfg->irq_2_pin;
260 entry = get_one_free_irq_2_pin(node);
264 entry->apic = old_entry->apic;
265 entry->pin = old_entry->pin;
268 old_entry = old_entry->next;
270 entry = get_one_free_irq_2_pin(node);
278 /* still use the old one */
281 entry->apic = old_entry->apic;
282 entry->pin = old_entry->pin;
285 old_entry = old_entry->next;
289 cfg->irq_2_pin = head;
292 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
294 struct irq_pin_list *entry, *next;
296 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
299 entry = old_cfg->irq_2_pin;
306 old_cfg->irq_2_pin = NULL;
309 void arch_init_copy_chip_data(struct irq_desc *old_desc,
310 struct irq_desc *desc, int node)
313 struct irq_cfg *old_cfg;
315 cfg = get_one_free_irq_cfg(node);
320 desc->chip_data = cfg;
322 old_cfg = old_desc->chip_data;
324 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
326 init_copy_irq_2_pin(old_cfg, cfg, node);
329 static void free_irq_cfg(struct irq_cfg *old_cfg)
334 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
336 struct irq_cfg *old_cfg, *cfg;
338 old_cfg = old_desc->chip_data;
339 cfg = desc->chip_data;
345 free_irq_2_pin(old_cfg, cfg);
346 free_irq_cfg(old_cfg);
347 old_desc->chip_data = NULL;
350 /* end for move_irq_desc */
353 static struct irq_cfg *irq_cfg(unsigned int irq)
355 return irq < nr_irqs ? irq_cfgx + irq : NULL;
362 unsigned int unused[3];
364 unsigned int unused2[11];
368 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
370 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
371 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
374 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
376 struct io_apic __iomem *io_apic = io_apic_base(apic);
377 writel(vector, &io_apic->eoi);
380 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
382 struct io_apic __iomem *io_apic = io_apic_base(apic);
383 writel(reg, &io_apic->index);
384 return readl(&io_apic->data);
387 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
389 struct io_apic __iomem *io_apic = io_apic_base(apic);
390 writel(reg, &io_apic->index);
391 writel(value, &io_apic->data);
395 * Re-write a value: to be used for read-modify-write
396 * cycles where the read already set up the index register.
398 * Older SiS APIC requires we rewrite the index register
400 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
402 struct io_apic __iomem *io_apic = io_apic_base(apic);
405 writel(reg, &io_apic->index);
406 writel(value, &io_apic->data);
409 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
411 struct irq_pin_list *entry;
414 spin_lock_irqsave(&ioapic_lock, flags);
415 for_each_irq_pin(entry, cfg->irq_2_pin) {
420 reg = io_apic_read(entry->apic, 0x10 + pin*2);
421 /* Is the remote IRR bit set? */
422 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
423 spin_unlock_irqrestore(&ioapic_lock, flags);
427 spin_unlock_irqrestore(&ioapic_lock, flags);
433 struct { u32 w1, w2; };
434 struct IO_APIC_route_entry entry;
437 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
439 union entry_union eu;
441 spin_lock_irqsave(&ioapic_lock, flags);
442 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
443 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
444 spin_unlock_irqrestore(&ioapic_lock, flags);
449 * When we write a new IO APIC routing entry, we need to write the high
450 * word first! If the mask bit in the low word is clear, we will enable
451 * the interrupt, and we need to make sure the entry is fully populated
452 * before that happens.
455 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
457 union entry_union eu = {{0, 0}};
460 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
461 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
464 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
467 spin_lock_irqsave(&ioapic_lock, flags);
468 __ioapic_write_entry(apic, pin, e);
469 spin_unlock_irqrestore(&ioapic_lock, flags);
473 * When we mask an IO APIC routing entry, we need to write the low
474 * word first, in order to set the mask bit before we change the
477 static void ioapic_mask_entry(int apic, int pin)
480 union entry_union eu = { .entry.mask = 1 };
482 spin_lock_irqsave(&ioapic_lock, flags);
483 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
484 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
485 spin_unlock_irqrestore(&ioapic_lock, flags);
489 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
490 * shared ISA-space IRQs, so we have to support them. We are super
491 * fast in the common case, and fast for shared ISA-space IRQs.
493 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
495 struct irq_pin_list **last, *entry;
497 /* don't allow duplicates */
498 last = &cfg->irq_2_pin;
499 for_each_irq_pin(entry, cfg->irq_2_pin) {
500 if (entry->apic == apic && entry->pin == pin)
505 entry = get_one_free_irq_2_pin(node);
507 printk(KERN_ERR "can not alloc irq_pin_list\n");
517 * Reroute an IRQ to a different pin.
519 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
520 int oldapic, int oldpin,
521 int newapic, int newpin)
523 struct irq_pin_list *entry;
525 for_each_irq_pin(entry, cfg->irq_2_pin) {
526 if (entry->apic == oldapic && entry->pin == oldpin) {
527 entry->apic = newapic;
529 /* every one is different, right? */
534 /* old apic/pin didn't exist, so just add new ones */
535 add_pin_to_irq_node(cfg, node, newapic, newpin);
538 static void io_apic_modify_irq(struct irq_cfg *cfg,
539 int mask_and, int mask_or,
540 void (*final)(struct irq_pin_list *entry))
543 struct irq_pin_list *entry;
545 for_each_irq_pin(entry, cfg->irq_2_pin) {
548 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
551 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
557 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
559 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
562 static void io_apic_sync(struct irq_pin_list *entry)
565 * Synchronize the IO-APIC and the CPU by doing
566 * a dummy read from the IO-APIC
568 struct io_apic __iomem *io_apic;
569 io_apic = io_apic_base(entry->apic);
570 readl(&io_apic->data);
573 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
575 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
578 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
580 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
581 IO_APIC_REDIR_MASKED, NULL);
584 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
586 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
587 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
590 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
592 struct irq_cfg *cfg = desc->chip_data;
597 spin_lock_irqsave(&ioapic_lock, flags);
598 __mask_IO_APIC_irq(cfg);
599 spin_unlock_irqrestore(&ioapic_lock, flags);
602 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
604 struct irq_cfg *cfg = desc->chip_data;
607 spin_lock_irqsave(&ioapic_lock, flags);
608 __unmask_IO_APIC_irq(cfg);
609 spin_unlock_irqrestore(&ioapic_lock, flags);
612 static void mask_IO_APIC_irq(unsigned int irq)
614 struct irq_desc *desc = irq_to_desc(irq);
616 mask_IO_APIC_irq_desc(desc);
618 static void unmask_IO_APIC_irq(unsigned int irq)
620 struct irq_desc *desc = irq_to_desc(irq);
622 unmask_IO_APIC_irq_desc(desc);
625 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
627 struct IO_APIC_route_entry entry;
629 /* Check delivery_mode to be sure we're not clearing an SMI pin */
630 entry = ioapic_read_entry(apic, pin);
631 if (entry.delivery_mode == dest_SMI)
634 * Disable it in the IO-APIC irq-routing table:
636 ioapic_mask_entry(apic, pin);
639 static void clear_IO_APIC (void)
643 for (apic = 0; apic < nr_ioapics; apic++)
644 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
645 clear_IO_APIC_pin(apic, pin);
650 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
651 * specific CPU-side IRQs.
655 static int pirq_entries[MAX_PIRQS] = {
656 [0 ... MAX_PIRQS - 1] = -1
659 static int __init ioapic_pirq_setup(char *str)
662 int ints[MAX_PIRQS+1];
664 get_options(str, ARRAY_SIZE(ints), ints);
666 apic_printk(APIC_VERBOSE, KERN_INFO
667 "PIRQ redirection, working around broken MP-BIOS.\n");
669 if (ints[0] < MAX_PIRQS)
672 for (i = 0; i < max; i++) {
673 apic_printk(APIC_VERBOSE, KERN_DEBUG
674 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
676 * PIRQs are mapped upside down, usually.
678 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
683 __setup("pirq=", ioapic_pirq_setup);
684 #endif /* CONFIG_X86_32 */
686 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
689 struct IO_APIC_route_entry **ioapic_entries;
691 ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
696 for (apic = 0; apic < nr_ioapics; apic++) {
697 ioapic_entries[apic] =
698 kzalloc(sizeof(struct IO_APIC_route_entry) *
699 nr_ioapic_registers[apic], GFP_ATOMIC);
700 if (!ioapic_entries[apic])
704 return ioapic_entries;
708 kfree(ioapic_entries[apic]);
709 kfree(ioapic_entries);
715 * Saves all the IO-APIC RTE's
717 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
724 for (apic = 0; apic < nr_ioapics; apic++) {
725 if (!ioapic_entries[apic])
728 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
729 ioapic_entries[apic][pin] =
730 ioapic_read_entry(apic, pin);
737 * Mask all IO APIC entries.
739 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
746 for (apic = 0; apic < nr_ioapics; apic++) {
747 if (!ioapic_entries[apic])
750 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
751 struct IO_APIC_route_entry entry;
753 entry = ioapic_entries[apic][pin];
756 ioapic_write_entry(apic, pin, entry);
763 * Restore IO APIC entries which was saved in ioapic_entries.
765 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
772 for (apic = 0; apic < nr_ioapics; apic++) {
773 if (!ioapic_entries[apic])
776 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
777 ioapic_write_entry(apic, pin,
778 ioapic_entries[apic][pin]);
783 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
787 for (apic = 0; apic < nr_ioapics; apic++)
788 kfree(ioapic_entries[apic]);
790 kfree(ioapic_entries);
794 * Find the IRQ entry number of a certain pin.
796 static int find_irq_entry(int apic, int pin, int type)
800 for (i = 0; i < mp_irq_entries; i++)
801 if (mp_irqs[i].irqtype == type &&
802 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
803 mp_irqs[i].dstapic == MP_APIC_ALL) &&
804 mp_irqs[i].dstirq == pin)
811 * Find the pin to which IRQ[irq] (ISA) is connected
813 static int __init find_isa_irq_pin(int irq, int type)
817 for (i = 0; i < mp_irq_entries; i++) {
818 int lbus = mp_irqs[i].srcbus;
820 if (test_bit(lbus, mp_bus_not_pci) &&
821 (mp_irqs[i].irqtype == type) &&
822 (mp_irqs[i].srcbusirq == irq))
824 return mp_irqs[i].dstirq;
829 static int __init find_isa_irq_apic(int irq, int type)
833 for (i = 0; i < mp_irq_entries; i++) {
834 int lbus = mp_irqs[i].srcbus;
836 if (test_bit(lbus, mp_bus_not_pci) &&
837 (mp_irqs[i].irqtype == type) &&
838 (mp_irqs[i].srcbusirq == irq))
841 if (i < mp_irq_entries) {
843 for(apic = 0; apic < nr_ioapics; apic++) {
844 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
852 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
854 * EISA Edge/Level control register, ELCR
856 static int EISA_ELCR(unsigned int irq)
858 if (irq < NR_IRQS_LEGACY) {
859 unsigned int port = 0x4d0 + (irq >> 3);
860 return (inb(port) >> (irq & 7)) & 1;
862 apic_printk(APIC_VERBOSE, KERN_INFO
863 "Broken MPtable reports ISA irq %d\n", irq);
869 /* ISA interrupts are always polarity zero edge triggered,
870 * when listed as conforming in the MP table. */
872 #define default_ISA_trigger(idx) (0)
873 #define default_ISA_polarity(idx) (0)
875 /* EISA interrupts are always polarity zero and can be edge or level
876 * trigger depending on the ELCR value. If an interrupt is listed as
877 * EISA conforming in the MP table, that means its trigger type must
878 * be read in from the ELCR */
880 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
881 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
883 /* PCI interrupts are always polarity one level triggered,
884 * when listed as conforming in the MP table. */
886 #define default_PCI_trigger(idx) (1)
887 #define default_PCI_polarity(idx) (1)
889 /* MCA interrupts are always polarity zero level triggered,
890 * when listed as conforming in the MP table. */
892 #define default_MCA_trigger(idx) (1)
893 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
895 static int MPBIOS_polarity(int idx)
897 int bus = mp_irqs[idx].srcbus;
901 * Determine IRQ line polarity (high active or low active):
903 switch (mp_irqs[idx].irqflag & 3)
905 case 0: /* conforms, ie. bus-type dependent polarity */
906 if (test_bit(bus, mp_bus_not_pci))
907 polarity = default_ISA_polarity(idx);
909 polarity = default_PCI_polarity(idx);
911 case 1: /* high active */
916 case 2: /* reserved */
918 printk(KERN_WARNING "broken BIOS!!\n");
922 case 3: /* low active */
927 default: /* invalid */
929 printk(KERN_WARNING "broken BIOS!!\n");
937 static int MPBIOS_trigger(int idx)
939 int bus = mp_irqs[idx].srcbus;
943 * Determine IRQ trigger mode (edge or level sensitive):
945 switch ((mp_irqs[idx].irqflag>>2) & 3)
947 case 0: /* conforms, ie. bus-type dependent */
948 if (test_bit(bus, mp_bus_not_pci))
949 trigger = default_ISA_trigger(idx);
951 trigger = default_PCI_trigger(idx);
952 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
953 switch (mp_bus_id_to_type[bus]) {
954 case MP_BUS_ISA: /* ISA pin */
956 /* set before the switch */
959 case MP_BUS_EISA: /* EISA pin */
961 trigger = default_EISA_trigger(idx);
964 case MP_BUS_PCI: /* PCI pin */
966 /* set before the switch */
969 case MP_BUS_MCA: /* MCA pin */
971 trigger = default_MCA_trigger(idx);
976 printk(KERN_WARNING "broken BIOS!!\n");
988 case 2: /* reserved */
990 printk(KERN_WARNING "broken BIOS!!\n");
999 default: /* invalid */
1001 printk(KERN_WARNING "broken BIOS!!\n");
1009 static inline int irq_polarity(int idx)
1011 return MPBIOS_polarity(idx);
1014 static inline int irq_trigger(int idx)
1016 return MPBIOS_trigger(idx);
1019 int (*ioapic_renumber_irq)(int ioapic, int irq);
1020 static int pin_2_irq(int idx, int apic, int pin)
1023 int bus = mp_irqs[idx].srcbus;
1026 * Debugging check, we are in big trouble if this message pops up!
1028 if (mp_irqs[idx].dstirq != pin)
1029 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1031 if (test_bit(bus, mp_bus_not_pci)) {
1032 irq = mp_irqs[idx].srcbusirq;
1035 * PCI IRQs are mapped in order
1039 irq += nr_ioapic_registers[i++];
1042 * For MPS mode, so far only needed by ES7000 platform
1044 if (ioapic_renumber_irq)
1045 irq = ioapic_renumber_irq(apic, irq);
1048 #ifdef CONFIG_X86_32
1050 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1052 if ((pin >= 16) && (pin <= 23)) {
1053 if (pirq_entries[pin-16] != -1) {
1054 if (!pirq_entries[pin-16]) {
1055 apic_printk(APIC_VERBOSE, KERN_DEBUG
1056 "disabling PIRQ%d\n", pin-16);
1058 irq = pirq_entries[pin-16];
1059 apic_printk(APIC_VERBOSE, KERN_DEBUG
1060 "using PIRQ%d -> IRQ %d\n",
1071 * Find a specific PCI IRQ entry.
1072 * Not an __init, possibly needed by modules
1074 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1075 struct io_apic_irq_attr *irq_attr)
1077 int apic, i, best_guess = -1;
1079 apic_printk(APIC_DEBUG,
1080 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1082 if (test_bit(bus, mp_bus_not_pci)) {
1083 apic_printk(APIC_VERBOSE,
1084 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1087 for (i = 0; i < mp_irq_entries; i++) {
1088 int lbus = mp_irqs[i].srcbus;
1090 for (apic = 0; apic < nr_ioapics; apic++)
1091 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1092 mp_irqs[i].dstapic == MP_APIC_ALL)
1095 if (!test_bit(lbus, mp_bus_not_pci) &&
1096 !mp_irqs[i].irqtype &&
1098 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1099 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1101 if (!(apic || IO_APIC_IRQ(irq)))
1104 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1105 set_io_apic_irq_attr(irq_attr, apic,
1112 * Use the first all-but-pin matching entry as a
1113 * best-guess fuzzy result for broken mptables.
1115 if (best_guess < 0) {
1116 set_io_apic_irq_attr(irq_attr, apic,
1126 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1128 void lock_vector_lock(void)
1130 /* Used to the online set of cpus does not change
1131 * during assign_irq_vector.
1133 spin_lock(&vector_lock);
1136 void unlock_vector_lock(void)
1138 spin_unlock(&vector_lock);
1142 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1145 * NOTE! The local APIC isn't very good at handling
1146 * multiple interrupts at the same interrupt level.
1147 * As the interrupt level is determined by taking the
1148 * vector number and shifting that right by 4, we
1149 * want to spread these out a bit so that they don't
1150 * all fall in the same interrupt level.
1152 * Also, we've got to be careful not to trash gate
1153 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1155 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1156 unsigned int old_vector;
1158 cpumask_var_t tmp_mask;
1160 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1163 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1166 old_vector = cfg->vector;
1168 cpumask_and(tmp_mask, mask, cpu_online_mask);
1169 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1170 if (!cpumask_empty(tmp_mask)) {
1171 free_cpumask_var(tmp_mask);
1176 /* Only try and allocate irqs on cpus that are present */
1178 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1182 apic->vector_allocation_domain(cpu, tmp_mask);
1184 vector = current_vector;
1185 offset = current_offset;
1188 if (vector >= first_system_vector) {
1189 /* If out of vectors on large boxen, must share them. */
1190 offset = (offset + 1) % 8;
1191 vector = FIRST_DEVICE_VECTOR + offset;
1193 if (unlikely(current_vector == vector))
1196 if (test_bit(vector, used_vectors))
1199 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1200 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1203 current_vector = vector;
1204 current_offset = offset;
1206 cfg->move_in_progress = 1;
1207 cpumask_copy(cfg->old_domain, cfg->domain);
1209 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1210 per_cpu(vector_irq, new_cpu)[vector] = irq;
1211 cfg->vector = vector;
1212 cpumask_copy(cfg->domain, tmp_mask);
1216 free_cpumask_var(tmp_mask);
1221 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1224 unsigned long flags;
1226 spin_lock_irqsave(&vector_lock, flags);
1227 err = __assign_irq_vector(irq, cfg, mask);
1228 spin_unlock_irqrestore(&vector_lock, flags);
1232 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1236 BUG_ON(!cfg->vector);
1238 vector = cfg->vector;
1239 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1240 per_cpu(vector_irq, cpu)[vector] = -1;
1243 cpumask_clear(cfg->domain);
1245 if (likely(!cfg->move_in_progress))
1247 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1248 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1250 if (per_cpu(vector_irq, cpu)[vector] != irq)
1252 per_cpu(vector_irq, cpu)[vector] = -1;
1256 cfg->move_in_progress = 0;
1259 void __setup_vector_irq(int cpu)
1261 /* Initialize vector_irq on a new cpu */
1262 /* This function must be called with vector_lock held */
1264 struct irq_cfg *cfg;
1265 struct irq_desc *desc;
1267 /* Mark the inuse vectors */
1268 for_each_irq_desc(irq, desc) {
1269 cfg = desc->chip_data;
1270 if (!cpumask_test_cpu(cpu, cfg->domain))
1272 vector = cfg->vector;
1273 per_cpu(vector_irq, cpu)[vector] = irq;
1275 /* Mark the free vectors */
1276 for (vector = 0; vector < NR_VECTORS; ++vector) {
1277 irq = per_cpu(vector_irq, cpu)[vector];
1282 if (!cpumask_test_cpu(cpu, cfg->domain))
1283 per_cpu(vector_irq, cpu)[vector] = -1;
1287 static struct irq_chip ioapic_chip;
1288 static struct irq_chip ir_ioapic_chip;
1290 #define IOAPIC_AUTO -1
1291 #define IOAPIC_EDGE 0
1292 #define IOAPIC_LEVEL 1
1294 #ifdef CONFIG_X86_32
1295 static inline int IO_APIC_irq_trigger(int irq)
1299 for (apic = 0; apic < nr_ioapics; apic++) {
1300 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1301 idx = find_irq_entry(apic, pin, mp_INT);
1302 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1303 return irq_trigger(idx);
1307 * nonexistent IRQs are edge default
1312 static inline int IO_APIC_irq_trigger(int irq)
1318 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1321 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1322 trigger == IOAPIC_LEVEL)
1323 desc->status |= IRQ_LEVEL;
1325 desc->status &= ~IRQ_LEVEL;
1327 if (irq_remapped(irq)) {
1328 desc->status |= IRQ_MOVE_PCNTXT;
1330 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1334 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1335 handle_edge_irq, "edge");
1339 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1340 trigger == IOAPIC_LEVEL)
1341 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1345 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1346 handle_edge_irq, "edge");
1349 int setup_ioapic_entry(int apic_id, int irq,
1350 struct IO_APIC_route_entry *entry,
1351 unsigned int destination, int trigger,
1352 int polarity, int vector, int pin)
1355 * add it to the IO-APIC irq-routing table:
1357 memset(entry,0,sizeof(*entry));
1359 if (intr_remapping_enabled) {
1360 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1362 struct IR_IO_APIC_route_entry *ir_entry =
1363 (struct IR_IO_APIC_route_entry *) entry;
1367 panic("No mapping iommu for ioapic %d\n", apic_id);
1369 index = alloc_irte(iommu, irq, 1);
1371 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1373 memset(&irte, 0, sizeof(irte));
1376 irte.dst_mode = apic->irq_dest_mode;
1378 * Trigger mode in the IRTE will always be edge, and the
1379 * actual level or edge trigger will be setup in the IO-APIC
1380 * RTE. This will help simplify level triggered irq migration.
1381 * For more details, see the comments above explainig IO-APIC
1382 * irq migration in the presence of interrupt-remapping.
1384 irte.trigger_mode = 0;
1385 irte.dlvry_mode = apic->irq_delivery_mode;
1386 irte.vector = vector;
1387 irte.dest_id = IRTE_DEST(destination);
1389 /* Set source-id of interrupt request */
1390 set_ioapic_sid(&irte, apic_id);
1392 modify_irte(irq, &irte);
1394 ir_entry->index2 = (index >> 15) & 0x1;
1396 ir_entry->format = 1;
1397 ir_entry->index = (index & 0x7fff);
1399 * IO-APIC RTE will be configured with virtual vector.
1400 * irq handler will do the explicit EOI to the io-apic.
1402 ir_entry->vector = pin;
1404 entry->delivery_mode = apic->irq_delivery_mode;
1405 entry->dest_mode = apic->irq_dest_mode;
1406 entry->dest = destination;
1407 entry->vector = vector;
1410 entry->mask = 0; /* enable IRQ */
1411 entry->trigger = trigger;
1412 entry->polarity = polarity;
1414 /* Mask level triggered irqs.
1415 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1422 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1423 int trigger, int polarity)
1425 struct irq_cfg *cfg;
1426 struct IO_APIC_route_entry entry;
1429 if (!IO_APIC_IRQ(irq))
1432 cfg = desc->chip_data;
1434 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1437 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1439 apic_printk(APIC_VERBOSE,KERN_DEBUG
1440 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1441 "IRQ %d Mode:%i Active:%i)\n",
1442 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1443 irq, trigger, polarity);
1446 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1447 dest, trigger, polarity, cfg->vector, pin)) {
1448 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1449 mp_ioapics[apic_id].apicid, pin);
1450 __clear_irq_vector(irq, cfg);
1454 ioapic_register_intr(irq, desc, trigger);
1455 if (irq < NR_IRQS_LEGACY)
1456 disable_8259A_irq(irq);
1458 ioapic_write_entry(apic_id, pin, entry);
1462 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
1463 } mp_ioapic_routing[MAX_IO_APICS];
1465 static void __init setup_IO_APIC_irqs(void)
1467 int apic_id = 0, pin, idx, irq;
1469 struct irq_desc *desc;
1470 struct irq_cfg *cfg;
1471 int node = cpu_to_node(boot_cpu_id);
1473 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1476 if (!acpi_disabled && acpi_ioapic) {
1477 apic_id = mp_find_ioapic(0);
1483 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1484 idx = find_irq_entry(apic_id, pin, mp_INT);
1488 apic_printk(APIC_VERBOSE,
1489 KERN_DEBUG " %d-%d",
1490 mp_ioapics[apic_id].apicid, pin);
1492 apic_printk(APIC_VERBOSE, " %d-%d",
1493 mp_ioapics[apic_id].apicid, pin);
1497 apic_printk(APIC_VERBOSE,
1498 " (apicid-pin) not connected\n");
1502 irq = pin_2_irq(idx, apic_id, pin);
1505 * Skip the timer IRQ if there's a quirk handler
1506 * installed and if it returns 1:
1508 if (apic->multi_timer_check &&
1509 apic->multi_timer_check(apic_id, irq))
1512 desc = irq_to_desc_alloc_node(irq, node);
1514 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1517 cfg = desc->chip_data;
1518 add_pin_to_irq_node(cfg, node, apic_id, pin);
1520 * don't mark it in pin_programmed, so later acpi could
1521 * set it correctly when irq < 16
1523 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1524 irq_trigger(idx), irq_polarity(idx));
1528 apic_printk(APIC_VERBOSE,
1529 " (apicid-pin) not connected\n");
1533 * Set up the timer pin, possibly with the 8259A-master behind.
1535 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1538 struct IO_APIC_route_entry entry;
1540 if (intr_remapping_enabled)
1543 memset(&entry, 0, sizeof(entry));
1546 * We use logical delivery to get the timer IRQ
1549 entry.dest_mode = apic->irq_dest_mode;
1550 entry.mask = 0; /* don't mask IRQ for edge */
1551 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1552 entry.delivery_mode = apic->irq_delivery_mode;
1555 entry.vector = vector;
1558 * The timer IRQ doesn't have to know that behind the
1559 * scene we may have a 8259A-master in AEOI mode ...
1561 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1564 * Add it to the IO-APIC irq-routing table:
1566 ioapic_write_entry(apic_id, pin, entry);
1570 __apicdebuginit(void) print_IO_APIC(void)
1573 union IO_APIC_reg_00 reg_00;
1574 union IO_APIC_reg_01 reg_01;
1575 union IO_APIC_reg_02 reg_02;
1576 union IO_APIC_reg_03 reg_03;
1577 unsigned long flags;
1578 struct irq_cfg *cfg;
1579 struct irq_desc *desc;
1582 if (apic_verbosity == APIC_QUIET)
1585 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1586 for (i = 0; i < nr_ioapics; i++)
1587 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1588 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1591 * We are a bit conservative about what we expect. We have to
1592 * know about every hardware change ASAP.
1594 printk(KERN_INFO "testing the IO APIC.......................\n");
1596 for (apic = 0; apic < nr_ioapics; apic++) {
1598 spin_lock_irqsave(&ioapic_lock, flags);
1599 reg_00.raw = io_apic_read(apic, 0);
1600 reg_01.raw = io_apic_read(apic, 1);
1601 if (reg_01.bits.version >= 0x10)
1602 reg_02.raw = io_apic_read(apic, 2);
1603 if (reg_01.bits.version >= 0x20)
1604 reg_03.raw = io_apic_read(apic, 3);
1605 spin_unlock_irqrestore(&ioapic_lock, flags);
1608 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1609 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1610 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1611 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1612 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1614 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1615 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1617 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1618 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1621 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1622 * but the value of reg_02 is read as the previous read register
1623 * value, so ignore it if reg_02 == reg_01.
1625 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1626 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1627 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1631 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1632 * or reg_03, but the value of reg_0[23] is read as the previous read
1633 * register value, so ignore it if reg_03 == reg_0[12].
1635 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1636 reg_03.raw != reg_01.raw) {
1637 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1638 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1641 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1643 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1644 " Stat Dmod Deli Vect: \n");
1646 for (i = 0; i <= reg_01.bits.entries; i++) {
1647 struct IO_APIC_route_entry entry;
1649 entry = ioapic_read_entry(apic, i);
1651 printk(KERN_DEBUG " %02x %03X ",
1656 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1661 entry.delivery_status,
1663 entry.delivery_mode,
1668 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1669 for_each_irq_desc(irq, desc) {
1670 struct irq_pin_list *entry;
1672 cfg = desc->chip_data;
1673 entry = cfg->irq_2_pin;
1676 printk(KERN_DEBUG "IRQ%d ", irq);
1677 for_each_irq_pin(entry, cfg->irq_2_pin)
1678 printk("-> %d:%d", entry->apic, entry->pin);
1682 printk(KERN_INFO ".................................... done.\n");
1687 __apicdebuginit(void) print_APIC_field(int base)
1691 if (apic_verbosity == APIC_QUIET)
1696 for (i = 0; i < 8; i++)
1697 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1699 printk(KERN_CONT "\n");
1702 __apicdebuginit(void) print_local_APIC(void *dummy)
1704 unsigned int i, v, ver, maxlvt;
1707 if (apic_verbosity == APIC_QUIET)
1710 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1711 smp_processor_id(), hard_smp_processor_id());
1712 v = apic_read(APIC_ID);
1713 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1714 v = apic_read(APIC_LVR);
1715 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1716 ver = GET_APIC_VERSION(v);
1717 maxlvt = lapic_get_maxlvt();
1719 v = apic_read(APIC_TASKPRI);
1720 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1722 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1723 if (!APIC_XAPIC(ver)) {
1724 v = apic_read(APIC_ARBPRI);
1725 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1726 v & APIC_ARBPRI_MASK);
1728 v = apic_read(APIC_PROCPRI);
1729 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1733 * Remote read supported only in the 82489DX and local APIC for
1734 * Pentium processors.
1736 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1737 v = apic_read(APIC_RRR);
1738 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1741 v = apic_read(APIC_LDR);
1742 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1743 if (!x2apic_enabled()) {
1744 v = apic_read(APIC_DFR);
1745 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1747 v = apic_read(APIC_SPIV);
1748 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1750 printk(KERN_DEBUG "... APIC ISR field:\n");
1751 print_APIC_field(APIC_ISR);
1752 printk(KERN_DEBUG "... APIC TMR field:\n");
1753 print_APIC_field(APIC_TMR);
1754 printk(KERN_DEBUG "... APIC IRR field:\n");
1755 print_APIC_field(APIC_IRR);
1757 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1758 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1759 apic_write(APIC_ESR, 0);
1761 v = apic_read(APIC_ESR);
1762 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1765 icr = apic_icr_read();
1766 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1767 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1769 v = apic_read(APIC_LVTT);
1770 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1772 if (maxlvt > 3) { /* PC is LVT#4. */
1773 v = apic_read(APIC_LVTPC);
1774 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1776 v = apic_read(APIC_LVT0);
1777 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1778 v = apic_read(APIC_LVT1);
1779 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1781 if (maxlvt > 2) { /* ERR is LVT#3. */
1782 v = apic_read(APIC_LVTERR);
1783 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1786 v = apic_read(APIC_TMICT);
1787 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1788 v = apic_read(APIC_TMCCT);
1789 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1790 v = apic_read(APIC_TDCR);
1791 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1793 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1794 v = apic_read(APIC_EFEAT);
1795 maxlvt = (v >> 16) & 0xff;
1796 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1797 v = apic_read(APIC_ECTRL);
1798 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1799 for (i = 0; i < maxlvt; i++) {
1800 v = apic_read(APIC_EILVTn(i));
1801 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1807 __apicdebuginit(void) print_all_local_APICs(void)
1812 for_each_online_cpu(cpu)
1813 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1817 __apicdebuginit(void) print_PIC(void)
1820 unsigned long flags;
1822 if (apic_verbosity == APIC_QUIET)
1825 printk(KERN_DEBUG "\nprinting PIC contents\n");
1827 spin_lock_irqsave(&i8259A_lock, flags);
1829 v = inb(0xa1) << 8 | inb(0x21);
1830 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1832 v = inb(0xa0) << 8 | inb(0x20);
1833 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1837 v = inb(0xa0) << 8 | inb(0x20);
1841 spin_unlock_irqrestore(&i8259A_lock, flags);
1843 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1845 v = inb(0x4d1) << 8 | inb(0x4d0);
1846 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1849 __apicdebuginit(int) print_all_ICs(void)
1853 /* don't print out if apic is not there */
1854 if (!cpu_has_apic || disable_apic)
1857 print_all_local_APICs();
1863 fs_initcall(print_all_ICs);
1866 /* Where if anywhere is the i8259 connect in external int mode */
1867 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1869 void __init enable_IO_APIC(void)
1871 union IO_APIC_reg_01 reg_01;
1872 int i8259_apic, i8259_pin;
1874 unsigned long flags;
1877 * The number of IO-APIC IRQ registers (== #pins):
1879 for (apic = 0; apic < nr_ioapics; apic++) {
1880 spin_lock_irqsave(&ioapic_lock, flags);
1881 reg_01.raw = io_apic_read(apic, 1);
1882 spin_unlock_irqrestore(&ioapic_lock, flags);
1883 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1885 for(apic = 0; apic < nr_ioapics; apic++) {
1887 /* See if any of the pins is in ExtINT mode */
1888 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1889 struct IO_APIC_route_entry entry;
1890 entry = ioapic_read_entry(apic, pin);
1892 /* If the interrupt line is enabled and in ExtInt mode
1893 * I have found the pin where the i8259 is connected.
1895 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1896 ioapic_i8259.apic = apic;
1897 ioapic_i8259.pin = pin;
1903 /* Look to see what if the MP table has reported the ExtINT */
1904 /* If we could not find the appropriate pin by looking at the ioapic
1905 * the i8259 probably is not connected the ioapic but give the
1906 * mptable a chance anyway.
1908 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1909 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1910 /* Trust the MP table if nothing is setup in the hardware */
1911 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1912 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1913 ioapic_i8259.pin = i8259_pin;
1914 ioapic_i8259.apic = i8259_apic;
1916 /* Complain if the MP table and the hardware disagree */
1917 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1918 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1920 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1924 * Do not trust the IO-APIC being empty at bootup
1930 * Not an __init, needed by the reboot code
1932 void disable_IO_APIC(void)
1935 * Clear the IO-APIC before rebooting:
1940 * If the i8259 is routed through an IOAPIC
1941 * Put that IOAPIC in virtual wire mode
1942 * so legacy interrupts can be delivered.
1944 * With interrupt-remapping, for now we will use virtual wire A mode,
1945 * as virtual wire B is little complex (need to configure both
1946 * IOAPIC RTE aswell as interrupt-remapping table entry).
1947 * As this gets called during crash dump, keep this simple for now.
1949 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
1950 struct IO_APIC_route_entry entry;
1952 memset(&entry, 0, sizeof(entry));
1953 entry.mask = 0; /* Enabled */
1954 entry.trigger = 0; /* Edge */
1956 entry.polarity = 0; /* High */
1957 entry.delivery_status = 0;
1958 entry.dest_mode = 0; /* Physical */
1959 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1961 entry.dest = read_apic_id();
1964 * Add it to the IO-APIC irq-routing table:
1966 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1970 * Use virtual wire A mode when interrupt remapping is enabled.
1973 disconnect_bsp_APIC(!intr_remapping_enabled &&
1974 ioapic_i8259.pin != -1);
1977 #ifdef CONFIG_X86_32
1979 * function to set the IO-APIC physical IDs based on the
1980 * values stored in the MPC table.
1982 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1985 static void __init setup_ioapic_ids_from_mpc(void)
1987 union IO_APIC_reg_00 reg_00;
1988 physid_mask_t phys_id_present_map;
1991 unsigned char old_id;
1992 unsigned long flags;
1994 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
1998 * Don't check I/O APIC IDs for xAPIC systems. They have
1999 * no meaning without the serial APIC bus.
2001 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2002 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2005 * This is broken; anything with a real cpu count has to
2006 * circumvent this idiocy regardless.
2008 phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
2011 * Set the IOAPIC ID to the value stored in the MPC table.
2013 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2015 /* Read the register 0 value */
2016 spin_lock_irqsave(&ioapic_lock, flags);
2017 reg_00.raw = io_apic_read(apic_id, 0);
2018 spin_unlock_irqrestore(&ioapic_lock, flags);
2020 old_id = mp_ioapics[apic_id].apicid;
2022 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2023 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2024 apic_id, mp_ioapics[apic_id].apicid);
2025 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2027 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2031 * Sanity check, is the ID really free? Every APIC in a
2032 * system must have a unique ID or we get lots of nice
2033 * 'stuck on smp_invalidate_needed IPI wait' messages.
2035 if (apic->check_apicid_used(phys_id_present_map,
2036 mp_ioapics[apic_id].apicid)) {
2037 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2038 apic_id, mp_ioapics[apic_id].apicid);
2039 for (i = 0; i < get_physical_broadcast(); i++)
2040 if (!physid_isset(i, phys_id_present_map))
2042 if (i >= get_physical_broadcast())
2043 panic("Max APIC ID exceeded!\n");
2044 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2046 physid_set(i, phys_id_present_map);
2047 mp_ioapics[apic_id].apicid = i;
2050 tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
2051 apic_printk(APIC_VERBOSE, "Setting %d in the "
2052 "phys_id_present_map\n",
2053 mp_ioapics[apic_id].apicid);
2054 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2059 * We need to adjust the IRQ routing table
2060 * if the ID changed.
2062 if (old_id != mp_ioapics[apic_id].apicid)
2063 for (i = 0; i < mp_irq_entries; i++)
2064 if (mp_irqs[i].dstapic == old_id)
2066 = mp_ioapics[apic_id].apicid;
2069 * Read the right value from the MPC table and
2070 * write it into the ID register.
2072 apic_printk(APIC_VERBOSE, KERN_INFO
2073 "...changing IO-APIC physical APIC ID to %d ...",
2074 mp_ioapics[apic_id].apicid);
2076 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2077 spin_lock_irqsave(&ioapic_lock, flags);
2078 io_apic_write(apic_id, 0, reg_00.raw);
2079 spin_unlock_irqrestore(&ioapic_lock, flags);
2084 spin_lock_irqsave(&ioapic_lock, flags);
2085 reg_00.raw = io_apic_read(apic_id, 0);
2086 spin_unlock_irqrestore(&ioapic_lock, flags);
2087 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2088 printk("could not set ID!\n");
2090 apic_printk(APIC_VERBOSE, " ok.\n");
2095 int no_timer_check __initdata;
2097 static int __init notimercheck(char *s)
2102 __setup("no_timer_check", notimercheck);
2105 * There is a nasty bug in some older SMP boards, their mptable lies
2106 * about the timer IRQ. We do the following to work around the situation:
2108 * - timer IRQ defaults to IO-APIC IRQ
2109 * - if this function detects that timer IRQs are defunct, then we fall
2110 * back to ISA timer IRQs
2112 static int __init timer_irq_works(void)
2114 unsigned long t1 = jiffies;
2115 unsigned long flags;
2120 local_save_flags(flags);
2122 /* Let ten ticks pass... */
2123 mdelay((10 * 1000) / HZ);
2124 local_irq_restore(flags);
2127 * Expect a few ticks at least, to be sure some possible
2128 * glue logic does not lock up after one or two first
2129 * ticks in a non-ExtINT mode. Also the local APIC
2130 * might have cached one ExtINT interrupt. Finally, at
2131 * least one tick may be lost due to delays.
2135 if (time_after(jiffies, t1 + 4))
2141 * In the SMP+IOAPIC case it might happen that there are an unspecified
2142 * number of pending IRQ events unhandled. These cases are very rare,
2143 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2144 * better to do it this way as thus we do not have to be aware of
2145 * 'pending' interrupts in the IRQ path, except at this point.
2148 * Edge triggered needs to resend any interrupt
2149 * that was delayed but this is now handled in the device
2154 * Starting up a edge-triggered IO-APIC interrupt is
2155 * nasty - we need to make sure that we get the edge.
2156 * If it is already asserted for some reason, we need
2157 * return 1 to indicate that is was pending.
2159 * This is not complete - we should be able to fake
2160 * an edge even if it isn't on the 8259A...
2163 static unsigned int startup_ioapic_irq(unsigned int irq)
2165 int was_pending = 0;
2166 unsigned long flags;
2167 struct irq_cfg *cfg;
2169 spin_lock_irqsave(&ioapic_lock, flags);
2170 if (irq < NR_IRQS_LEGACY) {
2171 disable_8259A_irq(irq);
2172 if (i8259A_irq_pending(irq))
2176 __unmask_IO_APIC_irq(cfg);
2177 spin_unlock_irqrestore(&ioapic_lock, flags);
2182 static int ioapic_retrigger_irq(unsigned int irq)
2185 struct irq_cfg *cfg = irq_cfg(irq);
2186 unsigned long flags;
2188 spin_lock_irqsave(&vector_lock, flags);
2189 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2190 spin_unlock_irqrestore(&vector_lock, flags);
2196 * Level and edge triggered IO-APIC interrupts need different handling,
2197 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2198 * handled with the level-triggered descriptor, but that one has slightly
2199 * more overhead. Level-triggered interrupts cannot be handled with the
2200 * edge-triggered handler, without risking IRQ storms and other ugly
2205 static void send_cleanup_vector(struct irq_cfg *cfg)
2207 cpumask_var_t cleanup_mask;
2209 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2211 cfg->move_cleanup_count = 0;
2212 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2213 cfg->move_cleanup_count++;
2214 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2215 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2217 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2218 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
2219 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2220 free_cpumask_var(cleanup_mask);
2222 cfg->move_in_progress = 0;
2225 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2228 struct irq_pin_list *entry;
2229 u8 vector = cfg->vector;
2231 for_each_irq_pin(entry, cfg->irq_2_pin) {
2237 * With interrupt-remapping, destination information comes
2238 * from interrupt-remapping table entry.
2240 if (!irq_remapped(irq))
2241 io_apic_write(apic, 0x11 + pin*2, dest);
2242 reg = io_apic_read(apic, 0x10 + pin*2);
2243 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2245 io_apic_modify(apic, 0x10 + pin*2, reg);
2250 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
2253 * Either sets desc->affinity to a valid value, and returns
2254 * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
2255 * leaves desc->affinity untouched.
2258 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
2260 struct irq_cfg *cfg;
2263 if (!cpumask_intersects(mask, cpu_online_mask))
2267 cfg = desc->chip_data;
2268 if (assign_irq_vector(irq, cfg, mask))
2271 cpumask_copy(desc->affinity, mask);
2273 return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
2277 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2279 struct irq_cfg *cfg;
2280 unsigned long flags;
2286 cfg = desc->chip_data;
2288 spin_lock_irqsave(&ioapic_lock, flags);
2289 dest = set_desc_affinity(desc, mask);
2290 if (dest != BAD_APICID) {
2291 /* Only the high 8 bits are valid. */
2292 dest = SET_APIC_LOGICAL_ID(dest);
2293 __target_IO_APIC_irq(irq, dest, cfg);
2296 spin_unlock_irqrestore(&ioapic_lock, flags);
2302 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
2304 struct irq_desc *desc;
2306 desc = irq_to_desc(irq);
2308 return set_ioapic_affinity_irq_desc(desc, mask);
2311 #ifdef CONFIG_INTR_REMAP
2314 * Migrate the IO-APIC irq in the presence of intr-remapping.
2316 * For both level and edge triggered, irq migration is a simple atomic
2317 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2319 * For level triggered, we eliminate the io-apic RTE modification (with the
2320 * updated vector information), by using a virtual vector (io-apic pin number).
2321 * Real vector that is used for interrupting cpu will be coming from
2322 * the interrupt-remapping table entry.
2325 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2327 struct irq_cfg *cfg;
2333 if (!cpumask_intersects(mask, cpu_online_mask))
2337 if (get_irte(irq, &irte))
2340 cfg = desc->chip_data;
2341 if (assign_irq_vector(irq, cfg, mask))
2344 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2346 irte.vector = cfg->vector;
2347 irte.dest_id = IRTE_DEST(dest);
2350 * Modified the IRTE and flushes the Interrupt entry cache.
2352 modify_irte(irq, &irte);
2354 if (cfg->move_in_progress)
2355 send_cleanup_vector(cfg);
2357 cpumask_copy(desc->affinity, mask);
2363 * Migrates the IRQ destination in the process context.
2365 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2366 const struct cpumask *mask)
2368 return migrate_ioapic_irq_desc(desc, mask);
2370 static int set_ir_ioapic_affinity_irq(unsigned int irq,
2371 const struct cpumask *mask)
2373 struct irq_desc *desc = irq_to_desc(irq);
2375 return set_ir_ioapic_affinity_irq_desc(desc, mask);
2378 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2379 const struct cpumask *mask)
2385 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2387 unsigned vector, me;
2393 me = smp_processor_id();
2394 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2397 struct irq_desc *desc;
2398 struct irq_cfg *cfg;
2399 irq = __get_cpu_var(vector_irq)[vector];
2404 desc = irq_to_desc(irq);
2409 spin_lock(&desc->lock);
2410 if (!cfg->move_cleanup_count)
2413 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2416 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2418 * Check if the vector that needs to be cleanedup is
2419 * registered at the cpu's IRR. If so, then this is not
2420 * the best time to clean it up. Lets clean it up in the
2421 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2424 if (irr & (1 << (vector % 32))) {
2425 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2428 __get_cpu_var(vector_irq)[vector] = -1;
2429 cfg->move_cleanup_count--;
2431 spin_unlock(&desc->lock);
2437 static void irq_complete_move(struct irq_desc **descp)
2439 struct irq_desc *desc = *descp;
2440 struct irq_cfg *cfg = desc->chip_data;
2441 unsigned vector, me;
2443 if (likely(!cfg->move_in_progress))
2446 vector = ~get_irq_regs()->orig_ax;
2447 me = smp_processor_id();
2449 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2450 send_cleanup_vector(cfg);
2453 static inline void irq_complete_move(struct irq_desc **descp) {}
2456 static void ack_apic_edge(unsigned int irq)
2458 struct irq_desc *desc = irq_to_desc(irq);
2460 irq_complete_move(&desc);
2461 move_native_irq(irq);
2465 atomic_t irq_mis_count;
2467 static void ack_apic_level(unsigned int irq)
2469 struct irq_desc *desc = irq_to_desc(irq);
2472 struct irq_cfg *cfg;
2473 int do_unmask_irq = 0;
2475 irq_complete_move(&desc);
2476 #ifdef CONFIG_GENERIC_PENDING_IRQ
2477 /* If we are moving the irq we need to mask it */
2478 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2480 mask_IO_APIC_irq_desc(desc);
2485 * It appears there is an erratum which affects at least version 0x11
2486 * of I/O APIC (that's the 82093AA and cores integrated into various
2487 * chipsets). Under certain conditions a level-triggered interrupt is
2488 * erroneously delivered as edge-triggered one but the respective IRR
2489 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2490 * message but it will never arrive and further interrupts are blocked
2491 * from the source. The exact reason is so far unknown, but the
2492 * phenomenon was observed when two consecutive interrupt requests
2493 * from a given source get delivered to the same CPU and the source is
2494 * temporarily disabled in between.
2496 * A workaround is to simulate an EOI message manually. We achieve it
2497 * by setting the trigger mode to edge and then to level when the edge
2498 * trigger mode gets detected in the TMR of a local APIC for a
2499 * level-triggered interrupt. We mask the source for the time of the
2500 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2501 * The idea is from Manfred Spraul. --macro
2503 cfg = desc->chip_data;
2505 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2508 * We must acknowledge the irq before we move it or the acknowledge will
2509 * not propagate properly.
2513 /* Now we can move and renable the irq */
2514 if (unlikely(do_unmask_irq)) {
2515 /* Only migrate the irq if the ack has been received.
2517 * On rare occasions the broadcast level triggered ack gets
2518 * delayed going to ioapics, and if we reprogram the
2519 * vector while Remote IRR is still set the irq will never
2522 * To prevent this scenario we read the Remote IRR bit
2523 * of the ioapic. This has two effects.
2524 * - On any sane system the read of the ioapic will
2525 * flush writes (and acks) going to the ioapic from
2527 * - We get to see if the ACK has actually been delivered.
2529 * Based on failed experiments of reprogramming the
2530 * ioapic entry from outside of irq context starting
2531 * with masking the ioapic entry and then polling until
2532 * Remote IRR was clear before reprogramming the
2533 * ioapic I don't trust the Remote IRR bit to be
2534 * completey accurate.
2536 * However there appears to be no other way to plug
2537 * this race, so if the Remote IRR bit is not
2538 * accurate and is causing problems then it is a hardware bug
2539 * and you can go talk to the chipset vendor about it.
2541 cfg = desc->chip_data;
2542 if (!io_apic_level_ack_pending(cfg))
2543 move_masked_irq(irq);
2544 unmask_IO_APIC_irq_desc(desc);
2547 /* Tail end of version 0x11 I/O APIC bug workaround */
2548 if (!(v & (1 << (i & 0x1f)))) {
2549 atomic_inc(&irq_mis_count);
2550 spin_lock(&ioapic_lock);
2551 __mask_and_edge_IO_APIC_irq(cfg);
2552 __unmask_and_level_IO_APIC_irq(cfg);
2553 spin_unlock(&ioapic_lock);
2557 #ifdef CONFIG_INTR_REMAP
2558 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2560 struct irq_pin_list *entry;
2562 for_each_irq_pin(entry, cfg->irq_2_pin)
2563 io_apic_eoi(entry->apic, entry->pin);
2567 eoi_ioapic_irq(struct irq_desc *desc)
2569 struct irq_cfg *cfg;
2570 unsigned long flags;
2574 cfg = desc->chip_data;
2576 spin_lock_irqsave(&ioapic_lock, flags);
2577 __eoi_ioapic_irq(irq, cfg);
2578 spin_unlock_irqrestore(&ioapic_lock, flags);
2581 static void ir_ack_apic_edge(unsigned int irq)
2586 static void ir_ack_apic_level(unsigned int irq)
2588 struct irq_desc *desc = irq_to_desc(irq);
2591 eoi_ioapic_irq(desc);
2593 #endif /* CONFIG_INTR_REMAP */
2595 static struct irq_chip ioapic_chip __read_mostly = {
2597 .startup = startup_ioapic_irq,
2598 .mask = mask_IO_APIC_irq,
2599 .unmask = unmask_IO_APIC_irq,
2600 .ack = ack_apic_edge,
2601 .eoi = ack_apic_level,
2603 .set_affinity = set_ioapic_affinity_irq,
2605 .retrigger = ioapic_retrigger_irq,
2608 static struct irq_chip ir_ioapic_chip __read_mostly = {
2609 .name = "IR-IO-APIC",
2610 .startup = startup_ioapic_irq,
2611 .mask = mask_IO_APIC_irq,
2612 .unmask = unmask_IO_APIC_irq,
2613 #ifdef CONFIG_INTR_REMAP
2614 .ack = ir_ack_apic_edge,
2615 .eoi = ir_ack_apic_level,
2617 .set_affinity = set_ir_ioapic_affinity_irq,
2620 .retrigger = ioapic_retrigger_irq,
2623 static inline void init_IO_APIC_traps(void)
2626 struct irq_desc *desc;
2627 struct irq_cfg *cfg;
2630 * NOTE! The local APIC isn't very good at handling
2631 * multiple interrupts at the same interrupt level.
2632 * As the interrupt level is determined by taking the
2633 * vector number and shifting that right by 4, we
2634 * want to spread these out a bit so that they don't
2635 * all fall in the same interrupt level.
2637 * Also, we've got to be careful not to trash gate
2638 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2640 for_each_irq_desc(irq, desc) {
2641 cfg = desc->chip_data;
2642 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2644 * Hmm.. We don't have an entry for this,
2645 * so default to an old-fashioned 8259
2646 * interrupt if we can..
2648 if (irq < NR_IRQS_LEGACY)
2649 make_8259A_irq(irq);
2651 /* Strange. Oh, well.. */
2652 desc->chip = &no_irq_chip;
2658 * The local APIC irq-chip implementation:
2661 static void mask_lapic_irq(unsigned int irq)
2665 v = apic_read(APIC_LVT0);
2666 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2669 static void unmask_lapic_irq(unsigned int irq)
2673 v = apic_read(APIC_LVT0);
2674 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2677 static void ack_lapic_irq(unsigned int irq)
2682 static struct irq_chip lapic_chip __read_mostly = {
2683 .name = "local-APIC",
2684 .mask = mask_lapic_irq,
2685 .unmask = unmask_lapic_irq,
2686 .ack = ack_lapic_irq,
2689 static void lapic_register_intr(int irq, struct irq_desc *desc)
2691 desc->status &= ~IRQ_LEVEL;
2692 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2696 static void __init setup_nmi(void)
2699 * Dirty trick to enable the NMI watchdog ...
2700 * We put the 8259A master into AEOI mode and
2701 * unmask on all local APICs LVT0 as NMI.
2703 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2704 * is from Maciej W. Rozycki - so we do not have to EOI from
2705 * the NMI handler or the timer interrupt.
2707 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2709 enable_NMI_through_LVT0();
2711 apic_printk(APIC_VERBOSE, " done.\n");
2715 * This looks a bit hackish but it's about the only one way of sending
2716 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2717 * not support the ExtINT mode, unfortunately. We need to send these
2718 * cycles as some i82489DX-based boards have glue logic that keeps the
2719 * 8259A interrupt line asserted until INTA. --macro
2721 static inline void __init unlock_ExtINT_logic(void)
2724 struct IO_APIC_route_entry entry0, entry1;
2725 unsigned char save_control, save_freq_select;
2727 pin = find_isa_irq_pin(8, mp_INT);
2732 apic = find_isa_irq_apic(8, mp_INT);
2738 entry0 = ioapic_read_entry(apic, pin);
2739 clear_IO_APIC_pin(apic, pin);
2741 memset(&entry1, 0, sizeof(entry1));
2743 entry1.dest_mode = 0; /* physical delivery */
2744 entry1.mask = 0; /* unmask IRQ now */
2745 entry1.dest = hard_smp_processor_id();
2746 entry1.delivery_mode = dest_ExtINT;
2747 entry1.polarity = entry0.polarity;
2751 ioapic_write_entry(apic, pin, entry1);
2753 save_control = CMOS_READ(RTC_CONTROL);
2754 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2755 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2757 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2762 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2766 CMOS_WRITE(save_control, RTC_CONTROL);
2767 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2768 clear_IO_APIC_pin(apic, pin);
2770 ioapic_write_entry(apic, pin, entry0);
2773 static int disable_timer_pin_1 __initdata;
2774 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2775 static int __init disable_timer_pin_setup(char *arg)
2777 disable_timer_pin_1 = 1;
2780 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2782 int timer_through_8259 __initdata;
2785 * This code may look a bit paranoid, but it's supposed to cooperate with
2786 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2787 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2788 * fanatically on his truly buggy board.
2790 * FIXME: really need to revamp this for all platforms.
2792 static inline void __init check_timer(void)
2794 struct irq_desc *desc = irq_to_desc(0);
2795 struct irq_cfg *cfg = desc->chip_data;
2796 int node = cpu_to_node(boot_cpu_id);
2797 int apic1, pin1, apic2, pin2;
2798 unsigned long flags;
2801 local_irq_save(flags);
2804 * get/set the timer IRQ vector:
2806 disable_8259A_irq(0);
2807 assign_irq_vector(0, cfg, apic->target_cpus());
2810 * As IRQ0 is to be enabled in the 8259A, the virtual
2811 * wire has to be disabled in the local APIC. Also
2812 * timer interrupts need to be acknowledged manually in
2813 * the 8259A for the i82489DX when using the NMI
2814 * watchdog as that APIC treats NMIs as level-triggered.
2815 * The AEOI mode will finish them in the 8259A
2818 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2820 #ifdef CONFIG_X86_32
2824 ver = apic_read(APIC_LVR);
2825 ver = GET_APIC_VERSION(ver);
2826 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2830 pin1 = find_isa_irq_pin(0, mp_INT);
2831 apic1 = find_isa_irq_apic(0, mp_INT);
2832 pin2 = ioapic_i8259.pin;
2833 apic2 = ioapic_i8259.apic;
2835 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2836 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2837 cfg->vector, apic1, pin1, apic2, pin2);
2840 * Some BIOS writers are clueless and report the ExtINTA
2841 * I/O APIC input from the cascaded 8259A as the timer
2842 * interrupt input. So just in case, if only one pin
2843 * was found above, try it both directly and through the
2847 if (intr_remapping_enabled)
2848 panic("BIOS bug: timer not connected to IO-APIC");
2852 } else if (pin2 == -1) {
2859 * Ok, does IRQ0 through the IOAPIC work?
2862 add_pin_to_irq_node(cfg, node, apic1, pin1);
2863 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2865 /* for edge trigger, setup_IO_APIC_irq already
2866 * leave it unmasked.
2867 * so only need to unmask if it is level-trigger
2868 * do we really have level trigger timer?
2871 idx = find_irq_entry(apic1, pin1, mp_INT);
2872 if (idx != -1 && irq_trigger(idx))
2873 unmask_IO_APIC_irq_desc(desc);
2875 if (timer_irq_works()) {
2876 if (nmi_watchdog == NMI_IO_APIC) {
2878 enable_8259A_irq(0);
2880 if (disable_timer_pin_1 > 0)
2881 clear_IO_APIC_pin(0, pin1);
2884 if (intr_remapping_enabled)
2885 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2886 local_irq_disable();
2887 clear_IO_APIC_pin(apic1, pin1);
2889 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2890 "8254 timer not connected to IO-APIC\n");
2892 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2893 "(IRQ0) through the 8259A ...\n");
2894 apic_printk(APIC_QUIET, KERN_INFO
2895 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2897 * legacy devices should be connected to IO APIC #0
2899 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2900 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2901 enable_8259A_irq(0);
2902 if (timer_irq_works()) {
2903 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2904 timer_through_8259 = 1;
2905 if (nmi_watchdog == NMI_IO_APIC) {
2906 disable_8259A_irq(0);
2908 enable_8259A_irq(0);
2913 * Cleanup, just in case ...
2915 local_irq_disable();
2916 disable_8259A_irq(0);
2917 clear_IO_APIC_pin(apic2, pin2);
2918 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2921 if (nmi_watchdog == NMI_IO_APIC) {
2922 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2923 "through the IO-APIC - disabling NMI Watchdog!\n");
2924 nmi_watchdog = NMI_NONE;
2926 #ifdef CONFIG_X86_32
2930 apic_printk(APIC_QUIET, KERN_INFO
2931 "...trying to set up timer as Virtual Wire IRQ...\n");
2933 lapic_register_intr(0, desc);
2934 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2935 enable_8259A_irq(0);
2937 if (timer_irq_works()) {
2938 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2941 local_irq_disable();
2942 disable_8259A_irq(0);
2943 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2944 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2946 apic_printk(APIC_QUIET, KERN_INFO
2947 "...trying to set up timer as ExtINT IRQ...\n");
2951 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2953 unlock_ExtINT_logic();
2955 if (timer_irq_works()) {
2956 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2959 local_irq_disable();
2960 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2961 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2962 "report. Then try booting with the 'noapic' option.\n");
2964 local_irq_restore(flags);
2968 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2969 * to devices. However there may be an I/O APIC pin available for
2970 * this interrupt regardless. The pin may be left unconnected, but
2971 * typically it will be reused as an ExtINT cascade interrupt for
2972 * the master 8259A. In the MPS case such a pin will normally be
2973 * reported as an ExtINT interrupt in the MP table. With ACPI
2974 * there is no provision for ExtINT interrupts, and in the absence
2975 * of an override it would be treated as an ordinary ISA I/O APIC
2976 * interrupt, that is edge-triggered and unmasked by default. We
2977 * used to do this, but it caused problems on some systems because
2978 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2979 * the same ExtINT cascade interrupt to drive the local APIC of the
2980 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2981 * the I/O APIC in all cases now. No actual device should request
2982 * it anyway. --macro
2984 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2986 void __init setup_IO_APIC(void)
2990 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2993 io_apic_irqs = ~PIC_IRQS;
2995 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2997 * Set up IO-APIC IRQ routing.
2999 #ifdef CONFIG_X86_32
3001 setup_ioapic_ids_from_mpc();
3004 setup_IO_APIC_irqs();
3005 init_IO_APIC_traps();
3010 * Called after all the initialization is done. If we didnt find any
3011 * APIC bugs then we can allow the modify fast path
3014 static int __init io_apic_bug_finalize(void)
3016 if (sis_apic_bug == -1)
3021 late_initcall(io_apic_bug_finalize);
3023 struct sysfs_ioapic_data {
3024 struct sys_device dev;
3025 struct IO_APIC_route_entry entry[0];
3027 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3029 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3031 struct IO_APIC_route_entry *entry;
3032 struct sysfs_ioapic_data *data;
3035 data = container_of(dev, struct sysfs_ioapic_data, dev);
3036 entry = data->entry;
3037 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3038 *entry = ioapic_read_entry(dev->id, i);
3043 static int ioapic_resume(struct sys_device *dev)
3045 struct IO_APIC_route_entry *entry;
3046 struct sysfs_ioapic_data *data;
3047 unsigned long flags;
3048 union IO_APIC_reg_00 reg_00;
3051 data = container_of(dev, struct sysfs_ioapic_data, dev);
3052 entry = data->entry;
3054 spin_lock_irqsave(&ioapic_lock, flags);
3055 reg_00.raw = io_apic_read(dev->id, 0);
3056 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3057 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3058 io_apic_write(dev->id, 0, reg_00.raw);
3060 spin_unlock_irqrestore(&ioapic_lock, flags);
3061 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3062 ioapic_write_entry(dev->id, i, entry[i]);
3067 static struct sysdev_class ioapic_sysdev_class = {
3069 .suspend = ioapic_suspend,
3070 .resume = ioapic_resume,
3073 static int __init ioapic_init_sysfs(void)
3075 struct sys_device * dev;
3078 error = sysdev_class_register(&ioapic_sysdev_class);
3082 for (i = 0; i < nr_ioapics; i++ ) {
3083 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3084 * sizeof(struct IO_APIC_route_entry);
3085 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3086 if (!mp_ioapic_data[i]) {
3087 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3090 dev = &mp_ioapic_data[i]->dev;
3092 dev->cls = &ioapic_sysdev_class;
3093 error = sysdev_register(dev);
3095 kfree(mp_ioapic_data[i]);
3096 mp_ioapic_data[i] = NULL;
3097 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3105 device_initcall(ioapic_init_sysfs);
3107 static int nr_irqs_gsi = NR_IRQS_LEGACY;
3109 * Dynamic irq allocate and deallocation
3111 unsigned int create_irq_nr(unsigned int irq_want, int node)
3113 /* Allocate an unused irq */
3116 unsigned long flags;
3117 struct irq_cfg *cfg_new = NULL;
3118 struct irq_desc *desc_new = NULL;
3121 if (irq_want < nr_irqs_gsi)
3122 irq_want = nr_irqs_gsi;
3124 spin_lock_irqsave(&vector_lock, flags);
3125 for (new = irq_want; new < nr_irqs; new++) {
3126 desc_new = irq_to_desc_alloc_node(new, node);
3128 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3131 cfg_new = desc_new->chip_data;
3133 if (cfg_new->vector != 0)
3136 desc_new = move_irq_desc(desc_new, node);
3138 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3142 spin_unlock_irqrestore(&vector_lock, flags);
3145 dynamic_irq_init(irq);
3146 /* restore it, in case dynamic_irq_init clear it */
3148 desc_new->chip_data = cfg_new;
3153 int create_irq(void)
3155 int node = cpu_to_node(boot_cpu_id);
3156 unsigned int irq_want;
3159 irq_want = nr_irqs_gsi;
3160 irq = create_irq_nr(irq_want, node);
3168 void destroy_irq(unsigned int irq)
3170 unsigned long flags;
3171 struct irq_cfg *cfg;
3172 struct irq_desc *desc;
3174 /* store it, in case dynamic_irq_cleanup clear it */
3175 desc = irq_to_desc(irq);
3176 cfg = desc->chip_data;
3177 dynamic_irq_cleanup(irq);
3178 /* connect back irq_cfg */
3179 desc->chip_data = cfg;
3182 spin_lock_irqsave(&vector_lock, flags);
3183 __clear_irq_vector(irq, cfg);
3184 spin_unlock_irqrestore(&vector_lock, flags);
3188 * MSI message composition
3190 #ifdef CONFIG_PCI_MSI
3191 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3193 struct irq_cfg *cfg;
3201 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3205 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3207 if (irq_remapped(irq)) {
3212 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3213 BUG_ON(ir_index == -1);
3215 memset (&irte, 0, sizeof(irte));
3218 irte.dst_mode = apic->irq_dest_mode;
3219 irte.trigger_mode = 0; /* edge */
3220 irte.dlvry_mode = apic->irq_delivery_mode;
3221 irte.vector = cfg->vector;
3222 irte.dest_id = IRTE_DEST(dest);
3224 /* Set source-id of interrupt request */
3225 set_msi_sid(&irte, pdev);
3227 modify_irte(irq, &irte);
3229 msg->address_hi = MSI_ADDR_BASE_HI;
3230 msg->data = sub_handle;
3231 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3233 MSI_ADDR_IR_INDEX1(ir_index) |
3234 MSI_ADDR_IR_INDEX2(ir_index);
3236 if (x2apic_enabled())
3237 msg->address_hi = MSI_ADDR_BASE_HI |
3238 MSI_ADDR_EXT_DEST_ID(dest);
3240 msg->address_hi = MSI_ADDR_BASE_HI;
3244 ((apic->irq_dest_mode == 0) ?
3245 MSI_ADDR_DEST_MODE_PHYSICAL:
3246 MSI_ADDR_DEST_MODE_LOGICAL) |
3247 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3248 MSI_ADDR_REDIRECTION_CPU:
3249 MSI_ADDR_REDIRECTION_LOWPRI) |
3250 MSI_ADDR_DEST_ID(dest);
3253 MSI_DATA_TRIGGER_EDGE |
3254 MSI_DATA_LEVEL_ASSERT |
3255 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3256 MSI_DATA_DELIVERY_FIXED:
3257 MSI_DATA_DELIVERY_LOWPRI) |
3258 MSI_DATA_VECTOR(cfg->vector);
3264 static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3266 struct irq_desc *desc = irq_to_desc(irq);
3267 struct irq_cfg *cfg;
3271 dest = set_desc_affinity(desc, mask);
3272 if (dest == BAD_APICID)
3275 cfg = desc->chip_data;
3277 read_msi_msg_desc(desc, &msg);
3279 msg.data &= ~MSI_DATA_VECTOR_MASK;
3280 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3281 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3282 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3284 write_msi_msg_desc(desc, &msg);
3288 #ifdef CONFIG_INTR_REMAP
3290 * Migrate the MSI irq to another cpumask. This migration is
3291 * done in the process context using interrupt-remapping hardware.
3294 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3296 struct irq_desc *desc = irq_to_desc(irq);
3297 struct irq_cfg *cfg = desc->chip_data;
3301 if (get_irte(irq, &irte))
3304 dest = set_desc_affinity(desc, mask);
3305 if (dest == BAD_APICID)
3308 irte.vector = cfg->vector;
3309 irte.dest_id = IRTE_DEST(dest);
3312 * atomically update the IRTE with the new destination and vector.
3314 modify_irte(irq, &irte);
3317 * After this point, all the interrupts will start arriving
3318 * at the new destination. So, time to cleanup the previous
3319 * vector allocation.
3321 if (cfg->move_in_progress)
3322 send_cleanup_vector(cfg);
3328 #endif /* CONFIG_SMP */
3331 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3332 * which implement the MSI or MSI-X Capability Structure.
3334 static struct irq_chip msi_chip = {
3336 .unmask = unmask_msi_irq,
3337 .mask = mask_msi_irq,
3338 .ack = ack_apic_edge,
3340 .set_affinity = set_msi_irq_affinity,
3342 .retrigger = ioapic_retrigger_irq,
3345 static struct irq_chip msi_ir_chip = {
3346 .name = "IR-PCI-MSI",
3347 .unmask = unmask_msi_irq,
3348 .mask = mask_msi_irq,
3349 #ifdef CONFIG_INTR_REMAP
3350 .ack = ir_ack_apic_edge,
3352 .set_affinity = ir_set_msi_irq_affinity,
3355 .retrigger = ioapic_retrigger_irq,
3359 * Map the PCI dev to the corresponding remapping hardware unit
3360 * and allocate 'nvec' consecutive interrupt-remapping table entries
3363 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3365 struct intel_iommu *iommu;
3368 iommu = map_dev_to_ir(dev);
3371 "Unable to map PCI %s to iommu\n", pci_name(dev));
3375 index = alloc_irte(iommu, irq, nvec);
3378 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3385 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3390 ret = msi_compose_msg(dev, irq, &msg);
3394 set_irq_msi(irq, msidesc);
3395 write_msi_msg(irq, &msg);
3397 if (irq_remapped(irq)) {
3398 struct irq_desc *desc = irq_to_desc(irq);
3400 * irq migration in process context
3402 desc->status |= IRQ_MOVE_PCNTXT;
3403 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3405 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3407 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3412 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3415 int ret, sub_handle;
3416 struct msi_desc *msidesc;
3417 unsigned int irq_want;
3418 struct intel_iommu *iommu = NULL;
3422 /* x86 doesn't support multiple MSI yet */
3423 if (type == PCI_CAP_ID_MSI && nvec > 1)
3426 node = dev_to_node(&dev->dev);
3427 irq_want = nr_irqs_gsi;
3429 list_for_each_entry(msidesc, &dev->msi_list, list) {
3430 irq = create_irq_nr(irq_want, node);
3434 if (!intr_remapping_enabled)
3439 * allocate the consecutive block of IRTE's
3442 index = msi_alloc_irte(dev, irq, nvec);
3448 iommu = map_dev_to_ir(dev);
3454 * setup the mapping between the irq and the IRTE
3455 * base index, the sub_handle pointing to the
3456 * appropriate interrupt remap table entry.
3458 set_irte_irq(irq, iommu, index, sub_handle);
3461 ret = setup_msi_irq(dev, msidesc, irq);
3473 void arch_teardown_msi_irq(unsigned int irq)
3478 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3480 static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3482 struct irq_desc *desc = irq_to_desc(irq);
3483 struct irq_cfg *cfg;
3487 dest = set_desc_affinity(desc, mask);
3488 if (dest == BAD_APICID)
3491 cfg = desc->chip_data;
3493 dmar_msi_read(irq, &msg);
3495 msg.data &= ~MSI_DATA_VECTOR_MASK;
3496 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3497 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3498 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3500 dmar_msi_write(irq, &msg);
3505 #endif /* CONFIG_SMP */
3507 static struct irq_chip dmar_msi_type = {
3509 .unmask = dmar_msi_unmask,
3510 .mask = dmar_msi_mask,
3511 .ack = ack_apic_edge,
3513 .set_affinity = dmar_msi_set_affinity,
3515 .retrigger = ioapic_retrigger_irq,
3518 int arch_setup_dmar_msi(unsigned int irq)
3523 ret = msi_compose_msg(NULL, irq, &msg);
3526 dmar_msi_write(irq, &msg);
3527 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3533 #ifdef CONFIG_HPET_TIMER
3536 static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3538 struct irq_desc *desc = irq_to_desc(irq);
3539 struct irq_cfg *cfg;
3543 dest = set_desc_affinity(desc, mask);
3544 if (dest == BAD_APICID)
3547 cfg = desc->chip_data;
3549 hpet_msi_read(irq, &msg);
3551 msg.data &= ~MSI_DATA_VECTOR_MASK;
3552 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3553 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3554 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3556 hpet_msi_write(irq, &msg);
3561 #endif /* CONFIG_SMP */
3563 static struct irq_chip hpet_msi_type = {
3565 .unmask = hpet_msi_unmask,
3566 .mask = hpet_msi_mask,
3567 .ack = ack_apic_edge,
3569 .set_affinity = hpet_msi_set_affinity,
3571 .retrigger = ioapic_retrigger_irq,
3574 int arch_setup_hpet_msi(unsigned int irq)
3578 struct irq_desc *desc = irq_to_desc(irq);
3580 ret = msi_compose_msg(NULL, irq, &msg);
3584 hpet_msi_write(irq, &msg);
3585 desc->status |= IRQ_MOVE_PCNTXT;
3586 set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3593 #endif /* CONFIG_PCI_MSI */
3595 * Hypertransport interrupt support
3597 #ifdef CONFIG_HT_IRQ
3601 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3603 struct ht_irq_msg msg;
3604 fetch_ht_irq_msg(irq, &msg);
3606 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3607 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3609 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3610 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3612 write_ht_irq_msg(irq, &msg);
3615 static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3617 struct irq_desc *desc = irq_to_desc(irq);
3618 struct irq_cfg *cfg;
3621 dest = set_desc_affinity(desc, mask);
3622 if (dest == BAD_APICID)
3625 cfg = desc->chip_data;
3627 target_ht_irq(irq, dest, cfg->vector);
3634 static struct irq_chip ht_irq_chip = {
3636 .mask = mask_ht_irq,
3637 .unmask = unmask_ht_irq,
3638 .ack = ack_apic_edge,
3640 .set_affinity = set_ht_irq_affinity,
3642 .retrigger = ioapic_retrigger_irq,
3645 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3647 struct irq_cfg *cfg;
3654 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3656 struct ht_irq_msg msg;
3659 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3660 apic->target_cpus());
3662 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3666 HT_IRQ_LOW_DEST_ID(dest) |
3667 HT_IRQ_LOW_VECTOR(cfg->vector) |
3668 ((apic->irq_dest_mode == 0) ?
3669 HT_IRQ_LOW_DM_PHYSICAL :
3670 HT_IRQ_LOW_DM_LOGICAL) |
3671 HT_IRQ_LOW_RQEOI_EDGE |
3672 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3673 HT_IRQ_LOW_MT_FIXED :
3674 HT_IRQ_LOW_MT_ARBITRATED) |
3675 HT_IRQ_LOW_IRQ_MASKED;
3677 write_ht_irq_msg(irq, &msg);
3679 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3680 handle_edge_irq, "edge");
3682 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3686 #endif /* CONFIG_HT_IRQ */
3688 #ifdef CONFIG_X86_UV
3690 * Re-target the irq to the specified CPU and enable the specified MMR located
3691 * on the specified blade to allow the sending of MSIs to the specified CPU.
3693 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3694 unsigned long mmr_offset)
3696 const struct cpumask *eligible_cpu = cpumask_of(cpu);
3697 struct irq_cfg *cfg;
3699 unsigned long mmr_value;
3700 struct uv_IO_APIC_route_entry *entry;
3701 unsigned long flags;
3704 BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3708 err = assign_irq_vector(irq, cfg, eligible_cpu);
3712 spin_lock_irqsave(&vector_lock, flags);
3713 set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3715 spin_unlock_irqrestore(&vector_lock, flags);
3718 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3719 entry->vector = cfg->vector;
3720 entry->delivery_mode = apic->irq_delivery_mode;
3721 entry->dest_mode = apic->irq_dest_mode;
3722 entry->polarity = 0;
3725 entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
3727 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3728 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3734 * Disable the specified MMR located on the specified blade so that MSIs are
3735 * longer allowed to be sent.
3737 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3739 unsigned long mmr_value;
3740 struct uv_IO_APIC_route_entry *entry;
3743 BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3746 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3749 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3750 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3752 #endif /* CONFIG_X86_64 */
3754 int __init io_apic_get_redir_entries (int ioapic)
3756 union IO_APIC_reg_01 reg_01;
3757 unsigned long flags;
3759 spin_lock_irqsave(&ioapic_lock, flags);
3760 reg_01.raw = io_apic_read(ioapic, 1);
3761 spin_unlock_irqrestore(&ioapic_lock, flags);
3763 return reg_01.bits.entries;
3766 void __init probe_nr_irqs_gsi(void)
3770 nr = acpi_probe_gsi();
3771 if (nr > nr_irqs_gsi) {
3774 /* for acpi=off or acpi is not compiled in */
3778 for (idx = 0; idx < nr_ioapics; idx++)
3779 nr += io_apic_get_redir_entries(idx) + 1;
3781 if (nr > nr_irqs_gsi)
3785 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3788 #ifdef CONFIG_SPARSE_IRQ
3789 int __init arch_probe_nr_irqs(void)
3793 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3794 nr_irqs = NR_VECTORS * nr_cpu_ids;
3796 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3797 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3799 * for MSI and HT dyn irq
3801 nr += nr_irqs_gsi * 16;
3810 static int __io_apic_set_pci_routing(struct device *dev, int irq,
3811 struct io_apic_irq_attr *irq_attr)
3813 struct irq_desc *desc;
3814 struct irq_cfg *cfg;
3817 int trigger, polarity;
3819 ioapic = irq_attr->ioapic;
3820 if (!IO_APIC_IRQ(irq)) {
3821 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3827 node = dev_to_node(dev);
3829 node = cpu_to_node(boot_cpu_id);
3831 desc = irq_to_desc_alloc_node(irq, node);
3833 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3837 pin = irq_attr->ioapic_pin;
3838 trigger = irq_attr->trigger;
3839 polarity = irq_attr->polarity;
3842 * IRQs < 16 are already in the irq_2_pin[] map
3844 if (irq >= NR_IRQS_LEGACY) {
3845 cfg = desc->chip_data;
3846 add_pin_to_irq_node(cfg, node, ioapic, pin);
3849 setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity);
3854 int io_apic_set_pci_routing(struct device *dev, int irq,
3855 struct io_apic_irq_attr *irq_attr)
3859 * Avoid pin reprogramming. PRTs typically include entries
3860 * with redundant pin->gsi mappings (but unique PCI devices);
3861 * we only program the IOAPIC on the first.
3863 ioapic = irq_attr->ioapic;
3864 pin = irq_attr->ioapic_pin;
3865 if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) {
3866 pr_debug("Pin %d-%d already programmed\n",
3867 mp_ioapics[ioapic].apicid, pin);
3870 set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed);
3872 return __io_apic_set_pci_routing(dev, irq, irq_attr);
3875 /* --------------------------------------------------------------------------
3876 ACPI-based IOAPIC Configuration
3877 -------------------------------------------------------------------------- */
3881 #ifdef CONFIG_X86_32
3882 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3884 union IO_APIC_reg_00 reg_00;
3885 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3887 unsigned long flags;
3891 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3892 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3893 * supports up to 16 on one shared APIC bus.
3895 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3896 * advantage of new APIC bus architecture.
3899 if (physids_empty(apic_id_map))
3900 apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
3902 spin_lock_irqsave(&ioapic_lock, flags);
3903 reg_00.raw = io_apic_read(ioapic, 0);
3904 spin_unlock_irqrestore(&ioapic_lock, flags);
3906 if (apic_id >= get_physical_broadcast()) {
3907 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3908 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3909 apic_id = reg_00.bits.ID;
3913 * Every APIC in a system must have a unique ID or we get lots of nice
3914 * 'stuck on smp_invalidate_needed IPI wait' messages.
3916 if (apic->check_apicid_used(apic_id_map, apic_id)) {
3918 for (i = 0; i < get_physical_broadcast(); i++) {
3919 if (!apic->check_apicid_used(apic_id_map, i))
3923 if (i == get_physical_broadcast())
3924 panic("Max apic_id exceeded!\n");
3926 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3927 "trying %d\n", ioapic, apic_id, i);
3932 tmp = apic->apicid_to_cpu_present(apic_id);
3933 physids_or(apic_id_map, apic_id_map, tmp);
3935 if (reg_00.bits.ID != apic_id) {
3936 reg_00.bits.ID = apic_id;
3938 spin_lock_irqsave(&ioapic_lock, flags);
3939 io_apic_write(ioapic, 0, reg_00.raw);
3940 reg_00.raw = io_apic_read(ioapic, 0);
3941 spin_unlock_irqrestore(&ioapic_lock, flags);
3944 if (reg_00.bits.ID != apic_id) {
3945 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3950 apic_printk(APIC_VERBOSE, KERN_INFO
3951 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3957 int __init io_apic_get_version(int ioapic)
3959 union IO_APIC_reg_01 reg_01;
3960 unsigned long flags;
3962 spin_lock_irqsave(&ioapic_lock, flags);
3963 reg_01.raw = io_apic_read(ioapic, 1);
3964 spin_unlock_irqrestore(&ioapic_lock, flags);
3966 return reg_01.bits.version;
3969 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3973 if (skip_ioapic_setup)
3976 for (i = 0; i < mp_irq_entries; i++)
3977 if (mp_irqs[i].irqtype == mp_INT &&
3978 mp_irqs[i].srcbusirq == bus_irq)
3980 if (i >= mp_irq_entries)
3983 *trigger = irq_trigger(i);
3984 *polarity = irq_polarity(i);
3988 #endif /* CONFIG_ACPI */
3991 * This function currently is only a helper for the i386 smp boot process where
3992 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3993 * so mask in all cases should simply be apic->target_cpus()
3996 void __init setup_ioapic_dest(void)
3998 int pin, ioapic = 0, irq, irq_entry;
3999 struct irq_desc *desc;
4000 const struct cpumask *mask;
4002 if (skip_ioapic_setup == 1)
4006 if (!acpi_disabled && acpi_ioapic) {
4007 ioapic = mp_find_ioapic(0);
4013 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4014 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4015 if (irq_entry == -1)
4017 irq = pin_2_irq(irq_entry, ioapic, pin);
4019 desc = irq_to_desc(irq);
4022 * Honour affinities which have been set in early boot
4025 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4026 mask = desc->affinity;
4028 mask = apic->target_cpus();
4030 if (intr_remapping_enabled)
4031 set_ir_ioapic_affinity_irq_desc(desc, mask);
4033 set_ioapic_affinity_irq_desc(desc, mask);
4039 #define IOAPIC_RESOURCE_NAME_SIZE 11
4041 static struct resource *ioapic_resources;
4043 static struct resource * __init ioapic_setup_resources(void)
4046 struct resource *res;
4050 if (nr_ioapics <= 0)
4053 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4056 mem = alloc_bootmem(n);
4060 mem += sizeof(struct resource) * nr_ioapics;
4062 for (i = 0; i < nr_ioapics; i++) {
4064 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4065 sprintf(mem, "IOAPIC %u", i);
4066 mem += IOAPIC_RESOURCE_NAME_SIZE;
4070 ioapic_resources = res;
4075 void __init ioapic_init_mappings(void)
4077 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4078 struct resource *ioapic_res;
4081 ioapic_res = ioapic_setup_resources();
4082 for (i = 0; i < nr_ioapics; i++) {
4083 if (smp_found_config) {
4084 ioapic_phys = mp_ioapics[i].apicaddr;
4085 #ifdef CONFIG_X86_32
4088 "WARNING: bogus zero IO-APIC "
4089 "address found in MPTABLE, "
4090 "disabling IO/APIC support!\n");
4091 smp_found_config = 0;
4092 skip_ioapic_setup = 1;
4093 goto fake_ioapic_page;
4097 #ifdef CONFIG_X86_32
4100 ioapic_phys = (unsigned long)
4101 alloc_bootmem_pages(PAGE_SIZE);
4102 ioapic_phys = __pa(ioapic_phys);
4104 set_fixmap_nocache(idx, ioapic_phys);
4105 apic_printk(APIC_VERBOSE,
4106 "mapped IOAPIC to %08lx (%08lx)\n",
4107 __fix_to_virt(idx), ioapic_phys);
4110 if (ioapic_res != NULL) {
4111 ioapic_res->start = ioapic_phys;
4112 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4118 static int __init ioapic_insert_resources(void)
4121 struct resource *r = ioapic_resources;
4124 if (nr_ioapics > 0) {
4126 "IO APIC resources couldn't be allocated.\n");
4132 for (i = 0; i < nr_ioapics; i++) {
4133 insert_resource(&iomem_resource, r);
4140 /* Insert the IO APIC resources after PCI initialization has occured to handle
4141 * IO APICS that are mapped in on a BAR in PCI space. */
4142 late_initcall(ioapic_insert_resources);