2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/kernel_stat.h>
18 #include <linux/mc146818rtc.h>
19 #include <linux/acpi_pmtmr.h>
20 #include <linux/clockchips.h>
21 #include <linux/interrupt.h>
22 #include <linux/bootmem.h>
23 #include <linux/ftrace.h>
24 #include <linux/ioport.h>
25 #include <linux/module.h>
26 #include <linux/sysdev.h>
27 #include <linux/delay.h>
28 #include <linux/timex.h>
29 #include <linux/dmar.h>
30 #include <linux/init.h>
31 #include <linux/cpu.h>
32 #include <linux/dmi.h>
33 #include <linux/nmi.h>
34 #include <linux/smp.h>
37 #include <asm/pgalloc.h>
38 #include <asm/atomic.h>
39 #include <asm/mpspec.h>
40 #include <asm/i8253.h>
41 #include <asm/i8259.h>
42 #include <asm/proto.h>
51 unsigned int num_processors;
53 unsigned disabled_cpus __cpuinitdata;
55 /* Processor that is doing the boot up */
56 unsigned int boot_cpu_physical_apicid = -1U;
59 * The highest APIC ID seen during enumeration.
61 * This determines the messaging protocol we can use: if all APIC IDs
62 * are in the 0 ... 7 range, then we can use logical addressing which
63 * has some performance advantages (better broadcasting).
65 * If there's an APIC ID above 8, we use physical addressing.
67 unsigned int max_physical_apicid;
70 * Bitmask of physically existing CPUs:
72 physid_mask_t phys_cpu_present_map;
75 * Map cpu index to physical APIC ID
77 DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID);
78 DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID);
79 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
80 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
84 * Knob to control our willingness to enable the local APIC.
88 static int force_enable_local_apic;
90 * APIC command line parameters
92 static int __init parse_lapic(char *arg)
94 force_enable_local_apic = 1;
97 early_param("lapic", parse_lapic);
98 /* Local APIC was disabled by the BIOS and enabled by the kernel */
99 static int enabled_via_apicbase;
102 * Handle interrupt mode configuration register (IMCR).
103 * This register controls whether the interrupt signals
104 * that reach the BSP come from the master PIC or from the
105 * local APIC. Before entering Symmetric I/O Mode, either
106 * the BIOS or the operating system must switch out of
107 * PIC Mode by changing the IMCR.
109 static inline void imcr_pic_to_apic(void)
111 /* select IMCR register */
113 /* NMI and 8259 INTR go through APIC */
117 static inline void imcr_apic_to_pic(void)
119 /* select IMCR register */
121 /* NMI and 8259 INTR go directly to BSP */
127 static int apic_calibrate_pmtmr __initdata;
128 static __init int setup_apicpmtimer(char *s)
130 apic_calibrate_pmtmr = 1;
134 __setup("apicpmtimer", setup_apicpmtimer);
137 #ifdef CONFIG_X86_X2APIC
139 /* x2apic enabled before OS handover */
140 static int x2apic_preenabled;
141 static int disable_x2apic;
142 static __init int setup_nox2apic(char *str)
145 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
148 early_param("nox2apic", setup_nox2apic);
151 unsigned long mp_lapic_addr;
153 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
154 static int disable_apic_timer __cpuinitdata;
155 /* Local APIC timer works in C2 */
156 int local_apic_timer_c2_ok;
157 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
159 int first_system_vector = 0xfe;
162 * Debug level, exported for io_apic.c
164 unsigned int apic_verbosity;
168 /* Have we found an MP table */
169 int smp_found_config;
171 static struct resource lapic_resource = {
172 .name = "Local APIC",
173 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
176 static unsigned int calibration_result;
178 static int lapic_next_event(unsigned long delta,
179 struct clock_event_device *evt);
180 static void lapic_timer_setup(enum clock_event_mode mode,
181 struct clock_event_device *evt);
182 static void lapic_timer_broadcast(const struct cpumask *mask);
183 static void apic_pm_activate(void);
186 * The local apic timer can be used for any function which is CPU local.
188 static struct clock_event_device lapic_clockevent = {
190 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
191 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
193 .set_mode = lapic_timer_setup,
194 .set_next_event = lapic_next_event,
195 .broadcast = lapic_timer_broadcast,
199 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
201 static unsigned long apic_phys;
204 * Get the LAPIC version
206 static inline int lapic_get_version(void)
208 return GET_APIC_VERSION(apic_read(APIC_LVR));
212 * Check, if the APIC is integrated or a separate chip
214 static inline int lapic_is_integrated(void)
219 return APIC_INTEGRATED(lapic_get_version());
224 * Check, whether this is a modern or a first generation APIC
226 static int modern_apic(void)
228 /* AMD systems use old APIC versions, so check the CPU */
229 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
230 boot_cpu_data.x86 >= 0xf)
232 return lapic_get_version() >= 0x14;
236 * bare function to substitute write operation
237 * and it's _that_ fast :)
239 void native_apic_write_dummy(u32 reg, u32 v)
241 WARN_ON_ONCE((cpu_has_apic || !disable_apic));
245 * right after this call apic->write doesn't do anything
246 * note that there is no restore operation it works one way
248 void apic_disable(void)
250 apic->write = native_apic_write_dummy;
253 void native_apic_wait_icr_idle(void)
255 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
259 u32 native_safe_apic_wait_icr_idle(void)
266 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
270 } while (timeout++ < 1000);
275 void native_apic_icr_write(u32 low, u32 id)
277 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
278 apic_write(APIC_ICR, low);
281 u64 native_apic_icr_read(void)
285 icr2 = apic_read(APIC_ICR2);
286 icr1 = apic_read(APIC_ICR);
288 return icr1 | ((u64)icr2 << 32);
292 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
294 void __cpuinit enable_NMI_through_LVT0(void)
298 /* unmask and set to NMI */
301 /* Level triggered for 82489DX (32bit mode) */
302 if (!lapic_is_integrated())
303 v |= APIC_LVT_LEVEL_TRIGGER;
305 apic_write(APIC_LVT0, v);
310 * get_physical_broadcast - Get number of physical broadcast IDs
312 int get_physical_broadcast(void)
314 return modern_apic() ? 0xff : 0xf;
319 * lapic_get_maxlvt - get the maximum number of local vector table entries
321 int lapic_get_maxlvt(void)
325 v = apic_read(APIC_LVR);
327 * - we always have APIC integrated on 64bit mode
328 * - 82489DXs do not report # of LVT entries
330 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
338 #define APIC_DIVISOR 16
341 * This function sets up the local APIC timer, with a timeout of
342 * 'clocks' APIC bus clock. During calibration we actually call
343 * this function twice on the boot CPU, once with a bogus timeout
344 * value, second time for real. The other (noncalibrating) CPUs
345 * call this function only once, with the real, calibrated value.
347 * We do reads before writes even if unnecessary, to get around the
348 * P5 APIC double write bug.
350 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
352 unsigned int lvtt_value, tmp_value;
354 lvtt_value = LOCAL_TIMER_VECTOR;
356 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
357 if (!lapic_is_integrated())
358 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
361 lvtt_value |= APIC_LVT_MASKED;
363 apic_write(APIC_LVTT, lvtt_value);
368 tmp_value = apic_read(APIC_TDCR);
369 apic_write(APIC_TDCR,
370 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
374 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
378 * Setup extended LVT, AMD specific (K8, family 10h)
380 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
381 * MCE interrupts are supported. Thus MCE offset must be set to 0.
383 * If mask=1, the LVT entry does not generate interrupts while mask=0
384 * enables the vector. See also the BKDGs.
387 #define APIC_EILVT_LVTOFF_MCE 0
388 #define APIC_EILVT_LVTOFF_IBS 1
390 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
392 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
393 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
398 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
400 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
401 return APIC_EILVT_LVTOFF_MCE;
404 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
406 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
407 return APIC_EILVT_LVTOFF_IBS;
409 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs);
412 * Program the next event, relative to now
414 static int lapic_next_event(unsigned long delta,
415 struct clock_event_device *evt)
417 apic_write(APIC_TMICT, delta);
422 * Setup the lapic timer in periodic or oneshot mode
424 static void lapic_timer_setup(enum clock_event_mode mode,
425 struct clock_event_device *evt)
430 /* Lapic used as dummy for broadcast ? */
431 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
434 local_irq_save(flags);
437 case CLOCK_EVT_MODE_PERIODIC:
438 case CLOCK_EVT_MODE_ONESHOT:
439 __setup_APIC_LVTT(calibration_result,
440 mode != CLOCK_EVT_MODE_PERIODIC, 1);
442 case CLOCK_EVT_MODE_UNUSED:
443 case CLOCK_EVT_MODE_SHUTDOWN:
444 v = apic_read(APIC_LVTT);
445 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
446 apic_write(APIC_LVTT, v);
447 apic_write(APIC_TMICT, 0xffffffff);
449 case CLOCK_EVT_MODE_RESUME:
450 /* Nothing to do here */
454 local_irq_restore(flags);
458 * Local APIC timer broadcast function
460 static void lapic_timer_broadcast(const struct cpumask *mask)
463 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
468 * Setup the local APIC timer for this CPU. Copy the initilized values
469 * of the boot CPU and register the clock event in the framework.
471 static void __cpuinit setup_APIC_timer(void)
473 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
475 if (cpu_has(¤t_cpu_data, X86_FEATURE_ARAT)) {
476 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
477 /* Make LAPIC timer preferrable over percpu HPET */
478 lapic_clockevent.rating = 150;
481 memcpy(levt, &lapic_clockevent, sizeof(*levt));
482 levt->cpumask = cpumask_of(smp_processor_id());
484 clockevents_register_device(levt);
488 * In this functions we calibrate APIC bus clocks to the external timer.
490 * We want to do the calibration only once since we want to have local timer
491 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
494 * This was previously done by reading the PIT/HPET and waiting for a wrap
495 * around to find out, that a tick has elapsed. I have a box, where the PIT
496 * readout is broken, so it never gets out of the wait loop again. This was
497 * also reported by others.
499 * Monitoring the jiffies value is inaccurate and the clockevents
500 * infrastructure allows us to do a simple substitution of the interrupt
503 * The calibration routine also uses the pm_timer when possible, as the PIT
504 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
505 * back to normal later in the boot process).
508 #define LAPIC_CAL_LOOPS (HZ/10)
510 static __initdata int lapic_cal_loops = -1;
511 static __initdata long lapic_cal_t1, lapic_cal_t2;
512 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
513 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
514 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
517 * Temporary interrupt handler.
519 static void __init lapic_cal_handler(struct clock_event_device *dev)
521 unsigned long long tsc = 0;
522 long tapic = apic_read(APIC_TMCCT);
523 unsigned long pm = acpi_pm_read_early();
528 switch (lapic_cal_loops++) {
530 lapic_cal_t1 = tapic;
531 lapic_cal_tsc1 = tsc;
533 lapic_cal_j1 = jiffies;
536 case LAPIC_CAL_LOOPS:
537 lapic_cal_t2 = tapic;
538 lapic_cal_tsc2 = tsc;
539 if (pm < lapic_cal_pm1)
540 pm += ACPI_PM_OVRRUN;
542 lapic_cal_j2 = jiffies;
548 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
550 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
551 const long pm_thresh = pm_100ms / 100;
555 #ifndef CONFIG_X86_PM_TIMER
559 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
561 /* Check, if the PM timer is available */
565 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
567 if (deltapm > (pm_100ms - pm_thresh) &&
568 deltapm < (pm_100ms + pm_thresh)) {
569 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
573 res = (((u64)deltapm) * mult) >> 22;
574 do_div(res, 1000000);
575 pr_warning("APIC calibration not consistent "
576 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
578 /* Correct the lapic counter value */
579 res = (((u64)(*delta)) * pm_100ms);
580 do_div(res, deltapm);
581 pr_info("APIC delta adjusted to PM-Timer: "
582 "%lu (%ld)\n", (unsigned long)res, *delta);
585 /* Correct the tsc counter value */
587 res = (((u64)(*deltatsc)) * pm_100ms);
588 do_div(res, deltapm);
589 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
590 "PM-Timer: %lu (%ld) \n",
591 (unsigned long)res, *deltatsc);
592 *deltatsc = (long)res;
598 static int __init calibrate_APIC_clock(void)
600 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
601 void (*real_handler)(struct clock_event_device *dev);
602 unsigned long deltaj;
603 long delta, deltatsc;
604 int pm_referenced = 0;
608 /* Replace the global interrupt handler */
609 real_handler = global_clock_event->event_handler;
610 global_clock_event->event_handler = lapic_cal_handler;
613 * Setup the APIC counter to maximum. There is no way the lapic
614 * can underflow in the 100ms detection time frame
616 __setup_APIC_LVTT(0xffffffff, 0, 0);
618 /* Let the interrupts run */
621 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
626 /* Restore the real event handler */
627 global_clock_event->event_handler = real_handler;
629 /* Build delta t1-t2 as apic timer counts down */
630 delta = lapic_cal_t1 - lapic_cal_t2;
631 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
633 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
635 /* we trust the PM based calibration if possible */
636 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
639 /* Calculate the scaled math multiplication factor */
640 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
641 lapic_clockevent.shift);
642 lapic_clockevent.max_delta_ns =
643 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
644 lapic_clockevent.min_delta_ns =
645 clockevent_delta2ns(0xF, &lapic_clockevent);
647 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
649 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
650 apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult);
651 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
655 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
657 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
658 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
661 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
663 calibration_result / (1000000 / HZ),
664 calibration_result % (1000000 / HZ));
667 * Do a sanity check on the APIC calibration result
669 if (calibration_result < (1000000 / HZ)) {
671 pr_warning("APIC frequency too slow, disabling apic timer\n");
675 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
678 * PM timer calibration failed or not turned on
679 * so lets try APIC timer based calibration
681 if (!pm_referenced) {
682 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
685 * Setup the apic timer manually
687 levt->event_handler = lapic_cal_handler;
688 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
689 lapic_cal_loops = -1;
691 /* Let the interrupts run */
694 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
697 /* Stop the lapic timer */
698 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
701 deltaj = lapic_cal_j2 - lapic_cal_j1;
702 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
704 /* Check, if the jiffies result is consistent */
705 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
706 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
708 levt->features |= CLOCK_EVT_FEAT_DUMMY;
712 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
713 pr_warning("APIC timer disabled due to verification failure\n");
721 * Setup the boot APIC
723 * Calibrate and verify the result.
725 void __init setup_boot_APIC_clock(void)
728 * The local apic timer can be disabled via the kernel
729 * commandline or from the CPU detection code. Register the lapic
730 * timer as a dummy clock event source on SMP systems, so the
731 * broadcast mechanism is used. On UP systems simply ignore it.
733 if (disable_apic_timer) {
734 pr_info("Disabling APIC timer\n");
735 /* No broadcast on UP ! */
736 if (num_possible_cpus() > 1) {
737 lapic_clockevent.mult = 1;
743 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
744 "calibrating APIC timer ...\n");
746 if (calibrate_APIC_clock()) {
747 /* No broadcast on UP ! */
748 if (num_possible_cpus() > 1)
754 * If nmi_watchdog is set to IO_APIC, we need the
755 * PIT/HPET going. Otherwise register lapic as a dummy
758 if (nmi_watchdog != NMI_IO_APIC)
759 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
761 pr_warning("APIC timer registered as dummy,"
762 " due to nmi_watchdog=%d!\n", nmi_watchdog);
764 /* Setup the lapic or request the broadcast */
768 void __cpuinit setup_secondary_APIC_clock(void)
774 * The guts of the apic timer interrupt
776 static void local_apic_timer_interrupt(void)
778 int cpu = smp_processor_id();
779 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
782 * Normally we should not be here till LAPIC has been initialized but
783 * in some cases like kdump, its possible that there is a pending LAPIC
784 * timer interrupt from previous kernel's context and is delivered in
785 * new kernel the moment interrupts are enabled.
787 * Interrupts are enabled early and LAPIC is setup much later, hence
788 * its possible that when we get here evt->event_handler is NULL.
789 * Check for event_handler being NULL and discard the interrupt as
792 if (!evt->event_handler) {
793 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
795 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
800 * the NMI deadlock-detector uses this.
802 inc_irq_stat(apic_timer_irqs);
804 evt->event_handler(evt);
808 * Local APIC timer interrupt. This is the most natural way for doing
809 * local interrupts, but local timer interrupts can be emulated by
810 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
812 * [ if a single-CPU system runs an SMP kernel then we call the local
813 * interrupt as well. Thus we cannot inline the local irq ... ]
815 void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
817 struct pt_regs *old_regs = set_irq_regs(regs);
820 * NOTE! We'd better ACK the irq immediately,
821 * because timer handling can be slow.
825 * update_process_times() expects us to have done irq_enter().
826 * Besides, if we don't timer interrupts ignore the global
827 * interrupt lock, which is the WrongThing (tm) to do.
831 local_apic_timer_interrupt();
834 set_irq_regs(old_regs);
837 int setup_profiling_timer(unsigned int multiplier)
843 * Local APIC start and shutdown
847 * clear_local_APIC - shutdown the local APIC
849 * This is called, when a CPU is disabled and before rebooting, so the state of
850 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
851 * leftovers during boot.
853 void clear_local_APIC(void)
858 /* APIC hasn't been mapped yet */
859 if (!x2apic && !apic_phys)
862 maxlvt = lapic_get_maxlvt();
864 * Masking an LVT entry can trigger a local APIC error
865 * if the vector is zero. Mask LVTERR first to prevent this.
868 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
869 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
872 * Careful: we have to set masks only first to deassert
873 * any level-triggered sources.
875 v = apic_read(APIC_LVTT);
876 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
877 v = apic_read(APIC_LVT0);
878 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
879 v = apic_read(APIC_LVT1);
880 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
882 v = apic_read(APIC_LVTPC);
883 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
886 /* lets not touch this if we didn't frob it */
887 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
889 v = apic_read(APIC_LVTTHMR);
890 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
893 #ifdef CONFIG_X86_MCE_INTEL
895 v = apic_read(APIC_LVTCMCI);
896 if (!(v & APIC_LVT_MASKED))
897 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
902 * Clean APIC state for other OSs:
904 apic_write(APIC_LVTT, APIC_LVT_MASKED);
905 apic_write(APIC_LVT0, APIC_LVT_MASKED);
906 apic_write(APIC_LVT1, APIC_LVT_MASKED);
908 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
910 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
912 /* Integrated APIC (!82489DX) ? */
913 if (lapic_is_integrated()) {
915 /* Clear ESR due to Pentium errata 3AP and 11AP */
916 apic_write(APIC_ESR, 0);
922 * disable_local_APIC - clear and disable the local APIC
924 void disable_local_APIC(void)
928 /* APIC hasn't been mapped yet */
935 * Disable APIC (implies clearing of registers
938 value = apic_read(APIC_SPIV);
939 value &= ~APIC_SPIV_APIC_ENABLED;
940 apic_write(APIC_SPIV, value);
944 * When LAPIC was disabled by the BIOS and enabled by the kernel,
945 * restore the disabled state.
947 if (enabled_via_apicbase) {
950 rdmsr(MSR_IA32_APICBASE, l, h);
951 l &= ~MSR_IA32_APICBASE_ENABLE;
952 wrmsr(MSR_IA32_APICBASE, l, h);
958 * If Linux enabled the LAPIC against the BIOS default disable it down before
959 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
960 * not power-off. Additionally clear all LVT entries before disable_local_APIC
961 * for the case where Linux didn't enable the LAPIC.
963 void lapic_shutdown(void)
970 local_irq_save(flags);
973 if (!enabled_via_apicbase)
977 disable_local_APIC();
980 local_irq_restore(flags);
984 * This is to verify that we're looking at a real local APIC.
985 * Check these against your board if the CPUs aren't getting
986 * started for no apparent reason.
988 int __init verify_local_APIC(void)
990 unsigned int reg0, reg1;
993 * The version register is read-only in a real APIC.
995 reg0 = apic_read(APIC_LVR);
996 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
997 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
998 reg1 = apic_read(APIC_LVR);
999 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
1002 * The two version reads above should print the same
1003 * numbers. If the second one is different, then we
1004 * poke at a non-APIC.
1010 * Check if the version looks reasonably.
1012 reg1 = GET_APIC_VERSION(reg0);
1013 if (reg1 == 0x00 || reg1 == 0xff)
1015 reg1 = lapic_get_maxlvt();
1016 if (reg1 < 0x02 || reg1 == 0xff)
1020 * The ID register is read/write in a real APIC.
1022 reg0 = apic_read(APIC_ID);
1023 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
1024 apic_write(APIC_ID, reg0 ^ apic->apic_id_mask);
1025 reg1 = apic_read(APIC_ID);
1026 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
1027 apic_write(APIC_ID, reg0);
1028 if (reg1 != (reg0 ^ apic->apic_id_mask))
1032 * The next two are just to see if we have sane values.
1033 * They're only really relevant if we're in Virtual Wire
1034 * compatibility mode, but most boxes are anymore.
1036 reg0 = apic_read(APIC_LVT0);
1037 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
1038 reg1 = apic_read(APIC_LVT1);
1039 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
1045 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1047 void __init sync_Arb_IDs(void)
1050 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1053 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1059 apic_wait_icr_idle();
1061 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1062 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1063 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1067 * An initial setup of the virtual wire mode.
1069 void __init init_bsp_APIC(void)
1074 * Don't do the setup now if we have a SMP BIOS as the
1075 * through-I/O-APIC virtual wire mode might be active.
1077 if (smp_found_config || !cpu_has_apic)
1081 * Do not trust the local APIC being empty at bootup.
1088 value = apic_read(APIC_SPIV);
1089 value &= ~APIC_VECTOR_MASK;
1090 value |= APIC_SPIV_APIC_ENABLED;
1092 #ifdef CONFIG_X86_32
1093 /* This bit is reserved on P4/Xeon and should be cleared */
1094 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1095 (boot_cpu_data.x86 == 15))
1096 value &= ~APIC_SPIV_FOCUS_DISABLED;
1099 value |= APIC_SPIV_FOCUS_DISABLED;
1100 value |= SPURIOUS_APIC_VECTOR;
1101 apic_write(APIC_SPIV, value);
1104 * Set up the virtual wire mode.
1106 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1107 value = APIC_DM_NMI;
1108 if (!lapic_is_integrated()) /* 82489DX */
1109 value |= APIC_LVT_LEVEL_TRIGGER;
1110 apic_write(APIC_LVT1, value);
1113 static void __cpuinit lapic_setup_esr(void)
1115 unsigned int oldvalue, value, maxlvt;
1117 if (!lapic_is_integrated()) {
1118 pr_info("No ESR for 82489DX.\n");
1122 if (apic->disable_esr) {
1124 * Something untraceable is creating bad interrupts on
1125 * secondary quads ... for the moment, just leave the
1126 * ESR disabled - we can't do anything useful with the
1127 * errors anyway - mbligh
1129 pr_info("Leaving ESR disabled.\n");
1133 maxlvt = lapic_get_maxlvt();
1134 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1135 apic_write(APIC_ESR, 0);
1136 oldvalue = apic_read(APIC_ESR);
1138 /* enables sending errors */
1139 value = ERROR_APIC_VECTOR;
1140 apic_write(APIC_LVTERR, value);
1143 * spec says clear errors after enabling vector.
1146 apic_write(APIC_ESR, 0);
1147 value = apic_read(APIC_ESR);
1148 if (value != oldvalue)
1149 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1150 "vector: 0x%08x after: 0x%08x\n",
1156 * setup_local_APIC - setup the local APIC
1158 void __cpuinit setup_local_APIC(void)
1164 arch_disable_smp_support();
1168 #ifdef CONFIG_X86_32
1169 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1170 if (lapic_is_integrated() && apic->disable_esr) {
1171 apic_write(APIC_ESR, 0);
1172 apic_write(APIC_ESR, 0);
1173 apic_write(APIC_ESR, 0);
1174 apic_write(APIC_ESR, 0);
1181 * Double-check whether this APIC is really registered.
1182 * This is meaningless in clustered apic mode, so we skip it.
1184 if (!apic->apic_id_registered())
1188 * Intel recommends to set DFR, LDR and TPR before enabling
1189 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1190 * document number 292116). So here it goes...
1192 apic->init_apic_ldr();
1195 * Set Task Priority to 'accept all'. We never change this
1198 value = apic_read(APIC_TASKPRI);
1199 value &= ~APIC_TPRI_MASK;
1200 apic_write(APIC_TASKPRI, value);
1203 * After a crash, we no longer service the interrupts and a pending
1204 * interrupt from previous kernel might still have ISR bit set.
1206 * Most probably by now CPU has serviced that pending interrupt and
1207 * it might not have done the ack_APIC_irq() because it thought,
1208 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1209 * does not clear the ISR bit and cpu thinks it has already serivced
1210 * the interrupt. Hence a vector might get locked. It was noticed
1211 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1213 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1214 value = apic_read(APIC_ISR + i*0x10);
1215 for (j = 31; j >= 0; j--) {
1222 * Now that we are all set up, enable the APIC
1224 value = apic_read(APIC_SPIV);
1225 value &= ~APIC_VECTOR_MASK;
1229 value |= APIC_SPIV_APIC_ENABLED;
1231 #ifdef CONFIG_X86_32
1233 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1234 * certain networking cards. If high frequency interrupts are
1235 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1236 * entry is masked/unmasked at a high rate as well then sooner or
1237 * later IOAPIC line gets 'stuck', no more interrupts are received
1238 * from the device. If focus CPU is disabled then the hang goes
1241 * [ This bug can be reproduced easily with a level-triggered
1242 * PCI Ne2000 networking cards and PII/PIII processors, dual
1246 * Actually disabling the focus CPU check just makes the hang less
1247 * frequent as it makes the interrupt distributon model be more
1248 * like LRU than MRU (the short-term load is more even across CPUs).
1249 * See also the comment in end_level_ioapic_irq(). --macro
1253 * - enable focus processor (bit==0)
1254 * - 64bit mode always use processor focus
1255 * so no need to set it
1257 value &= ~APIC_SPIV_FOCUS_DISABLED;
1261 * Set spurious IRQ vector
1263 value |= SPURIOUS_APIC_VECTOR;
1264 apic_write(APIC_SPIV, value);
1267 * Set up LVT0, LVT1:
1269 * set up through-local-APIC on the BP's LINT0. This is not
1270 * strictly necessary in pure symmetric-IO mode, but sometimes
1271 * we delegate interrupts to the 8259A.
1274 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1276 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1277 if (!smp_processor_id() && (pic_mode || !value)) {
1278 value = APIC_DM_EXTINT;
1279 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
1280 smp_processor_id());
1282 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1283 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
1284 smp_processor_id());
1286 apic_write(APIC_LVT0, value);
1289 * only the BP should see the LINT1 NMI signal, obviously.
1291 if (!smp_processor_id())
1292 value = APIC_DM_NMI;
1294 value = APIC_DM_NMI | APIC_LVT_MASKED;
1295 if (!lapic_is_integrated()) /* 82489DX */
1296 value |= APIC_LVT_LEVEL_TRIGGER;
1297 apic_write(APIC_LVT1, value);
1301 #ifdef CONFIG_X86_MCE_INTEL
1302 /* Recheck CMCI information after local APIC is up on CPU #0 */
1303 if (smp_processor_id() == 0)
1308 void __cpuinit end_local_APIC_setup(void)
1312 #ifdef CONFIG_X86_32
1315 /* Disable the local apic timer */
1316 value = apic_read(APIC_LVTT);
1317 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1318 apic_write(APIC_LVTT, value);
1322 setup_apic_nmi_watchdog(NULL);
1326 #ifdef CONFIG_X86_X2APIC
1327 void check_x2apic(void)
1329 if (x2apic_enabled()) {
1330 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1331 x2apic_preenabled = x2apic = 1;
1335 void enable_x2apic(void)
1342 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1343 if (!(msr & X2APIC_ENABLE)) {
1344 pr_info("Enabling x2apic\n");
1345 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
1349 void __init enable_IR_x2apic(void)
1351 #ifdef CONFIG_INTR_REMAP
1353 unsigned long flags;
1354 struct IO_APIC_route_entry **ioapic_entries = NULL;
1356 if (!cpu_has_x2apic)
1359 if (!x2apic_preenabled && disable_x2apic) {
1360 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1361 "because of nox2apic\n");
1365 if (x2apic_preenabled && disable_x2apic)
1366 panic("Bios already enabled x2apic, can't enforce nox2apic");
1368 if (!x2apic_preenabled && skip_ioapic_setup) {
1369 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1370 "because of skipping io-apic setup\n");
1374 ret = dmar_table_init();
1376 pr_info("dmar_table_init() failed with %d:\n", ret);
1378 if (x2apic_preenabled)
1379 panic("x2apic enabled by bios. But IR enabling failed");
1381 pr_info("Not enabling x2apic,Intr-remapping\n");
1385 ioapic_entries = alloc_ioapic_entries();
1386 if (!ioapic_entries) {
1387 pr_info("Allocate ioapic_entries failed: %d\n", ret);
1391 ret = save_IO_APIC_setup(ioapic_entries);
1393 pr_info("Saving IO-APIC state failed: %d\n", ret);
1397 local_irq_save(flags);
1398 mask_IO_APIC_setup(ioapic_entries);
1401 ret = enable_intr_remapping(EIM_32BIT_APIC_ID);
1403 if (ret && x2apic_preenabled) {
1404 local_irq_restore(flags);
1405 panic("x2apic enabled by bios. But IR enabling failed");
1419 * IR enabling failed
1421 restore_IO_APIC_setup(ioapic_entries);
1423 reinit_intr_remapped_IO_APIC(x2apic_preenabled, ioapic_entries);
1426 local_irq_restore(flags);
1430 if (!x2apic_preenabled)
1431 pr_info("Enabled x2apic and interrupt-remapping\n");
1433 pr_info("Enabled Interrupt-remapping\n");
1435 pr_err("Failed to enable Interrupt-remapping and x2apic\n");
1437 free_ioapic_entries(ioapic_entries);
1439 if (!cpu_has_x2apic)
1442 if (x2apic_preenabled)
1443 panic("x2apic enabled prior OS handover,"
1444 " enable CONFIG_INTR_REMAP");
1446 pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1452 #endif /* CONFIG_X86_X2APIC */
1454 #ifdef CONFIG_X86_64
1456 * Detect and enable local APICs on non-SMP boards.
1457 * Original code written by Keir Fraser.
1458 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1459 * not correctly set up (usually the APIC timer won't work etc.)
1461 static int __init detect_init_APIC(void)
1463 if (!cpu_has_apic) {
1464 pr_info("No local APIC present\n");
1468 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1469 boot_cpu_physical_apicid = 0;
1474 * Detect and initialize APIC
1476 static int __init detect_init_APIC(void)
1480 /* Disabled by kernel option? */
1484 switch (boot_cpu_data.x86_vendor) {
1485 case X86_VENDOR_AMD:
1486 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1487 (boot_cpu_data.x86 >= 15))
1490 case X86_VENDOR_INTEL:
1491 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1492 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1499 if (!cpu_has_apic) {
1501 * Over-ride BIOS and try to enable the local APIC only if
1502 * "lapic" specified.
1504 if (!force_enable_local_apic) {
1505 pr_info("Local APIC disabled by BIOS -- "
1506 "you can enable it with \"lapic\"\n");
1510 * Some BIOSes disable the local APIC in the APIC_BASE
1511 * MSR. This can only be done in software for Intel P6 or later
1512 * and AMD K7 (Model > 1) or later.
1514 rdmsr(MSR_IA32_APICBASE, l, h);
1515 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1516 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1517 l &= ~MSR_IA32_APICBASE_BASE;
1518 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
1519 wrmsr(MSR_IA32_APICBASE, l, h);
1520 enabled_via_apicbase = 1;
1524 * The APIC feature bit should now be enabled
1527 features = cpuid_edx(1);
1528 if (!(features & (1 << X86_FEATURE_APIC))) {
1529 pr_warning("Could not enable APIC!\n");
1532 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1533 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1535 /* The BIOS may have set up the APIC at some other address */
1536 rdmsr(MSR_IA32_APICBASE, l, h);
1537 if (l & MSR_IA32_APICBASE_ENABLE)
1538 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1540 pr_info("Found and enabled local APIC!\n");
1547 pr_info("No local APIC present or hardware disabled\n");
1552 #ifdef CONFIG_X86_64
1553 void __init early_init_lapic_mapping(void)
1555 unsigned long phys_addr;
1558 * If no local APIC can be found then go out
1559 * : it means there is no mpatable and MADT
1561 if (!smp_found_config)
1564 phys_addr = mp_lapic_addr;
1566 set_fixmap_nocache(FIX_APIC_BASE, phys_addr);
1567 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1568 APIC_BASE, phys_addr);
1571 * Fetch the APIC ID of the BSP in case we have a
1572 * default configuration (or the MP table is broken).
1574 boot_cpu_physical_apicid = read_apic_id();
1579 * init_apic_mappings - initialize APIC mappings
1581 void __init init_apic_mappings(void)
1584 boot_cpu_physical_apicid = read_apic_id();
1589 * If no local APIC can be found then set up a fake all
1590 * zeroes page to simulate the local APIC and another
1591 * one for the IO-APIC.
1593 if (!smp_found_config && detect_init_APIC()) {
1594 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
1595 apic_phys = __pa(apic_phys);
1597 apic_phys = mp_lapic_addr;
1599 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1600 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n",
1601 APIC_BASE, apic_phys);
1604 * Fetch the APIC ID of the BSP in case we have a
1605 * default configuration (or the MP table is broken).
1607 if (boot_cpu_physical_apicid == -1U)
1608 boot_cpu_physical_apicid = read_apic_id();
1610 /* lets check if we may to NOP'ify apic operations */
1611 if (!cpu_has_apic) {
1612 pr_info("APIC: disable apic facility\n");
1618 * This initializes the IO-APIC and APIC hardware if this is
1621 int apic_version[MAX_APICS];
1623 int __init APIC_init_uniprocessor(void)
1626 pr_info("Apic disabled\n");
1629 #ifdef CONFIG_X86_64
1630 if (!cpu_has_apic) {
1632 pr_info("Apic disabled by BIOS\n");
1636 if (!smp_found_config && !cpu_has_apic)
1640 * Complain if the BIOS pretends there is one.
1642 if (!cpu_has_apic &&
1643 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1644 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1645 boot_cpu_physical_apicid);
1646 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1652 #ifdef CONFIG_X86_64
1653 default_setup_apic_routing();
1656 verify_local_APIC();
1659 #ifdef CONFIG_X86_64
1660 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1663 * Hack: In case of kdump, after a crash, kernel might be booting
1664 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1665 * might be zero if read from MP tables. Get it from LAPIC.
1667 # ifdef CONFIG_CRASH_DUMP
1668 boot_cpu_physical_apicid = read_apic_id();
1671 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1674 #ifdef CONFIG_X86_IO_APIC
1676 * Now enable IO-APICs, actually call clear_IO_APIC
1677 * We need clear_IO_APIC before enabling error vector
1679 if (!skip_ioapic_setup && nr_ioapics)
1683 end_local_APIC_setup();
1685 #ifdef CONFIG_X86_IO_APIC
1686 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1690 localise_nmi_watchdog();
1693 localise_nmi_watchdog();
1697 #ifdef CONFIG_X86_64
1698 check_nmi_watchdog();
1705 * Local APIC interrupts
1709 * This interrupt should _never_ happen with our APIC/SMP architecture
1711 void smp_spurious_interrupt(struct pt_regs *regs)
1718 * Check if this really is a spurious interrupt and ACK it
1719 * if it is a vectored one. Just in case...
1720 * Spurious interrupts should not be ACKed.
1722 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1723 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1726 inc_irq_stat(irq_spurious_count);
1728 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1729 pr_info("spurious APIC interrupt on CPU#%d, "
1730 "should never happen.\n", smp_processor_id());
1735 * This interrupt should never happen with our APIC/SMP architecture
1737 void smp_error_interrupt(struct pt_regs *regs)
1743 /* First tickle the hardware, only then report what went on. -- REW */
1744 v = apic_read(APIC_ESR);
1745 apic_write(APIC_ESR, 0);
1746 v1 = apic_read(APIC_ESR);
1748 atomic_inc(&irq_err_count);
1751 * Here is what the APIC error bits mean:
1753 * 1: Receive CS error
1754 * 2: Send accept error
1755 * 3: Receive accept error
1757 * 5: Send illegal vector
1758 * 6: Received illegal vector
1759 * 7: Illegal register address
1761 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1762 smp_processor_id(), v , v1);
1767 * connect_bsp_APIC - attach the APIC to the interrupt system
1769 void __init connect_bsp_APIC(void)
1771 #ifdef CONFIG_X86_32
1774 * Do not trust the local APIC being empty at bootup.
1778 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1779 * local APIC to INT and NMI lines.
1781 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1782 "enabling APIC mode.\n");
1786 if (apic->enable_apic_mode)
1787 apic->enable_apic_mode();
1791 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1792 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1794 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1797 void disconnect_bsp_APIC(int virt_wire_setup)
1801 #ifdef CONFIG_X86_32
1804 * Put the board back into PIC mode (has an effect only on
1805 * certain older boards). Note that APIC interrupts, including
1806 * IPIs, won't work beyond this point! The only exception are
1809 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1810 "entering PIC mode.\n");
1816 /* Go back to Virtual Wire compatibility mode */
1818 /* For the spurious interrupt use vector F, and enable it */
1819 value = apic_read(APIC_SPIV);
1820 value &= ~APIC_VECTOR_MASK;
1821 value |= APIC_SPIV_APIC_ENABLED;
1823 apic_write(APIC_SPIV, value);
1825 if (!virt_wire_setup) {
1827 * For LVT0 make it edge triggered, active high,
1828 * external and enabled
1830 value = apic_read(APIC_LVT0);
1831 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1832 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1833 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1834 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1835 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1836 apic_write(APIC_LVT0, value);
1839 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1843 * For LVT1 make it edge triggered, active high,
1846 value = apic_read(APIC_LVT1);
1847 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1848 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1849 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1850 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1851 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1852 apic_write(APIC_LVT1, value);
1855 void __cpuinit generic_processor_info(int apicid, int version)
1862 if (version == 0x0) {
1863 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1864 "fixing up to 0x10. (tell your hw vendor)\n",
1868 apic_version[apicid] = version;
1870 if (num_processors >= nr_cpu_ids) {
1871 int max = nr_cpu_ids;
1872 int thiscpu = max + disabled_cpus;
1875 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1876 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
1883 cpu = cpumask_next_zero(-1, cpu_present_mask);
1885 if (version != apic_version[boot_cpu_physical_apicid])
1887 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1888 apic_version[boot_cpu_physical_apicid], cpu, version);
1890 physid_set(apicid, phys_cpu_present_map);
1891 if (apicid == boot_cpu_physical_apicid) {
1893 * x86_bios_cpu_apicid is required to have processors listed
1894 * in same order as logical cpu numbers. Hence the first
1895 * entry is BSP, and so on.
1899 if (apicid > max_physical_apicid)
1900 max_physical_apicid = apicid;
1902 #ifdef CONFIG_X86_32
1904 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1905 * but we need to work other dependencies like SMP_SUSPEND etc
1906 * before this can be done without some confusion.
1907 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1908 * - Ashok Raj <ashok.raj@intel.com>
1910 if (max_physical_apicid >= 8) {
1911 switch (boot_cpu_data.x86_vendor) {
1912 case X86_VENDOR_INTEL:
1913 if (!APIC_XAPIC(version)) {
1917 /* If P4 and above fall through */
1918 case X86_VENDOR_AMD:
1924 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
1925 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1926 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1929 set_cpu_possible(cpu, true);
1930 set_cpu_present(cpu, true);
1933 int hard_smp_processor_id(void)
1935 return read_apic_id();
1938 void default_init_apic_ldr(void)
1942 apic_write(APIC_DFR, APIC_DFR_VALUE);
1943 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
1944 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
1945 apic_write(APIC_LDR, val);
1948 #ifdef CONFIG_X86_32
1949 int default_apicid_to_node(int logical_apicid)
1952 return apicid_2_node[hard_smp_processor_id()];
1966 * 'active' is true if the local APIC was enabled by us and
1967 * not the BIOS; this signifies that we are also responsible
1968 * for disabling it before entering apm/acpi suspend
1971 /* r/w apic fields */
1972 unsigned int apic_id;
1973 unsigned int apic_taskpri;
1974 unsigned int apic_ldr;
1975 unsigned int apic_dfr;
1976 unsigned int apic_spiv;
1977 unsigned int apic_lvtt;
1978 unsigned int apic_lvtpc;
1979 unsigned int apic_lvt0;
1980 unsigned int apic_lvt1;
1981 unsigned int apic_lvterr;
1982 unsigned int apic_tmict;
1983 unsigned int apic_tdcr;
1984 unsigned int apic_thmr;
1987 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1989 unsigned long flags;
1992 if (!apic_pm_state.active)
1995 maxlvt = lapic_get_maxlvt();
1997 apic_pm_state.apic_id = apic_read(APIC_ID);
1998 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1999 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2000 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2001 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2002 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2004 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2005 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2006 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2007 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2008 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2009 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2010 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2012 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2015 local_irq_save(flags);
2016 disable_local_APIC();
2017 #ifdef CONFIG_INTR_REMAP
2018 if (intr_remapping_enabled)
2019 disable_intr_remapping();
2021 local_irq_restore(flags);
2025 static int lapic_resume(struct sys_device *dev)
2028 unsigned long flags;
2031 #ifdef CONFIG_INTR_REMAP
2033 struct IO_APIC_route_entry **ioapic_entries = NULL;
2035 if (!apic_pm_state.active)
2038 local_irq_save(flags);
2040 ioapic_entries = alloc_ioapic_entries();
2041 if (!ioapic_entries) {
2042 WARN(1, "Alloc ioapic_entries in lapic resume failed.");
2046 ret = save_IO_APIC_setup(ioapic_entries);
2048 WARN(1, "Saving IO-APIC state failed: %d\n", ret);
2049 free_ioapic_entries(ioapic_entries);
2053 mask_IO_APIC_setup(ioapic_entries);
2058 if (!apic_pm_state.active)
2061 local_irq_save(flags);
2068 * Make sure the APICBASE points to the right address
2070 * FIXME! This will be wrong if we ever support suspend on
2071 * SMP! We'll need to do this as part of the CPU restore!
2073 rdmsr(MSR_IA32_APICBASE, l, h);
2074 l &= ~MSR_IA32_APICBASE_BASE;
2075 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2076 wrmsr(MSR_IA32_APICBASE, l, h);
2079 maxlvt = lapic_get_maxlvt();
2080 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2081 apic_write(APIC_ID, apic_pm_state.apic_id);
2082 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2083 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2084 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2085 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2086 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2087 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2088 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2090 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2093 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2094 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2095 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2096 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2097 apic_write(APIC_ESR, 0);
2098 apic_read(APIC_ESR);
2099 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2100 apic_write(APIC_ESR, 0);
2101 apic_read(APIC_ESR);
2103 #ifdef CONFIG_INTR_REMAP
2104 if (intr_remapping_enabled)
2105 reenable_intr_remapping(EIM_32BIT_APIC_ID);
2109 restore_IO_APIC_setup(ioapic_entries);
2110 free_ioapic_entries(ioapic_entries);
2114 local_irq_restore(flags);
2121 * This device has no shutdown method - fully functioning local APICs
2122 * are needed on every CPU up until machine_halt/restart/poweroff.
2125 static struct sysdev_class lapic_sysclass = {
2127 .resume = lapic_resume,
2128 .suspend = lapic_suspend,
2131 static struct sys_device device_lapic = {
2133 .cls = &lapic_sysclass,
2136 static void __cpuinit apic_pm_activate(void)
2138 apic_pm_state.active = 1;
2141 static int __init init_lapic_sysfs(void)
2147 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2149 error = sysdev_class_register(&lapic_sysclass);
2151 error = sysdev_register(&device_lapic);
2155 /* local apic needs to resume before other devices access its registers. */
2156 core_initcall(init_lapic_sysfs);
2158 #else /* CONFIG_PM */
2160 static void apic_pm_activate(void) { }
2162 #endif /* CONFIG_PM */
2164 #ifdef CONFIG_X86_64
2166 * apic_is_clustered_box() -- Check if we can expect good TSC
2168 * Thus far, the major user of this is IBM's Summit2 series:
2170 * Clustered boxes may have unsynced TSC problems if they are
2171 * multi-chassis. Use available data to take a good guess.
2172 * If in doubt, go HPET.
2174 __cpuinit int apic_is_clustered_box(void)
2176 int i, clusters, zeros;
2178 u16 *bios_cpu_apicid;
2179 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
2182 * there is not this kind of box with AMD CPU yet.
2183 * Some AMD box with quadcore cpu and 8 sockets apicid
2184 * will be [4, 0x23] or [8, 0x27] could be thought to
2185 * vsmp box still need checking...
2187 if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
2190 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
2191 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
2193 for (i = 0; i < nr_cpu_ids; i++) {
2194 /* are we being called early in kernel startup? */
2195 if (bios_cpu_apicid) {
2196 id = bios_cpu_apicid[i];
2197 } else if (i < nr_cpu_ids) {
2199 id = per_cpu(x86_bios_cpu_apicid, i);
2205 if (id != BAD_APICID)
2206 __set_bit(APIC_CLUSTERID(id), clustermap);
2209 /* Problem: Partially populated chassis may not have CPUs in some of
2210 * the APIC clusters they have been allocated. Only present CPUs have
2211 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2212 * Since clusters are allocated sequentially, count zeros only if
2213 * they are bounded by ones.
2217 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
2218 if (test_bit(i, clustermap)) {
2219 clusters += 1 + zeros;
2225 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2226 * not guaranteed to be synced between boards
2228 if (is_vsmp_box() && clusters > 1)
2232 * If clusters > 2, then should be multi-chassis.
2233 * May have to revisit this when multi-core + hyperthreaded CPUs come
2234 * out, but AFAIK this will work even for them.
2236 return (clusters > 2);
2241 * APIC command line parameters
2243 static int __init setup_disableapic(char *arg)
2246 setup_clear_cpu_cap(X86_FEATURE_APIC);
2249 early_param("disableapic", setup_disableapic);
2251 /* same as disableapic, for compatibility */
2252 static int __init setup_nolapic(char *arg)
2254 return setup_disableapic(arg);
2256 early_param("nolapic", setup_nolapic);
2258 static int __init parse_lapic_timer_c2_ok(char *arg)
2260 local_apic_timer_c2_ok = 1;
2263 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2265 static int __init parse_disable_apic_timer(char *arg)
2267 disable_apic_timer = 1;
2270 early_param("noapictimer", parse_disable_apic_timer);
2272 static int __init parse_nolapic_timer(char *arg)
2274 disable_apic_timer = 1;
2277 early_param("nolapic_timer", parse_nolapic_timer);
2279 static int __init apic_set_verbosity(char *arg)
2282 #ifdef CONFIG_X86_64
2283 skip_ioapic_setup = 0;
2289 if (strcmp("debug", arg) == 0)
2290 apic_verbosity = APIC_DEBUG;
2291 else if (strcmp("verbose", arg) == 0)
2292 apic_verbosity = APIC_VERBOSE;
2294 pr_warning("APIC Verbosity level %s not recognised"
2295 " use apic=verbose or apic=debug\n", arg);
2301 early_param("apic", apic_set_verbosity);
2303 static int __init lapic_insert_resource(void)
2308 /* Put local APIC into the resource map. */
2309 lapic_resource.start = apic_phys;
2310 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2311 insert_resource(&iomem_resource, &lapic_resource);
2317 * need call insert after e820_reserve_resources()
2318 * that is using request_resource
2320 late_initcall(lapic_insert_resource);