2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/perf_counter.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/module.h>
27 #include <linux/sysdev.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/dmar.h>
31 #include <linux/init.h>
32 #include <linux/cpu.h>
33 #include <linux/dmi.h>
34 #include <linux/nmi.h>
35 #include <linux/smp.h>
38 #include <asm/perf_counter.h>
39 #include <asm/pgalloc.h>
40 #include <asm/atomic.h>
41 #include <asm/mpspec.h>
42 #include <asm/i8253.h>
43 #include <asm/i8259.h>
44 #include <asm/proto.h>
52 #include <asm/kvm_para.h>
54 unsigned int num_processors;
56 unsigned disabled_cpus __cpuinitdata;
58 /* Processor that is doing the boot up */
59 unsigned int boot_cpu_physical_apicid = -1U;
62 * The highest APIC ID seen during enumeration.
64 * On AMD, this determines the messaging protocol we can use: if all APIC IDs
65 * are in the 0 ... 7 range, then we can use logical addressing which
66 * has some performance advantages (better broadcasting).
68 * If there's an APIC ID above 8, we use physical addressing.
70 unsigned int max_physical_apicid;
73 * Bitmask of physically existing CPUs:
75 physid_mask_t phys_cpu_present_map;
78 * Map cpu index to physical APIC ID
80 DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID);
81 DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID);
82 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
83 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
87 * Knob to control our willingness to enable the local APIC.
91 static int force_enable_local_apic;
93 * APIC command line parameters
95 static int __init parse_lapic(char *arg)
97 force_enable_local_apic = 1;
100 early_param("lapic", parse_lapic);
101 /* Local APIC was disabled by the BIOS and enabled by the kernel */
102 static int enabled_via_apicbase;
105 * Handle interrupt mode configuration register (IMCR).
106 * This register controls whether the interrupt signals
107 * that reach the BSP come from the master PIC or from the
108 * local APIC. Before entering Symmetric I/O Mode, either
109 * the BIOS or the operating system must switch out of
110 * PIC Mode by changing the IMCR.
112 static inline void imcr_pic_to_apic(void)
114 /* select IMCR register */
116 /* NMI and 8259 INTR go through APIC */
120 static inline void imcr_apic_to_pic(void)
122 /* select IMCR register */
124 /* NMI and 8259 INTR go directly to BSP */
130 static int apic_calibrate_pmtmr __initdata;
131 static __init int setup_apicpmtimer(char *s)
133 apic_calibrate_pmtmr = 1;
137 __setup("apicpmtimer", setup_apicpmtimer);
141 #ifdef CONFIG_X86_X2APIC
142 /* x2apic enabled before OS handover */
143 static int x2apic_preenabled;
144 static __init int setup_nox2apic(char *str)
146 if (x2apic_enabled()) {
147 pr_warning("Bios already enabled x2apic, "
148 "can't enforce nox2apic");
152 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
155 early_param("nox2apic", setup_nox2apic);
158 unsigned long mp_lapic_addr;
160 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
161 static int disable_apic_timer __cpuinitdata;
162 /* Local APIC timer works in C2 */
163 int local_apic_timer_c2_ok;
164 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
166 int first_system_vector = 0xfe;
169 * Debug level, exported for io_apic.c
171 unsigned int apic_verbosity;
175 /* Have we found an MP table */
176 int smp_found_config;
178 static struct resource lapic_resource = {
179 .name = "Local APIC",
180 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
183 static unsigned int calibration_result;
185 static int lapic_next_event(unsigned long delta,
186 struct clock_event_device *evt);
187 static void lapic_timer_setup(enum clock_event_mode mode,
188 struct clock_event_device *evt);
189 static void lapic_timer_broadcast(const struct cpumask *mask);
190 static void apic_pm_activate(void);
193 * The local apic timer can be used for any function which is CPU local.
195 static struct clock_event_device lapic_clockevent = {
197 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
198 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
200 .set_mode = lapic_timer_setup,
201 .set_next_event = lapic_next_event,
202 .broadcast = lapic_timer_broadcast,
206 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
208 static unsigned long apic_phys;
211 * Get the LAPIC version
213 static inline int lapic_get_version(void)
215 return GET_APIC_VERSION(apic_read(APIC_LVR));
219 * Check, if the APIC is integrated or a separate chip
221 static inline int lapic_is_integrated(void)
226 return APIC_INTEGRATED(lapic_get_version());
231 * Check, whether this is a modern or a first generation APIC
233 static int modern_apic(void)
235 /* AMD systems use old APIC versions, so check the CPU */
236 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
237 boot_cpu_data.x86 >= 0xf)
239 return lapic_get_version() >= 0x14;
243 * bare function to substitute write operation
244 * and it's _that_ fast :)
246 static void native_apic_write_dummy(u32 reg, u32 v)
248 WARN_ON_ONCE((cpu_has_apic || !disable_apic));
251 static u32 native_apic_read_dummy(u32 reg)
253 WARN_ON_ONCE((cpu_has_apic && !disable_apic));
258 * right after this call apic->write/read doesn't do anything
259 * note that there is no restore operation it works one way
261 void apic_disable(void)
263 apic->read = native_apic_read_dummy;
264 apic->write = native_apic_write_dummy;
267 void native_apic_wait_icr_idle(void)
269 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
273 u32 native_safe_apic_wait_icr_idle(void)
280 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
284 } while (timeout++ < 1000);
289 void native_apic_icr_write(u32 low, u32 id)
291 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
292 apic_write(APIC_ICR, low);
295 u64 native_apic_icr_read(void)
299 icr2 = apic_read(APIC_ICR2);
300 icr1 = apic_read(APIC_ICR);
302 return icr1 | ((u64)icr2 << 32);
306 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
308 void __cpuinit enable_NMI_through_LVT0(void)
312 /* unmask and set to NMI */
315 /* Level triggered for 82489DX (32bit mode) */
316 if (!lapic_is_integrated())
317 v |= APIC_LVT_LEVEL_TRIGGER;
319 apic_write(APIC_LVT0, v);
324 * get_physical_broadcast - Get number of physical broadcast IDs
326 int get_physical_broadcast(void)
328 return modern_apic() ? 0xff : 0xf;
333 * lapic_get_maxlvt - get the maximum number of local vector table entries
335 int lapic_get_maxlvt(void)
339 v = apic_read(APIC_LVR);
341 * - we always have APIC integrated on 64bit mode
342 * - 82489DXs do not report # of LVT entries
344 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
352 #define APIC_DIVISOR 16
355 * This function sets up the local APIC timer, with a timeout of
356 * 'clocks' APIC bus clock. During calibration we actually call
357 * this function twice on the boot CPU, once with a bogus timeout
358 * value, second time for real. The other (noncalibrating) CPUs
359 * call this function only once, with the real, calibrated value.
361 * We do reads before writes even if unnecessary, to get around the
362 * P5 APIC double write bug.
364 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
366 unsigned int lvtt_value, tmp_value;
368 lvtt_value = LOCAL_TIMER_VECTOR;
370 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
371 if (!lapic_is_integrated())
372 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
375 lvtt_value |= APIC_LVT_MASKED;
377 apic_write(APIC_LVTT, lvtt_value);
382 tmp_value = apic_read(APIC_TDCR);
383 apic_write(APIC_TDCR,
384 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
388 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
392 * Setup extended LVT, AMD specific (K8, family 10h)
394 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
395 * MCE interrupts are supported. Thus MCE offset must be set to 0.
397 * If mask=1, the LVT entry does not generate interrupts while mask=0
398 * enables the vector. See also the BKDGs.
401 #define APIC_EILVT_LVTOFF_MCE 0
402 #define APIC_EILVT_LVTOFF_IBS 1
404 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
406 unsigned long reg = (lvt_off << 4) + APIC_EILVTn(0);
407 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
412 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
414 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
415 return APIC_EILVT_LVTOFF_MCE;
418 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
420 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
421 return APIC_EILVT_LVTOFF_IBS;
423 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs);
426 * Program the next event, relative to now
428 static int lapic_next_event(unsigned long delta,
429 struct clock_event_device *evt)
431 apic_write(APIC_TMICT, delta);
436 * Setup the lapic timer in periodic or oneshot mode
438 static void lapic_timer_setup(enum clock_event_mode mode,
439 struct clock_event_device *evt)
444 /* Lapic used as dummy for broadcast ? */
445 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
448 local_irq_save(flags);
451 case CLOCK_EVT_MODE_PERIODIC:
452 case CLOCK_EVT_MODE_ONESHOT:
453 __setup_APIC_LVTT(calibration_result,
454 mode != CLOCK_EVT_MODE_PERIODIC, 1);
456 case CLOCK_EVT_MODE_UNUSED:
457 case CLOCK_EVT_MODE_SHUTDOWN:
458 v = apic_read(APIC_LVTT);
459 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
460 apic_write(APIC_LVTT, v);
461 apic_write(APIC_TMICT, 0xffffffff);
463 case CLOCK_EVT_MODE_RESUME:
464 /* Nothing to do here */
468 local_irq_restore(flags);
472 * Local APIC timer broadcast function
474 static void lapic_timer_broadcast(const struct cpumask *mask)
477 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
482 * Setup the local APIC timer for this CPU. Copy the initilized values
483 * of the boot CPU and register the clock event in the framework.
485 static void __cpuinit setup_APIC_timer(void)
487 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
489 if (cpu_has(¤t_cpu_data, X86_FEATURE_ARAT)) {
490 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
491 /* Make LAPIC timer preferrable over percpu HPET */
492 lapic_clockevent.rating = 150;
495 memcpy(levt, &lapic_clockevent, sizeof(*levt));
496 levt->cpumask = cpumask_of(smp_processor_id());
498 clockevents_register_device(levt);
502 * In this functions we calibrate APIC bus clocks to the external timer.
504 * We want to do the calibration only once since we want to have local timer
505 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
508 * This was previously done by reading the PIT/HPET and waiting for a wrap
509 * around to find out, that a tick has elapsed. I have a box, where the PIT
510 * readout is broken, so it never gets out of the wait loop again. This was
511 * also reported by others.
513 * Monitoring the jiffies value is inaccurate and the clockevents
514 * infrastructure allows us to do a simple substitution of the interrupt
517 * The calibration routine also uses the pm_timer when possible, as the PIT
518 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
519 * back to normal later in the boot process).
522 #define LAPIC_CAL_LOOPS (HZ/10)
524 static __initdata int lapic_cal_loops = -1;
525 static __initdata long lapic_cal_t1, lapic_cal_t2;
526 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
527 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
528 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
531 * Temporary interrupt handler.
533 static void __init lapic_cal_handler(struct clock_event_device *dev)
535 unsigned long long tsc = 0;
536 long tapic = apic_read(APIC_TMCCT);
537 unsigned long pm = acpi_pm_read_early();
542 switch (lapic_cal_loops++) {
544 lapic_cal_t1 = tapic;
545 lapic_cal_tsc1 = tsc;
547 lapic_cal_j1 = jiffies;
550 case LAPIC_CAL_LOOPS:
551 lapic_cal_t2 = tapic;
552 lapic_cal_tsc2 = tsc;
553 if (pm < lapic_cal_pm1)
554 pm += ACPI_PM_OVRRUN;
556 lapic_cal_j2 = jiffies;
562 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
564 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
565 const long pm_thresh = pm_100ms / 100;
569 #ifndef CONFIG_X86_PM_TIMER
573 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
575 /* Check, if the PM timer is available */
579 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
581 if (deltapm > (pm_100ms - pm_thresh) &&
582 deltapm < (pm_100ms + pm_thresh)) {
583 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
587 res = (((u64)deltapm) * mult) >> 22;
588 do_div(res, 1000000);
589 pr_warning("APIC calibration not consistent "
590 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
592 /* Correct the lapic counter value */
593 res = (((u64)(*delta)) * pm_100ms);
594 do_div(res, deltapm);
595 pr_info("APIC delta adjusted to PM-Timer: "
596 "%lu (%ld)\n", (unsigned long)res, *delta);
599 /* Correct the tsc counter value */
601 res = (((u64)(*deltatsc)) * pm_100ms);
602 do_div(res, deltapm);
603 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
604 "PM-Timer: %lu (%ld) \n",
605 (unsigned long)res, *deltatsc);
606 *deltatsc = (long)res;
612 static int __init calibrate_APIC_clock(void)
614 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
615 void (*real_handler)(struct clock_event_device *dev);
616 unsigned long deltaj;
617 long delta, deltatsc;
618 int pm_referenced = 0;
622 /* Replace the global interrupt handler */
623 real_handler = global_clock_event->event_handler;
624 global_clock_event->event_handler = lapic_cal_handler;
627 * Setup the APIC counter to maximum. There is no way the lapic
628 * can underflow in the 100ms detection time frame
630 __setup_APIC_LVTT(0xffffffff, 0, 0);
632 /* Let the interrupts run */
635 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
640 /* Restore the real event handler */
641 global_clock_event->event_handler = real_handler;
643 /* Build delta t1-t2 as apic timer counts down */
644 delta = lapic_cal_t1 - lapic_cal_t2;
645 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
647 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
649 /* we trust the PM based calibration if possible */
650 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
653 /* Calculate the scaled math multiplication factor */
654 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
655 lapic_clockevent.shift);
656 lapic_clockevent.max_delta_ns =
657 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
658 lapic_clockevent.min_delta_ns =
659 clockevent_delta2ns(0xF, &lapic_clockevent);
661 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
663 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
664 apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult);
665 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
669 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
671 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
672 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
675 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
677 calibration_result / (1000000 / HZ),
678 calibration_result % (1000000 / HZ));
681 * Do a sanity check on the APIC calibration result
683 if (calibration_result < (1000000 / HZ)) {
685 pr_warning("APIC frequency too slow, disabling apic timer\n");
689 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
692 * PM timer calibration failed or not turned on
693 * so lets try APIC timer based calibration
695 if (!pm_referenced) {
696 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
699 * Setup the apic timer manually
701 levt->event_handler = lapic_cal_handler;
702 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
703 lapic_cal_loops = -1;
705 /* Let the interrupts run */
708 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
711 /* Stop the lapic timer */
712 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
715 deltaj = lapic_cal_j2 - lapic_cal_j1;
716 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
718 /* Check, if the jiffies result is consistent */
719 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
720 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
722 levt->features |= CLOCK_EVT_FEAT_DUMMY;
726 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
727 pr_warning("APIC timer disabled due to verification failure\n");
735 * Setup the boot APIC
737 * Calibrate and verify the result.
739 void __init setup_boot_APIC_clock(void)
742 * The local apic timer can be disabled via the kernel
743 * commandline or from the CPU detection code. Register the lapic
744 * timer as a dummy clock event source on SMP systems, so the
745 * broadcast mechanism is used. On UP systems simply ignore it.
747 if (disable_apic_timer) {
748 pr_info("Disabling APIC timer\n");
749 /* No broadcast on UP ! */
750 if (num_possible_cpus() > 1) {
751 lapic_clockevent.mult = 1;
757 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
758 "calibrating APIC timer ...\n");
760 if (calibrate_APIC_clock()) {
761 /* No broadcast on UP ! */
762 if (num_possible_cpus() > 1)
768 * If nmi_watchdog is set to IO_APIC, we need the
769 * PIT/HPET going. Otherwise register lapic as a dummy
772 if (nmi_watchdog != NMI_IO_APIC)
773 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
775 pr_warning("APIC timer registered as dummy,"
776 " due to nmi_watchdog=%d!\n", nmi_watchdog);
778 /* Setup the lapic or request the broadcast */
782 void __cpuinit setup_secondary_APIC_clock(void)
788 * The guts of the apic timer interrupt
790 static void local_apic_timer_interrupt(void)
792 int cpu = smp_processor_id();
793 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
796 * Normally we should not be here till LAPIC has been initialized but
797 * in some cases like kdump, its possible that there is a pending LAPIC
798 * timer interrupt from previous kernel's context and is delivered in
799 * new kernel the moment interrupts are enabled.
801 * Interrupts are enabled early and LAPIC is setup much later, hence
802 * its possible that when we get here evt->event_handler is NULL.
803 * Check for event_handler being NULL and discard the interrupt as
806 if (!evt->event_handler) {
807 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
809 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
814 * the NMI deadlock-detector uses this.
816 inc_irq_stat(apic_timer_irqs);
818 evt->event_handler(evt);
822 * Local APIC timer interrupt. This is the most natural way for doing
823 * local interrupts, but local timer interrupts can be emulated by
824 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
826 * [ if a single-CPU system runs an SMP kernel then we call the local
827 * interrupt as well. Thus we cannot inline the local irq ... ]
829 void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
831 struct pt_regs *old_regs = set_irq_regs(regs);
834 * NOTE! We'd better ACK the irq immediately,
835 * because timer handling can be slow.
839 * update_process_times() expects us to have done irq_enter().
840 * Besides, if we don't timer interrupts ignore the global
841 * interrupt lock, which is the WrongThing (tm) to do.
845 local_apic_timer_interrupt();
848 set_irq_regs(old_regs);
851 int setup_profiling_timer(unsigned int multiplier)
857 * Local APIC start and shutdown
861 * clear_local_APIC - shutdown the local APIC
863 * This is called, when a CPU is disabled and before rebooting, so the state of
864 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
865 * leftovers during boot.
867 void clear_local_APIC(void)
872 /* APIC hasn't been mapped yet */
873 if (!x2apic_mode && !apic_phys)
876 maxlvt = lapic_get_maxlvt();
878 * Masking an LVT entry can trigger a local APIC error
879 * if the vector is zero. Mask LVTERR first to prevent this.
882 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
883 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
886 * Careful: we have to set masks only first to deassert
887 * any level-triggered sources.
889 v = apic_read(APIC_LVTT);
890 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
891 v = apic_read(APIC_LVT0);
892 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
893 v = apic_read(APIC_LVT1);
894 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
896 v = apic_read(APIC_LVTPC);
897 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
900 /* lets not touch this if we didn't frob it */
901 #ifdef CONFIG_X86_THERMAL_VECTOR
903 v = apic_read(APIC_LVTTHMR);
904 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
907 #ifdef CONFIG_X86_MCE_INTEL
909 v = apic_read(APIC_LVTCMCI);
910 if (!(v & APIC_LVT_MASKED))
911 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
916 * Clean APIC state for other OSs:
918 apic_write(APIC_LVTT, APIC_LVT_MASKED);
919 apic_write(APIC_LVT0, APIC_LVT_MASKED);
920 apic_write(APIC_LVT1, APIC_LVT_MASKED);
922 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
924 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
926 /* Integrated APIC (!82489DX) ? */
927 if (lapic_is_integrated()) {
929 /* Clear ESR due to Pentium errata 3AP and 11AP */
930 apic_write(APIC_ESR, 0);
936 * disable_local_APIC - clear and disable the local APIC
938 void disable_local_APIC(void)
942 /* APIC hasn't been mapped yet */
949 * Disable APIC (implies clearing of registers
952 value = apic_read(APIC_SPIV);
953 value &= ~APIC_SPIV_APIC_ENABLED;
954 apic_write(APIC_SPIV, value);
958 * When LAPIC was disabled by the BIOS and enabled by the kernel,
959 * restore the disabled state.
961 if (enabled_via_apicbase) {
964 rdmsr(MSR_IA32_APICBASE, l, h);
965 l &= ~MSR_IA32_APICBASE_ENABLE;
966 wrmsr(MSR_IA32_APICBASE, l, h);
972 * If Linux enabled the LAPIC against the BIOS default disable it down before
973 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
974 * not power-off. Additionally clear all LVT entries before disable_local_APIC
975 * for the case where Linux didn't enable the LAPIC.
977 void lapic_shutdown(void)
984 local_irq_save(flags);
987 if (!enabled_via_apicbase)
991 disable_local_APIC();
994 local_irq_restore(flags);
998 * This is to verify that we're looking at a real local APIC.
999 * Check these against your board if the CPUs aren't getting
1000 * started for no apparent reason.
1002 int __init verify_local_APIC(void)
1004 unsigned int reg0, reg1;
1007 * The version register is read-only in a real APIC.
1009 reg0 = apic_read(APIC_LVR);
1010 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
1011 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
1012 reg1 = apic_read(APIC_LVR);
1013 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
1016 * The two version reads above should print the same
1017 * numbers. If the second one is different, then we
1018 * poke at a non-APIC.
1024 * Check if the version looks reasonably.
1026 reg1 = GET_APIC_VERSION(reg0);
1027 if (reg1 == 0x00 || reg1 == 0xff)
1029 reg1 = lapic_get_maxlvt();
1030 if (reg1 < 0x02 || reg1 == 0xff)
1034 * The ID register is read/write in a real APIC.
1036 reg0 = apic_read(APIC_ID);
1037 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
1038 apic_write(APIC_ID, reg0 ^ apic->apic_id_mask);
1039 reg1 = apic_read(APIC_ID);
1040 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
1041 apic_write(APIC_ID, reg0);
1042 if (reg1 != (reg0 ^ apic->apic_id_mask))
1046 * The next two are just to see if we have sane values.
1047 * They're only really relevant if we're in Virtual Wire
1048 * compatibility mode, but most boxes are anymore.
1050 reg0 = apic_read(APIC_LVT0);
1051 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
1052 reg1 = apic_read(APIC_LVT1);
1053 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
1059 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1061 void __init sync_Arb_IDs(void)
1064 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1067 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1073 apic_wait_icr_idle();
1075 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1076 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1077 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1081 * An initial setup of the virtual wire mode.
1083 void __init init_bsp_APIC(void)
1088 * Don't do the setup now if we have a SMP BIOS as the
1089 * through-I/O-APIC virtual wire mode might be active.
1091 if (smp_found_config || !cpu_has_apic)
1095 * Do not trust the local APIC being empty at bootup.
1102 value = apic_read(APIC_SPIV);
1103 value &= ~APIC_VECTOR_MASK;
1104 value |= APIC_SPIV_APIC_ENABLED;
1106 #ifdef CONFIG_X86_32
1107 /* This bit is reserved on P4/Xeon and should be cleared */
1108 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1109 (boot_cpu_data.x86 == 15))
1110 value &= ~APIC_SPIV_FOCUS_DISABLED;
1113 value |= APIC_SPIV_FOCUS_DISABLED;
1114 value |= SPURIOUS_APIC_VECTOR;
1115 apic_write(APIC_SPIV, value);
1118 * Set up the virtual wire mode.
1120 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1121 value = APIC_DM_NMI;
1122 if (!lapic_is_integrated()) /* 82489DX */
1123 value |= APIC_LVT_LEVEL_TRIGGER;
1124 apic_write(APIC_LVT1, value);
1127 static void __cpuinit lapic_setup_esr(void)
1129 unsigned int oldvalue, value, maxlvt;
1131 if (!lapic_is_integrated()) {
1132 pr_info("No ESR for 82489DX.\n");
1136 if (apic->disable_esr) {
1138 * Something untraceable is creating bad interrupts on
1139 * secondary quads ... for the moment, just leave the
1140 * ESR disabled - we can't do anything useful with the
1141 * errors anyway - mbligh
1143 pr_info("Leaving ESR disabled.\n");
1147 maxlvt = lapic_get_maxlvt();
1148 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1149 apic_write(APIC_ESR, 0);
1150 oldvalue = apic_read(APIC_ESR);
1152 /* enables sending errors */
1153 value = ERROR_APIC_VECTOR;
1154 apic_write(APIC_LVTERR, value);
1157 * spec says clear errors after enabling vector.
1160 apic_write(APIC_ESR, 0);
1161 value = apic_read(APIC_ESR);
1162 if (value != oldvalue)
1163 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1164 "vector: 0x%08x after: 0x%08x\n",
1170 * setup_local_APIC - setup the local APIC
1172 void __cpuinit setup_local_APIC(void)
1178 arch_disable_smp_support();
1182 #ifdef CONFIG_X86_32
1183 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1184 if (lapic_is_integrated() && apic->disable_esr) {
1185 apic_write(APIC_ESR, 0);
1186 apic_write(APIC_ESR, 0);
1187 apic_write(APIC_ESR, 0);
1188 apic_write(APIC_ESR, 0);
1191 perf_counters_lapic_init();
1196 * Double-check whether this APIC is really registered.
1197 * This is meaningless in clustered apic mode, so we skip it.
1199 BUG_ON(!apic->apic_id_registered());
1202 * Intel recommends to set DFR, LDR and TPR before enabling
1203 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1204 * document number 292116). So here it goes...
1206 apic->init_apic_ldr();
1209 * Set Task Priority to 'accept all'. We never change this
1212 value = apic_read(APIC_TASKPRI);
1213 value &= ~APIC_TPRI_MASK;
1214 apic_write(APIC_TASKPRI, value);
1217 * After a crash, we no longer service the interrupts and a pending
1218 * interrupt from previous kernel might still have ISR bit set.
1220 * Most probably by now CPU has serviced that pending interrupt and
1221 * it might not have done the ack_APIC_irq() because it thought,
1222 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1223 * does not clear the ISR bit and cpu thinks it has already serivced
1224 * the interrupt. Hence a vector might get locked. It was noticed
1225 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1227 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1228 value = apic_read(APIC_ISR + i*0x10);
1229 for (j = 31; j >= 0; j--) {
1236 * Now that we are all set up, enable the APIC
1238 value = apic_read(APIC_SPIV);
1239 value &= ~APIC_VECTOR_MASK;
1243 value |= APIC_SPIV_APIC_ENABLED;
1245 #ifdef CONFIG_X86_32
1247 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1248 * certain networking cards. If high frequency interrupts are
1249 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1250 * entry is masked/unmasked at a high rate as well then sooner or
1251 * later IOAPIC line gets 'stuck', no more interrupts are received
1252 * from the device. If focus CPU is disabled then the hang goes
1255 * [ This bug can be reproduced easily with a level-triggered
1256 * PCI Ne2000 networking cards and PII/PIII processors, dual
1260 * Actually disabling the focus CPU check just makes the hang less
1261 * frequent as it makes the interrupt distributon model be more
1262 * like LRU than MRU (the short-term load is more even across CPUs).
1263 * See also the comment in end_level_ioapic_irq(). --macro
1267 * - enable focus processor (bit==0)
1268 * - 64bit mode always use processor focus
1269 * so no need to set it
1271 value &= ~APIC_SPIV_FOCUS_DISABLED;
1275 * Set spurious IRQ vector
1277 value |= SPURIOUS_APIC_VECTOR;
1278 apic_write(APIC_SPIV, value);
1281 * Set up LVT0, LVT1:
1283 * set up through-local-APIC on the BP's LINT0. This is not
1284 * strictly necessary in pure symmetric-IO mode, but sometimes
1285 * we delegate interrupts to the 8259A.
1288 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1290 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1291 if (!smp_processor_id() && (pic_mode || !value)) {
1292 value = APIC_DM_EXTINT;
1293 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
1294 smp_processor_id());
1296 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1297 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
1298 smp_processor_id());
1300 apic_write(APIC_LVT0, value);
1303 * only the BP should see the LINT1 NMI signal, obviously.
1305 if (!smp_processor_id())
1306 value = APIC_DM_NMI;
1308 value = APIC_DM_NMI | APIC_LVT_MASKED;
1309 if (!lapic_is_integrated()) /* 82489DX */
1310 value |= APIC_LVT_LEVEL_TRIGGER;
1311 apic_write(APIC_LVT1, value);
1315 #ifdef CONFIG_X86_MCE_INTEL
1316 /* Recheck CMCI information after local APIC is up on CPU #0 */
1317 if (smp_processor_id() == 0)
1322 void __cpuinit end_local_APIC_setup(void)
1326 #ifdef CONFIG_X86_32
1329 /* Disable the local apic timer */
1330 value = apic_read(APIC_LVTT);
1331 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1332 apic_write(APIC_LVTT, value);
1336 setup_apic_nmi_watchdog(NULL);
1340 #ifdef CONFIG_X86_X2APIC
1341 void check_x2apic(void)
1343 if (x2apic_enabled()) {
1344 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1345 x2apic_preenabled = x2apic_mode = 1;
1349 void enable_x2apic(void)
1356 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1357 if (!(msr & X2APIC_ENABLE)) {
1358 pr_info("Enabling x2apic\n");
1359 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
1362 #endif /* CONFIG_X86_X2APIC */
1364 int __init enable_IR(void)
1366 #ifdef CONFIG_INTR_REMAP
1367 if (!intr_remapping_supported()) {
1368 pr_debug("intr-remapping not supported\n");
1372 if (!x2apic_preenabled && skip_ioapic_setup) {
1373 pr_info("Skipped enabling intr-remap because of skipping "
1378 if (enable_intr_remapping(x2apic_supported()))
1381 pr_info("Enabled Interrupt-remapping\n");
1389 void __init enable_IR_x2apic(void)
1391 unsigned long flags;
1392 struct IO_APIC_route_entry **ioapic_entries = NULL;
1393 int ret, x2apic_enabled = 0;
1394 int dmar_table_init_ret = 0;
1396 #ifdef CONFIG_INTR_REMAP
1397 dmar_table_init_ret = dmar_table_init();
1398 if (dmar_table_init_ret)
1399 pr_debug("dmar_table_init() failed with %d:\n",
1400 dmar_table_init_ret);
1403 ioapic_entries = alloc_ioapic_entries();
1404 if (!ioapic_entries) {
1405 pr_err("Allocate ioapic_entries failed\n");
1409 ret = save_IO_APIC_setup(ioapic_entries);
1411 pr_info("Saving IO-APIC state failed: %d\n", ret);
1415 local_irq_save(flags);
1417 mask_IO_APIC_setup(ioapic_entries);
1419 if (dmar_table_init_ret)
1425 /* IR is required if there is APIC ID > 255 even when running
1428 if (max_physical_apicid > 255 || !kvm_para_available())
1431 * without IR all CPUs can be addressed by IOAPIC/MSI
1432 * only in physical mode
1434 x2apic_force_phys();
1439 if (x2apic_supported() && !x2apic_mode) {
1442 pr_info("Enabled x2apic\n");
1446 if (!ret) /* IR enabling failed */
1447 restore_IO_APIC_setup(ioapic_entries);
1449 local_irq_restore(flags);
1453 free_ioapic_entries(ioapic_entries);
1458 if (x2apic_preenabled)
1459 panic("x2apic: enabled by BIOS but kernel init failed.");
1460 else if (cpu_has_x2apic)
1461 pr_info("Not enabling x2apic, Intr-remapping init failed.\n");
1464 #ifdef CONFIG_X86_64
1466 * Detect and enable local APICs on non-SMP boards.
1467 * Original code written by Keir Fraser.
1468 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1469 * not correctly set up (usually the APIC timer won't work etc.)
1471 static int __init detect_init_APIC(void)
1473 if (!cpu_has_apic) {
1474 pr_info("No local APIC present\n");
1478 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1483 * Detect and initialize APIC
1485 static int __init detect_init_APIC(void)
1489 /* Disabled by kernel option? */
1493 switch (boot_cpu_data.x86_vendor) {
1494 case X86_VENDOR_AMD:
1495 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1496 (boot_cpu_data.x86 >= 15))
1499 case X86_VENDOR_INTEL:
1500 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1501 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1508 if (!cpu_has_apic) {
1510 * Over-ride BIOS and try to enable the local APIC only if
1511 * "lapic" specified.
1513 if (!force_enable_local_apic) {
1514 pr_info("Local APIC disabled by BIOS -- "
1515 "you can enable it with \"lapic\"\n");
1519 * Some BIOSes disable the local APIC in the APIC_BASE
1520 * MSR. This can only be done in software for Intel P6 or later
1521 * and AMD K7 (Model > 1) or later.
1523 rdmsr(MSR_IA32_APICBASE, l, h);
1524 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1525 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1526 l &= ~MSR_IA32_APICBASE_BASE;
1527 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
1528 wrmsr(MSR_IA32_APICBASE, l, h);
1529 enabled_via_apicbase = 1;
1533 * The APIC feature bit should now be enabled
1536 features = cpuid_edx(1);
1537 if (!(features & (1 << X86_FEATURE_APIC))) {
1538 pr_warning("Could not enable APIC!\n");
1541 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1542 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1544 /* The BIOS may have set up the APIC at some other address */
1545 rdmsr(MSR_IA32_APICBASE, l, h);
1546 if (l & MSR_IA32_APICBASE_ENABLE)
1547 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1549 pr_info("Found and enabled local APIC!\n");
1556 pr_info("No local APIC present or hardware disabled\n");
1561 #ifdef CONFIG_X86_64
1562 void __init early_init_lapic_mapping(void)
1565 * If no local APIC can be found then go out
1566 * : it means there is no mpatable and MADT
1568 if (!smp_found_config)
1571 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
1572 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1573 APIC_BASE, mp_lapic_addr);
1576 * Fetch the APIC ID of the BSP in case we have a
1577 * default configuration (or the MP table is broken).
1579 boot_cpu_physical_apicid = read_apic_id();
1584 * init_apic_mappings - initialize APIC mappings
1586 void __init init_apic_mappings(void)
1588 unsigned int new_apicid;
1591 boot_cpu_physical_apicid = read_apic_id();
1595 /* If no local APIC can be found return early */
1596 if (!smp_found_config && detect_init_APIC()) {
1597 /* lets NOP'ify apic operations */
1598 pr_info("APIC: disable apic facility\n");
1601 apic_phys = mp_lapic_addr;
1604 * acpi lapic path already maps that address in
1605 * acpi_register_lapic_address()
1608 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1610 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n",
1611 APIC_BASE, apic_phys);
1615 * Fetch the APIC ID of the BSP in case we have a
1616 * default configuration (or the MP table is broken).
1618 new_apicid = read_apic_id();
1619 if (boot_cpu_physical_apicid != new_apicid) {
1620 boot_cpu_physical_apicid = new_apicid;
1622 * yeah -- we lie about apic_version
1623 * in case if apic was disabled via boot option
1624 * but it's not a problem for SMP compiled kernel
1625 * since smp_sanity_check is prepared for such a case
1626 * and disable smp mode
1628 apic_version[new_apicid] =
1629 GET_APIC_VERSION(apic_read(APIC_LVR));
1634 * This initializes the IO-APIC and APIC hardware if this is
1637 int apic_version[MAX_APICS];
1639 int __init APIC_init_uniprocessor(void)
1642 pr_info("Apic disabled\n");
1645 #ifdef CONFIG_X86_64
1646 if (!cpu_has_apic) {
1648 pr_info("Apic disabled by BIOS\n");
1652 if (!smp_found_config && !cpu_has_apic)
1656 * Complain if the BIOS pretends there is one.
1658 if (!cpu_has_apic &&
1659 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1660 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1661 boot_cpu_physical_apicid);
1667 #ifdef CONFIG_X86_64
1668 default_setup_apic_routing();
1671 verify_local_APIC();
1674 #ifdef CONFIG_X86_64
1675 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1678 * Hack: In case of kdump, after a crash, kernel might be booting
1679 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1680 * might be zero if read from MP tables. Get it from LAPIC.
1682 # ifdef CONFIG_CRASH_DUMP
1683 boot_cpu_physical_apicid = read_apic_id();
1686 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1689 #ifdef CONFIG_X86_IO_APIC
1691 * Now enable IO-APICs, actually call clear_IO_APIC
1692 * We need clear_IO_APIC before enabling error vector
1694 if (!skip_ioapic_setup && nr_ioapics)
1698 end_local_APIC_setup();
1700 #ifdef CONFIG_X86_IO_APIC
1701 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1705 localise_nmi_watchdog();
1708 localise_nmi_watchdog();
1712 #ifdef CONFIG_X86_64
1713 check_nmi_watchdog();
1720 * Local APIC interrupts
1724 * This interrupt should _never_ happen with our APIC/SMP architecture
1726 void smp_spurious_interrupt(struct pt_regs *regs)
1733 * Check if this really is a spurious interrupt and ACK it
1734 * if it is a vectored one. Just in case...
1735 * Spurious interrupts should not be ACKed.
1737 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1738 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1741 inc_irq_stat(irq_spurious_count);
1743 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1744 pr_info("spurious APIC interrupt on CPU#%d, "
1745 "should never happen.\n", smp_processor_id());
1750 * This interrupt should never happen with our APIC/SMP architecture
1752 void smp_error_interrupt(struct pt_regs *regs)
1758 /* First tickle the hardware, only then report what went on. -- REW */
1759 v = apic_read(APIC_ESR);
1760 apic_write(APIC_ESR, 0);
1761 v1 = apic_read(APIC_ESR);
1763 atomic_inc(&irq_err_count);
1766 * Here is what the APIC error bits mean:
1768 * 1: Receive CS error
1769 * 2: Send accept error
1770 * 3: Receive accept error
1772 * 5: Send illegal vector
1773 * 6: Received illegal vector
1774 * 7: Illegal register address
1776 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1777 smp_processor_id(), v , v1);
1782 * connect_bsp_APIC - attach the APIC to the interrupt system
1784 void __init connect_bsp_APIC(void)
1786 #ifdef CONFIG_X86_32
1789 * Do not trust the local APIC being empty at bootup.
1793 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1794 * local APIC to INT and NMI lines.
1796 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1797 "enabling APIC mode.\n");
1801 if (apic->enable_apic_mode)
1802 apic->enable_apic_mode();
1806 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1807 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1809 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1812 void disconnect_bsp_APIC(int virt_wire_setup)
1816 #ifdef CONFIG_X86_32
1819 * Put the board back into PIC mode (has an effect only on
1820 * certain older boards). Note that APIC interrupts, including
1821 * IPIs, won't work beyond this point! The only exception are
1824 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1825 "entering PIC mode.\n");
1831 /* Go back to Virtual Wire compatibility mode */
1833 /* For the spurious interrupt use vector F, and enable it */
1834 value = apic_read(APIC_SPIV);
1835 value &= ~APIC_VECTOR_MASK;
1836 value |= APIC_SPIV_APIC_ENABLED;
1838 apic_write(APIC_SPIV, value);
1840 if (!virt_wire_setup) {
1842 * For LVT0 make it edge triggered, active high,
1843 * external and enabled
1845 value = apic_read(APIC_LVT0);
1846 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1847 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1848 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1849 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1850 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1851 apic_write(APIC_LVT0, value);
1854 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1858 * For LVT1 make it edge triggered, active high,
1861 value = apic_read(APIC_LVT1);
1862 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1863 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1864 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1865 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1866 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1867 apic_write(APIC_LVT1, value);
1870 void __cpuinit generic_processor_info(int apicid, int version)
1877 if (version == 0x0) {
1878 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1879 "fixing up to 0x10. (tell your hw vendor)\n",
1883 apic_version[apicid] = version;
1885 if (num_processors >= nr_cpu_ids) {
1886 int max = nr_cpu_ids;
1887 int thiscpu = max + disabled_cpus;
1890 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1891 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
1898 cpu = cpumask_next_zero(-1, cpu_present_mask);
1900 if (version != apic_version[boot_cpu_physical_apicid])
1902 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1903 apic_version[boot_cpu_physical_apicid], cpu, version);
1905 physid_set(apicid, phys_cpu_present_map);
1906 if (apicid == boot_cpu_physical_apicid) {
1908 * x86_bios_cpu_apicid is required to have processors listed
1909 * in same order as logical cpu numbers. Hence the first
1910 * entry is BSP, and so on.
1914 if (apicid > max_physical_apicid)
1915 max_physical_apicid = apicid;
1917 #ifdef CONFIG_X86_32
1918 switch (boot_cpu_data.x86_vendor) {
1919 case X86_VENDOR_INTEL:
1920 if (num_processors > 8)
1923 case X86_VENDOR_AMD:
1924 if (max_physical_apicid >= 8)
1929 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
1930 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1931 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1934 set_cpu_possible(cpu, true);
1935 set_cpu_present(cpu, true);
1938 int hard_smp_processor_id(void)
1940 return read_apic_id();
1943 void default_init_apic_ldr(void)
1947 apic_write(APIC_DFR, APIC_DFR_VALUE);
1948 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
1949 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
1950 apic_write(APIC_LDR, val);
1953 #ifdef CONFIG_X86_32
1954 int default_apicid_to_node(int logical_apicid)
1957 return apicid_2_node[hard_smp_processor_id()];
1971 * 'active' is true if the local APIC was enabled by us and
1972 * not the BIOS; this signifies that we are also responsible
1973 * for disabling it before entering apm/acpi suspend
1976 /* r/w apic fields */
1977 unsigned int apic_id;
1978 unsigned int apic_taskpri;
1979 unsigned int apic_ldr;
1980 unsigned int apic_dfr;
1981 unsigned int apic_spiv;
1982 unsigned int apic_lvtt;
1983 unsigned int apic_lvtpc;
1984 unsigned int apic_lvt0;
1985 unsigned int apic_lvt1;
1986 unsigned int apic_lvterr;
1987 unsigned int apic_tmict;
1988 unsigned int apic_tdcr;
1989 unsigned int apic_thmr;
1992 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1994 unsigned long flags;
1997 if (!apic_pm_state.active)
2000 maxlvt = lapic_get_maxlvt();
2002 apic_pm_state.apic_id = apic_read(APIC_ID);
2003 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2004 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2005 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2006 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2007 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2009 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2010 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2011 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2012 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2013 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2014 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2015 #ifdef CONFIG_X86_THERMAL_VECTOR
2017 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2020 local_irq_save(flags);
2021 disable_local_APIC();
2023 if (intr_remapping_enabled)
2024 disable_intr_remapping();
2026 local_irq_restore(flags);
2030 static int lapic_resume(struct sys_device *dev)
2033 unsigned long flags;
2036 struct IO_APIC_route_entry **ioapic_entries = NULL;
2038 if (!apic_pm_state.active)
2041 local_irq_save(flags);
2042 if (intr_remapping_enabled) {
2043 ioapic_entries = alloc_ioapic_entries();
2044 if (!ioapic_entries) {
2045 WARN(1, "Alloc ioapic_entries in lapic resume failed.");
2050 ret = save_IO_APIC_setup(ioapic_entries);
2052 WARN(1, "Saving IO-APIC state failed: %d\n", ret);
2053 free_ioapic_entries(ioapic_entries);
2057 mask_IO_APIC_setup(ioapic_entries);
2065 * Make sure the APICBASE points to the right address
2067 * FIXME! This will be wrong if we ever support suspend on
2068 * SMP! We'll need to do this as part of the CPU restore!
2070 rdmsr(MSR_IA32_APICBASE, l, h);
2071 l &= ~MSR_IA32_APICBASE_BASE;
2072 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2073 wrmsr(MSR_IA32_APICBASE, l, h);
2076 maxlvt = lapic_get_maxlvt();
2077 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2078 apic_write(APIC_ID, apic_pm_state.apic_id);
2079 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2080 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2081 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2082 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2083 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2084 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2085 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2087 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2090 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2091 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2092 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2093 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2094 apic_write(APIC_ESR, 0);
2095 apic_read(APIC_ESR);
2096 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2097 apic_write(APIC_ESR, 0);
2098 apic_read(APIC_ESR);
2100 if (intr_remapping_enabled) {
2101 reenable_intr_remapping(x2apic_mode);
2103 restore_IO_APIC_setup(ioapic_entries);
2104 free_ioapic_entries(ioapic_entries);
2107 local_irq_restore(flags);
2113 * This device has no shutdown method - fully functioning local APICs
2114 * are needed on every CPU up until machine_halt/restart/poweroff.
2117 static struct sysdev_class lapic_sysclass = {
2119 .resume = lapic_resume,
2120 .suspend = lapic_suspend,
2123 static struct sys_device device_lapic = {
2125 .cls = &lapic_sysclass,
2128 static void __cpuinit apic_pm_activate(void)
2130 apic_pm_state.active = 1;
2133 static int __init init_lapic_sysfs(void)
2139 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2141 error = sysdev_class_register(&lapic_sysclass);
2143 error = sysdev_register(&device_lapic);
2147 /* local apic needs to resume before other devices access its registers. */
2148 core_initcall(init_lapic_sysfs);
2150 #else /* CONFIG_PM */
2152 static void apic_pm_activate(void) { }
2154 #endif /* CONFIG_PM */
2156 #ifdef CONFIG_X86_64
2158 static int __cpuinit apic_cluster_num(void)
2160 int i, clusters, zeros;
2162 u16 *bios_cpu_apicid;
2163 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
2165 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
2166 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
2168 for (i = 0; i < nr_cpu_ids; i++) {
2169 /* are we being called early in kernel startup? */
2170 if (bios_cpu_apicid) {
2171 id = bios_cpu_apicid[i];
2172 } else if (i < nr_cpu_ids) {
2174 id = per_cpu(x86_bios_cpu_apicid, i);
2180 if (id != BAD_APICID)
2181 __set_bit(APIC_CLUSTERID(id), clustermap);
2184 /* Problem: Partially populated chassis may not have CPUs in some of
2185 * the APIC clusters they have been allocated. Only present CPUs have
2186 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2187 * Since clusters are allocated sequentially, count zeros only if
2188 * they are bounded by ones.
2192 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
2193 if (test_bit(i, clustermap)) {
2194 clusters += 1 + zeros;
2203 static int __cpuinitdata multi_checked;
2204 static int __cpuinitdata multi;
2206 static int __cpuinit set_multi(const struct dmi_system_id *d)
2210 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2215 static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = {
2217 .callback = set_multi,
2218 .ident = "IBM System Summit2",
2220 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2221 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2227 static void __cpuinit dmi_check_multi(void)
2232 dmi_check_system(multi_dmi_table);
2237 * apic_is_clustered_box() -- Check if we can expect good TSC
2239 * Thus far, the major user of this is IBM's Summit2 series:
2240 * Clustered boxes may have unsynced TSC problems if they are
2242 * Use DMI to check them
2244 __cpuinit int apic_is_clustered_box(void)
2254 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2255 * not guaranteed to be synced between boards
2257 if (apic_cluster_num() > 1)
2265 * APIC command line parameters
2267 static int __init setup_disableapic(char *arg)
2270 setup_clear_cpu_cap(X86_FEATURE_APIC);
2273 early_param("disableapic", setup_disableapic);
2275 /* same as disableapic, for compatibility */
2276 static int __init setup_nolapic(char *arg)
2278 return setup_disableapic(arg);
2280 early_param("nolapic", setup_nolapic);
2282 static int __init parse_lapic_timer_c2_ok(char *arg)
2284 local_apic_timer_c2_ok = 1;
2287 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2289 static int __init parse_disable_apic_timer(char *arg)
2291 disable_apic_timer = 1;
2294 early_param("noapictimer", parse_disable_apic_timer);
2296 static int __init parse_nolapic_timer(char *arg)
2298 disable_apic_timer = 1;
2301 early_param("nolapic_timer", parse_nolapic_timer);
2303 static int __init apic_set_verbosity(char *arg)
2306 #ifdef CONFIG_X86_64
2307 skip_ioapic_setup = 0;
2313 if (strcmp("debug", arg) == 0)
2314 apic_verbosity = APIC_DEBUG;
2315 else if (strcmp("verbose", arg) == 0)
2316 apic_verbosity = APIC_VERBOSE;
2318 pr_warning("APIC Verbosity level %s not recognised"
2319 " use apic=verbose or apic=debug\n", arg);
2325 early_param("apic", apic_set_verbosity);
2327 static int __init lapic_insert_resource(void)
2332 /* Put local APIC into the resource map. */
2333 lapic_resource.start = apic_phys;
2334 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2335 insert_resource(&iomem_resource, &lapic_resource);
2341 * need call insert after e820_reserve_resources()
2342 * that is using request_resource
2344 late_initcall(lapic_insert_resource);