2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/gfp.h>
23 #include <linux/list.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <asm/pci-direct.h>
28 #include <asm/amd_iommu_types.h>
29 #include <asm/amd_iommu.h>
30 #include <asm/iommu.h>
34 * definitions for the ACPI scanning code
36 #define IVRS_HEADER_LENGTH 48
38 #define ACPI_IVHD_TYPE 0x10
39 #define ACPI_IVMD_TYPE_ALL 0x20
40 #define ACPI_IVMD_TYPE 0x21
41 #define ACPI_IVMD_TYPE_RANGE 0x22
43 #define IVHD_DEV_ALL 0x01
44 #define IVHD_DEV_SELECT 0x02
45 #define IVHD_DEV_SELECT_RANGE_START 0x03
46 #define IVHD_DEV_RANGE_END 0x04
47 #define IVHD_DEV_ALIAS 0x42
48 #define IVHD_DEV_ALIAS_RANGE 0x43
49 #define IVHD_DEV_EXT_SELECT 0x46
50 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
52 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
53 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
54 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
55 #define IVHD_FLAG_ISOC_EN_MASK 0x08
57 #define IVMD_FLAG_EXCL_RANGE 0x08
58 #define IVMD_FLAG_UNITY_MAP 0x01
60 #define ACPI_DEVFLAG_INITPASS 0x01
61 #define ACPI_DEVFLAG_EXTINT 0x02
62 #define ACPI_DEVFLAG_NMI 0x04
63 #define ACPI_DEVFLAG_SYSMGT1 0x10
64 #define ACPI_DEVFLAG_SYSMGT2 0x20
65 #define ACPI_DEVFLAG_LINT0 0x40
66 #define ACPI_DEVFLAG_LINT1 0x80
67 #define ACPI_DEVFLAG_ATSDIS 0x10000000
70 * ACPI table definitions
72 * These data structures are laid over the table to parse the important values
77 * structure describing one IOMMU in the ACPI table. Typically followed by one
78 * or more ivhd_entrys.
90 } __attribute__((packed));
93 * A device entry describing which devices a specific IOMMU translates and
94 * which requestor ids they use.
101 } __attribute__((packed));
104 * An AMD IOMMU memory definition structure. It defines things like exclusion
105 * ranges for devices and regions that should be unity mapped.
116 } __attribute__((packed));
118 static int __initdata amd_iommu_detected;
120 u16 amd_iommu_last_bdf; /* largest PCI device id we have
122 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
124 unsigned amd_iommu_aperture_order = 26; /* size of aperture in power of 2 */
125 bool amd_iommu_isolate = true; /* if true, device isolation is
127 bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
129 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
133 * Pointer to the device table which is shared by all AMD IOMMUs
134 * it is indexed by the PCI device id or the HT unit id and contains
135 * information about the domain the device belongs to as well as the
136 * page table root pointer.
138 struct dev_table_entry *amd_iommu_dev_table;
141 * The alias table is a driver specific data structure which contains the
142 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
143 * More than one device can share the same requestor id.
145 u16 *amd_iommu_alias_table;
148 * The rlookup table is used to find the IOMMU which is responsible
149 * for a specific device. It is also indexed by the PCI device id.
151 struct amd_iommu **amd_iommu_rlookup_table;
154 * The pd table (protection domain table) is used to find the protection domain
155 * data structure a device belongs to. Indexed with the PCI device id too.
157 struct protection_domain **amd_iommu_pd_table;
160 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
161 * to know which ones are already in use.
163 unsigned long *amd_iommu_pd_alloc_bitmap;
165 static u32 dev_table_size; /* size of the device table */
166 static u32 alias_table_size; /* size of the alias table */
167 static u32 rlookup_table_size; /* size if the rlookup table */
169 static inline void update_last_devid(u16 devid)
171 if (devid > amd_iommu_last_bdf)
172 amd_iommu_last_bdf = devid;
175 static inline unsigned long tbl_size(int entry_size)
177 unsigned shift = PAGE_SHIFT +
178 get_order(amd_iommu_last_bdf * entry_size);
183 /****************************************************************************
185 * AMD IOMMU MMIO register space handling functions
187 * These functions are used to program the IOMMU device registers in
188 * MMIO space required for that driver.
190 ****************************************************************************/
193 * This function set the exclusion range in the IOMMU. DMA accesses to the
194 * exclusion range are passed through untranslated
196 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
198 u64 start = iommu->exclusion_start & PAGE_MASK;
199 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
202 if (!iommu->exclusion_start)
205 entry = start | MMIO_EXCL_ENABLE_MASK;
206 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
207 &entry, sizeof(entry));
210 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
211 &entry, sizeof(entry));
214 /* Programs the physical address of the device table into the IOMMU hardware */
215 static void __init iommu_set_device_table(struct amd_iommu *iommu)
219 BUG_ON(iommu->mmio_base == NULL);
221 entry = virt_to_phys(amd_iommu_dev_table);
222 entry |= (dev_table_size >> 12) - 1;
223 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
224 &entry, sizeof(entry));
227 /* Generic functions to enable/disable certain features of the IOMMU. */
228 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
232 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
234 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
237 static void __init iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
241 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
243 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
246 /* Function to enable the hardware */
247 static void iommu_enable(struct amd_iommu *iommu)
249 printk(KERN_INFO "AMD IOMMU: Enabling IOMMU at %s cap 0x%hx\n",
250 dev_name(&iommu->dev->dev), iommu->cap_ptr);
252 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
255 static void iommu_disable(struct amd_iommu *iommu)
257 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
261 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
262 * the system has one.
264 static u8 * __init iommu_map_mmio_space(u64 address)
268 if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu"))
271 ret = ioremap_nocache(address, MMIO_REGION_LENGTH);
275 release_mem_region(address, MMIO_REGION_LENGTH);
280 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
282 if (iommu->mmio_base)
283 iounmap(iommu->mmio_base);
284 release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
287 /****************************************************************************
289 * The functions below belong to the first pass of AMD IOMMU ACPI table
290 * parsing. In this pass we try to find out the highest device id this
291 * code has to handle. Upon this information the size of the shared data
292 * structures is determined later.
294 ****************************************************************************/
297 * This function calculates the length of a given IVHD entry
299 static inline int ivhd_entry_length(u8 *ivhd)
301 return 0x04 << (*ivhd >> 6);
305 * This function reads the last device id the IOMMU has to handle from the PCI
306 * capability header for this IOMMU
308 static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
312 cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
313 update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
319 * After reading the highest device id from the IOMMU PCI capability header
320 * this function looks if there is a higher device id defined in the ACPI table
322 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
324 u8 *p = (void *)h, *end = (void *)h;
325 struct ivhd_entry *dev;
330 find_last_devid_on_pci(PCI_BUS(h->devid),
336 dev = (struct ivhd_entry *)p;
338 case IVHD_DEV_SELECT:
339 case IVHD_DEV_RANGE_END:
341 case IVHD_DEV_EXT_SELECT:
342 /* all the above subfield types refer to device ids */
343 update_last_devid(dev->devid);
348 p += ivhd_entry_length(p);
357 * Iterate over all IVHD entries in the ACPI table and find the highest device
358 * id which we need to handle. This is the first of three functions which parse
359 * the ACPI table. So we check the checksum here.
361 static int __init find_last_devid_acpi(struct acpi_table_header *table)
364 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
365 struct ivhd_header *h;
368 * Validate checksum here so we don't need to do it when
369 * we actually parse the table
371 for (i = 0; i < table->length; ++i)
374 /* ACPI table corrupt */
377 p += IVRS_HEADER_LENGTH;
379 end += table->length;
381 h = (struct ivhd_header *)p;
384 find_last_devid_from_ivhd(h);
396 /****************************************************************************
398 * The following functions belong the the code path which parses the ACPI table
399 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
400 * data structures, initialize the device/alias/rlookup table and also
401 * basically initialize the hardware.
403 ****************************************************************************/
406 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
407 * write commands to that buffer later and the IOMMU will execute them
410 static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
412 u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
413 get_order(CMD_BUFFER_SIZE));
418 iommu->cmd_buf_size = CMD_BUFFER_SIZE;
424 * This function writes the command buffer address to the hardware and
427 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
431 BUG_ON(iommu->cmd_buf == NULL);
433 entry = (u64)virt_to_phys(iommu->cmd_buf);
434 entry |= MMIO_CMD_SIZE_512;
436 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
437 &entry, sizeof(entry));
439 /* set head and tail to zero manually */
440 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
441 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
443 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
446 static void __init free_command_buffer(struct amd_iommu *iommu)
448 free_pages((unsigned long)iommu->cmd_buf,
449 get_order(iommu->cmd_buf_size));
452 /* allocates the memory where the IOMMU will log its events to */
453 static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
455 iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
456 get_order(EVT_BUFFER_SIZE));
458 if (iommu->evt_buf == NULL)
461 return iommu->evt_buf;
464 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
468 BUG_ON(iommu->evt_buf == NULL);
470 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
472 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
473 &entry, sizeof(entry));
475 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
478 static void __init free_event_buffer(struct amd_iommu *iommu)
480 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
483 /* sets a specific bit in the device table entry. */
484 static void set_dev_entry_bit(u16 devid, u8 bit)
486 int i = (bit >> 5) & 0x07;
487 int _bit = bit & 0x1f;
489 amd_iommu_dev_table[devid].data[i] |= (1 << _bit);
492 /* Writes the specific IOMMU for a device into the rlookup table */
493 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
495 amd_iommu_rlookup_table[devid] = iommu;
499 * This function takes the device specific flags read from the ACPI
500 * table and sets up the device table entry with that information
502 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
503 u16 devid, u32 flags, u32 ext_flags)
505 if (flags & ACPI_DEVFLAG_INITPASS)
506 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
507 if (flags & ACPI_DEVFLAG_EXTINT)
508 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
509 if (flags & ACPI_DEVFLAG_NMI)
510 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
511 if (flags & ACPI_DEVFLAG_SYSMGT1)
512 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
513 if (flags & ACPI_DEVFLAG_SYSMGT2)
514 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
515 if (flags & ACPI_DEVFLAG_LINT0)
516 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
517 if (flags & ACPI_DEVFLAG_LINT1)
518 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
520 set_iommu_for_device(iommu, devid);
524 * Reads the device exclusion range from ACPI and initialize IOMMU with
527 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
529 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
531 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
536 * We only can configure exclusion ranges per IOMMU, not
537 * per device. But we can enable the exclusion range per
538 * device. This is done here
540 set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
541 iommu->exclusion_start = m->range_start;
542 iommu->exclusion_length = m->range_length;
547 * This function reads some important data from the IOMMU PCI space and
548 * initializes the driver data structure with it. It reads the hardware
549 * capabilities and the first/last device entries
551 static void __init init_iommu_from_pci(struct amd_iommu *iommu)
553 int cap_ptr = iommu->cap_ptr;
556 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
558 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
560 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
563 iommu->first_device = calc_devid(MMIO_GET_BUS(range),
565 iommu->last_device = calc_devid(MMIO_GET_BUS(range),
567 iommu->evt_msi_num = MMIO_MSI_NUM(misc);
571 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
572 * initializes the hardware and our data structures with it.
574 static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
575 struct ivhd_header *h)
578 u8 *end = p, flags = 0;
579 u16 dev_i, devid = 0, devid_start = 0, devid_to = 0;
582 struct ivhd_entry *e;
585 * First set the recommended feature enable bits from ACPI
586 * into the IOMMU control registers
588 h->flags & IVHD_FLAG_HT_TUN_EN_MASK ?
589 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
590 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
592 h->flags & IVHD_FLAG_PASSPW_EN_MASK ?
593 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
594 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
596 h->flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
597 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
598 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
600 h->flags & IVHD_FLAG_ISOC_EN_MASK ?
601 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
602 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
605 * make IOMMU memory accesses cache coherent
607 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
610 * Done. Now parse the device entries
612 p += sizeof(struct ivhd_header);
616 e = (struct ivhd_entry *)p;
619 for (dev_i = iommu->first_device;
620 dev_i <= iommu->last_device; ++dev_i)
621 set_dev_entry_from_acpi(iommu, dev_i,
624 case IVHD_DEV_SELECT:
626 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
628 case IVHD_DEV_SELECT_RANGE_START:
629 devid_start = e->devid;
636 devid_to = e->ext >> 8;
637 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
638 amd_iommu_alias_table[devid] = devid_to;
640 case IVHD_DEV_ALIAS_RANGE:
641 devid_start = e->devid;
643 devid_to = e->ext >> 8;
647 case IVHD_DEV_EXT_SELECT:
649 set_dev_entry_from_acpi(iommu, devid, e->flags,
652 case IVHD_DEV_EXT_SELECT_RANGE:
653 devid_start = e->devid;
658 case IVHD_DEV_RANGE_END:
660 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
662 amd_iommu_alias_table[dev_i] = devid_to;
663 set_dev_entry_from_acpi(iommu,
664 amd_iommu_alias_table[dev_i],
672 p += ivhd_entry_length(p);
676 /* Initializes the device->iommu mapping for the driver */
677 static int __init init_iommu_devices(struct amd_iommu *iommu)
681 for (i = iommu->first_device; i <= iommu->last_device; ++i)
682 set_iommu_for_device(iommu, i);
687 static void __init free_iommu_one(struct amd_iommu *iommu)
689 free_command_buffer(iommu);
690 free_event_buffer(iommu);
691 iommu_unmap_mmio_space(iommu);
694 static void __init free_iommu_all(void)
696 struct amd_iommu *iommu, *next;
698 for_each_iommu_safe(iommu, next) {
699 list_del(&iommu->list);
700 free_iommu_one(iommu);
706 * This function clues the initialization function for one IOMMU
707 * together and also allocates the command buffer and programs the
708 * hardware. It does NOT enable the IOMMU. This is done afterwards.
710 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
712 spin_lock_init(&iommu->lock);
713 list_add_tail(&iommu->list, &amd_iommu_list);
716 * Copy data from ACPI table entry to the iommu struct
718 iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff);
722 iommu->cap_ptr = h->cap_ptr;
723 iommu->pci_seg = h->pci_seg;
724 iommu->mmio_phys = h->mmio_phys;
725 iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
726 if (!iommu->mmio_base)
729 iommu->cmd_buf = alloc_command_buffer(iommu);
733 iommu->evt_buf = alloc_event_buffer(iommu);
737 iommu->int_enabled = false;
739 init_iommu_from_pci(iommu);
740 init_iommu_from_acpi(iommu, h);
741 init_iommu_devices(iommu);
743 return pci_enable_device(iommu->dev);
747 * Iterates over all IOMMU entries in the ACPI table, allocates the
748 * IOMMU structure and initializes it with init_iommu_one()
750 static int __init init_iommu_all(struct acpi_table_header *table)
752 u8 *p = (u8 *)table, *end = (u8 *)table;
753 struct ivhd_header *h;
754 struct amd_iommu *iommu;
757 end += table->length;
758 p += IVRS_HEADER_LENGTH;
761 h = (struct ivhd_header *)p;
764 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
767 ret = init_iommu_one(iommu, h);
782 /****************************************************************************
784 * The following functions initialize the MSI interrupts for all IOMMUs
785 * in the system. Its a bit challenging because there could be multiple
786 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
789 ****************************************************************************/
791 static int __init iommu_setup_msi(struct amd_iommu *iommu)
795 if (pci_enable_msi(iommu->dev))
798 r = request_irq(iommu->dev->irq, amd_iommu_int_handler,
804 pci_disable_msi(iommu->dev);
808 iommu->int_enabled = true;
809 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
814 static int iommu_init_msi(struct amd_iommu *iommu)
816 if (iommu->int_enabled)
819 if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI))
820 return iommu_setup_msi(iommu);
825 /****************************************************************************
827 * The next functions belong to the third pass of parsing the ACPI
828 * table. In this last pass the memory mapping requirements are
829 * gathered (like exclusion and unity mapping reanges).
831 ****************************************************************************/
833 static void __init free_unity_maps(void)
835 struct unity_map_entry *entry, *next;
837 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
838 list_del(&entry->list);
843 /* called when we find an exclusion range definition in ACPI */
844 static int __init init_exclusion_range(struct ivmd_header *m)
850 set_device_exclusion_range(m->devid, m);
852 case ACPI_IVMD_TYPE_ALL:
853 for (i = 0; i <= amd_iommu_last_bdf; ++i)
854 set_device_exclusion_range(i, m);
856 case ACPI_IVMD_TYPE_RANGE:
857 for (i = m->devid; i <= m->aux; ++i)
858 set_device_exclusion_range(i, m);
867 /* called for unity map ACPI definition */
868 static int __init init_unity_map_range(struct ivmd_header *m)
870 struct unity_map_entry *e = 0;
872 e = kzalloc(sizeof(*e), GFP_KERNEL);
879 e->devid_start = e->devid_end = m->devid;
881 case ACPI_IVMD_TYPE_ALL:
883 e->devid_end = amd_iommu_last_bdf;
885 case ACPI_IVMD_TYPE_RANGE:
886 e->devid_start = m->devid;
887 e->devid_end = m->aux;
890 e->address_start = PAGE_ALIGN(m->range_start);
891 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
892 e->prot = m->flags >> 1;
894 list_add_tail(&e->list, &amd_iommu_unity_map);
899 /* iterates over all memory definitions we find in the ACPI table */
900 static int __init init_memory_definitions(struct acpi_table_header *table)
902 u8 *p = (u8 *)table, *end = (u8 *)table;
903 struct ivmd_header *m;
905 end += table->length;
906 p += IVRS_HEADER_LENGTH;
909 m = (struct ivmd_header *)p;
910 if (m->flags & IVMD_FLAG_EXCL_RANGE)
911 init_exclusion_range(m);
912 else if (m->flags & IVMD_FLAG_UNITY_MAP)
913 init_unity_map_range(m);
922 * Init the device table to not allow DMA access for devices and
923 * suppress all page faults
925 static void init_device_table(void)
929 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
930 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
931 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
936 * This function finally enables all IOMMUs found in the system after
937 * they have been initialized
939 static void enable_iommus(void)
941 struct amd_iommu *iommu;
943 for_each_iommu(iommu) {
944 iommu_set_device_table(iommu);
945 iommu_enable_command_buffer(iommu);
946 iommu_enable_event_buffer(iommu);
947 iommu_set_exclusion_range(iommu);
948 iommu_init_msi(iommu);
953 static void disable_iommus(void)
955 struct amd_iommu *iommu;
957 for_each_iommu(iommu)
958 iommu_disable(iommu);
962 * Suspend/Resume support
963 * disable suspend until real resume implemented
966 static int amd_iommu_resume(struct sys_device *dev)
969 * Disable IOMMUs before reprogramming the hardware registers.
970 * IOMMU is still enabled from the resume kernel.
974 /* re-load the hardware */
978 * we have to flush after the IOMMUs are enabled because a
979 * disabled IOMMU will never execute the commands we send
981 amd_iommu_flush_all_domains();
982 amd_iommu_flush_all_devices();
987 static int amd_iommu_suspend(struct sys_device *dev, pm_message_t state)
989 /* disable IOMMUs to go out of the way for BIOS */
995 static struct sysdev_class amd_iommu_sysdev_class = {
997 .suspend = amd_iommu_suspend,
998 .resume = amd_iommu_resume,
1001 static struct sys_device device_amd_iommu = {
1003 .cls = &amd_iommu_sysdev_class,
1007 * This is the core init function for AMD IOMMU hardware in the system.
1008 * This function is called from the generic x86 DMA layer initialization
1011 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1014 * 1 pass) Find the highest PCI device id the driver has to handle.
1015 * Upon this information the size of the data structures is
1016 * determined that needs to be allocated.
1018 * 2 pass) Initialize the data structures just allocated with the
1019 * information in the ACPI table about available AMD IOMMUs
1020 * in the system. It also maps the PCI devices in the
1021 * system to specific IOMMUs
1023 * 3 pass) After the basic data structures are allocated and
1024 * initialized we update them with information about memory
1025 * remapping requirements parsed out of the ACPI table in
1028 * After that the hardware is initialized and ready to go. In the last
1029 * step we do some Linux specific things like registering the driver in
1030 * the dma_ops interface and initializing the suspend/resume support
1031 * functions. Finally it prints some information about AMD IOMMUs and
1032 * the driver state and enables the hardware.
1034 int __init amd_iommu_init(void)
1040 printk(KERN_INFO "AMD IOMMU disabled by kernel command line\n");
1044 if (!amd_iommu_detected)
1048 * First parse ACPI tables to find the largest Bus/Dev/Func
1049 * we need to handle. Upon this information the shared data
1050 * structures for the IOMMUs in the system will be allocated
1052 if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0)
1055 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
1056 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
1057 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
1061 /* Device table - directly used by all IOMMUs */
1062 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1063 get_order(dev_table_size));
1064 if (amd_iommu_dev_table == NULL)
1068 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1069 * IOMMU see for that device
1071 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
1072 get_order(alias_table_size));
1073 if (amd_iommu_alias_table == NULL)
1076 /* IOMMU rlookup table - find the IOMMU for a specific device */
1077 amd_iommu_rlookup_table = (void *)__get_free_pages(
1078 GFP_KERNEL | __GFP_ZERO,
1079 get_order(rlookup_table_size));
1080 if (amd_iommu_rlookup_table == NULL)
1084 * Protection Domain table - maps devices to protection domains
1085 * This table has the same size as the rlookup_table
1087 amd_iommu_pd_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1088 get_order(rlookup_table_size));
1089 if (amd_iommu_pd_table == NULL)
1092 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
1093 GFP_KERNEL | __GFP_ZERO,
1094 get_order(MAX_DOMAIN_ID/8));
1095 if (amd_iommu_pd_alloc_bitmap == NULL)
1098 /* init the device table */
1099 init_device_table();
1102 * let all alias entries point to itself
1104 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1105 amd_iommu_alias_table[i] = i;
1108 * never allocate domain 0 because its used as the non-allocated and
1109 * error value placeholder
1111 amd_iommu_pd_alloc_bitmap[0] = 1;
1114 * now the data structures are allocated and basically initialized
1115 * start the real acpi table scan
1118 if (acpi_table_parse("IVRS", init_iommu_all) != 0)
1121 if (acpi_table_parse("IVRS", init_memory_definitions) != 0)
1124 ret = sysdev_class_register(&amd_iommu_sysdev_class);
1128 ret = sysdev_register(&device_amd_iommu);
1132 ret = amd_iommu_init_dma_ops();
1138 printk(KERN_INFO "AMD IOMMU: aperture size is %d MB\n",
1139 (1 << (amd_iommu_aperture_order-20)));
1141 printk(KERN_INFO "AMD IOMMU: device isolation ");
1142 if (amd_iommu_isolate)
1143 printk("enabled\n");
1145 printk("disabled\n");
1147 if (amd_iommu_unmap_flush)
1148 printk(KERN_INFO "AMD IOMMU: IO/TLB flush on unmap enabled\n");
1150 printk(KERN_INFO "AMD IOMMU: Lazy IO/TLB flushing enabled\n");
1156 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
1157 get_order(MAX_DOMAIN_ID/8));
1159 free_pages((unsigned long)amd_iommu_pd_table,
1160 get_order(rlookup_table_size));
1162 free_pages((unsigned long)amd_iommu_rlookup_table,
1163 get_order(rlookup_table_size));
1165 free_pages((unsigned long)amd_iommu_alias_table,
1166 get_order(alias_table_size));
1168 free_pages((unsigned long)amd_iommu_dev_table,
1169 get_order(dev_table_size));
1178 /****************************************************************************
1180 * Early detect code. This code runs at IOMMU detection time in the DMA
1181 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1184 ****************************************************************************/
1185 static int __init early_amd_iommu_detect(struct acpi_table_header *table)
1190 void __init amd_iommu_detect(void)
1192 if (swiotlb || no_iommu || (iommu_detected && !gart_iommu_aperture))
1195 if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) {
1197 amd_iommu_detected = 1;
1198 #ifdef CONFIG_GART_IOMMU
1199 gart_iommu_aperture_disabled = 1;
1200 gart_iommu_aperture = 0;
1205 /****************************************************************************
1207 * Parsing functions for the AMD IOMMU specific kernel command line
1210 ****************************************************************************/
1212 static int __init parse_amd_iommu_options(char *str)
1214 for (; *str; ++str) {
1215 if (strncmp(str, "isolate", 7) == 0)
1216 amd_iommu_isolate = true;
1217 if (strncmp(str, "share", 5) == 0)
1218 amd_iommu_isolate = false;
1219 if (strncmp(str, "fullflush", 9) == 0)
1220 amd_iommu_unmap_flush = true;
1226 static int __init parse_amd_iommu_size_options(char *str)
1228 unsigned order = PAGE_SHIFT + get_order(memparse(str, &str));
1230 if ((order > 24) && (order < 31))
1231 amd_iommu_aperture_order = order;
1236 __setup("amd_iommu=", parse_amd_iommu_options);
1237 __setup("amd_iommu_size=", parse_amd_iommu_size_options);