2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/scatterlist.h>
24 #include <linux/iommu-helper.h>
25 #include <asm/proto.h>
26 #include <asm/iommu.h>
28 #include <asm/amd_iommu_types.h>
29 #include <asm/amd_iommu.h>
31 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
33 #define EXIT_LOOP_COUNT 10000000
35 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
37 /* A list of preallocated protection domains */
38 static LIST_HEAD(iommu_pd_list);
39 static DEFINE_SPINLOCK(iommu_pd_list_lock);
42 * general struct to manage commands send to an IOMMU
48 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
49 struct unity_map_entry *e);
51 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
52 static int iommu_has_npcache(struct amd_iommu *iommu)
54 return iommu->cap & (1UL << IOMMU_CAP_NPCACHE);
57 /****************************************************************************
59 * Interrupt handling functions
61 ****************************************************************************/
63 static void iommu_print_event(void *__evt)
66 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
67 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
68 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
69 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
70 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
72 printk(KERN_ERR "AMD IOMMU: Event logged [");
75 case EVENT_TYPE_ILL_DEV:
76 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
77 "address=0x%016llx flags=0x%04x]\n",
78 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
81 case EVENT_TYPE_IO_FAULT:
82 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
83 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
84 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
85 domid, address, flags);
87 case EVENT_TYPE_DEV_TAB_ERR:
88 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
89 "address=0x%016llx flags=0x%04x]\n",
90 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
93 case EVENT_TYPE_PAGE_TAB_ERR:
94 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
95 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
96 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
97 domid, address, flags);
99 case EVENT_TYPE_ILL_CMD:
100 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
102 case EVENT_TYPE_CMD_HARD_ERR:
103 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
104 "flags=0x%04x]\n", address, flags);
106 case EVENT_TYPE_IOTLB_INV_TO:
107 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
108 "address=0x%016llx]\n",
109 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
112 case EVENT_TYPE_INV_DEV_REQ:
113 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
114 "address=0x%016llx flags=0x%04x]\n",
115 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
119 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
123 static void iommu_poll_events(struct amd_iommu *iommu)
128 spin_lock_irqsave(&iommu->lock, flags);
130 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
131 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
133 while (head != tail) {
134 iommu_print_event(iommu->evt_buf + head);
135 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
138 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
140 spin_unlock_irqrestore(&iommu->lock, flags);
143 irqreturn_t amd_iommu_int_handler(int irq, void *data)
145 struct amd_iommu *iommu;
147 list_for_each_entry(iommu, &amd_iommu_list, list)
148 iommu_poll_events(iommu);
153 /****************************************************************************
155 * IOMMU command queuing functions
157 ****************************************************************************/
160 * Writes the command to the IOMMUs command buffer and informs the
161 * hardware about the new command. Must be called with iommu->lock held.
163 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
168 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
169 target = iommu->cmd_buf + tail;
170 memcpy_toio(target, cmd, sizeof(*cmd));
171 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
172 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
175 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
181 * General queuing function for commands. Takes iommu->lock and calls
182 * __iommu_queue_command().
184 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
189 spin_lock_irqsave(&iommu->lock, flags);
190 ret = __iommu_queue_command(iommu, cmd);
191 spin_unlock_irqrestore(&iommu->lock, flags);
197 * This function is called whenever we need to ensure that the IOMMU has
198 * completed execution of all commands we sent. It sends a
199 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
200 * us about that by writing a value to a physical address we pass with
203 static int iommu_completion_wait(struct amd_iommu *iommu)
205 int ret = 0, ready = 0;
207 struct iommu_cmd cmd;
208 unsigned long flags, i = 0;
210 memset(&cmd, 0, sizeof(cmd));
211 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
212 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
214 iommu->need_sync = 0;
216 spin_lock_irqsave(&iommu->lock, flags);
218 ret = __iommu_queue_command(iommu, &cmd);
223 while (!ready && (i < EXIT_LOOP_COUNT)) {
225 /* wait for the bit to become one */
226 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
227 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
230 /* set bit back to zero */
231 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
232 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
234 if (unlikely((i == EXIT_LOOP_COUNT) && printk_ratelimit()))
235 printk(KERN_WARNING "AMD IOMMU: Completion wait loop failed\n");
237 spin_unlock_irqrestore(&iommu->lock, flags);
243 * Command send function for invalidating a device table entry
245 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
247 struct iommu_cmd cmd;
250 BUG_ON(iommu == NULL);
252 memset(&cmd, 0, sizeof(cmd));
253 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
256 ret = iommu_queue_command(iommu, &cmd);
258 iommu->need_sync = 1;
264 * Generic command send function for invalidaing TLB entries
266 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
267 u64 address, u16 domid, int pde, int s)
269 struct iommu_cmd cmd;
272 memset(&cmd, 0, sizeof(cmd));
273 address &= PAGE_MASK;
274 CMD_SET_TYPE(&cmd, CMD_INV_IOMMU_PAGES);
275 cmd.data[1] |= domid;
276 cmd.data[2] = lower_32_bits(address);
277 cmd.data[3] = upper_32_bits(address);
278 if (s) /* size bit - we flush more than one 4kb page */
279 cmd.data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
280 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
281 cmd.data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
283 ret = iommu_queue_command(iommu, &cmd);
285 iommu->need_sync = 1;
291 * TLB invalidation function which is called from the mapping functions.
292 * It invalidates a single PTE if the range to flush is within a single
293 * page. Otherwise it flushes the whole TLB of the IOMMU.
295 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
296 u64 address, size_t size)
299 unsigned pages = iommu_num_pages(address, size, PAGE_SIZE);
301 address &= PAGE_MASK;
305 * If we have to flush more than one page, flush all
306 * TLB entries for this domain
308 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
312 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
317 /* Flush the whole IO/TLB for a given protection domain */
318 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
320 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
322 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
325 /****************************************************************************
327 * The functions below are used the create the page table mappings for
328 * unity mapped regions.
330 ****************************************************************************/
333 * Generic mapping functions. It maps a physical address into a DMA
334 * address space. It allocates the page table pages if necessary.
335 * In the future it can be extended to a generic mapping function
336 * supporting all features of AMD IOMMU page tables like level skipping
337 * and full 64 bit address spaces.
339 static int iommu_map(struct protection_domain *dom,
340 unsigned long bus_addr,
341 unsigned long phys_addr,
344 u64 __pte, *pte, *page;
346 bus_addr = PAGE_ALIGN(bus_addr);
347 phys_addr = PAGE_ALIGN(bus_addr);
349 /* only support 512GB address spaces for now */
350 if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
353 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
355 if (!IOMMU_PTE_PRESENT(*pte)) {
356 page = (u64 *)get_zeroed_page(GFP_KERNEL);
359 *pte = IOMMU_L2_PDE(virt_to_phys(page));
362 pte = IOMMU_PTE_PAGE(*pte);
363 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
365 if (!IOMMU_PTE_PRESENT(*pte)) {
366 page = (u64 *)get_zeroed_page(GFP_KERNEL);
369 *pte = IOMMU_L1_PDE(virt_to_phys(page));
372 pte = IOMMU_PTE_PAGE(*pte);
373 pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)];
375 if (IOMMU_PTE_PRESENT(*pte))
378 __pte = phys_addr | IOMMU_PTE_P;
379 if (prot & IOMMU_PROT_IR)
380 __pte |= IOMMU_PTE_IR;
381 if (prot & IOMMU_PROT_IW)
382 __pte |= IOMMU_PTE_IW;
390 * This function checks if a specific unity mapping entry is needed for
391 * this specific IOMMU.
393 static int iommu_for_unity_map(struct amd_iommu *iommu,
394 struct unity_map_entry *entry)
398 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
399 bdf = amd_iommu_alias_table[i];
400 if (amd_iommu_rlookup_table[bdf] == iommu)
408 * Init the unity mappings for a specific IOMMU in the system
410 * Basically iterates over all unity mapping entries and applies them to
411 * the default domain DMA of that IOMMU if necessary.
413 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
415 struct unity_map_entry *entry;
418 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
419 if (!iommu_for_unity_map(iommu, entry))
421 ret = dma_ops_unity_map(iommu->default_dom, entry);
430 * This function actually applies the mapping to the page table of the
433 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
434 struct unity_map_entry *e)
439 for (addr = e->address_start; addr < e->address_end;
441 ret = iommu_map(&dma_dom->domain, addr, addr, e->prot);
445 * if unity mapping is in aperture range mark the page
446 * as allocated in the aperture
448 if (addr < dma_dom->aperture_size)
449 __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap);
456 * Inits the unity mappings required for a specific device
458 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
461 struct unity_map_entry *e;
464 list_for_each_entry(e, &amd_iommu_unity_map, list) {
465 if (!(devid >= e->devid_start && devid <= e->devid_end))
467 ret = dma_ops_unity_map(dma_dom, e);
475 /****************************************************************************
477 * The next functions belong to the address allocator for the dma_ops
478 * interface functions. They work like the allocators in the other IOMMU
479 * drivers. Its basically a bitmap which marks the allocated pages in
480 * the aperture. Maybe it could be enhanced in the future to a more
481 * efficient allocator.
483 ****************************************************************************/
486 * The address allocator core function.
488 * called with domain->lock held
490 static unsigned long dma_ops_alloc_addresses(struct device *dev,
491 struct dma_ops_domain *dom,
493 unsigned long align_mask,
497 unsigned long address;
498 unsigned long boundary_size;
500 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
501 PAGE_SIZE) >> PAGE_SHIFT;
502 limit = iommu_device_max_index(dom->aperture_size >> PAGE_SHIFT, 0,
503 dma_mask >> PAGE_SHIFT);
505 if (dom->next_bit >= limit) {
507 dom->need_flush = true;
510 address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages,
511 0 , boundary_size, align_mask);
513 address = iommu_area_alloc(dom->bitmap, limit, 0, pages,
514 0, boundary_size, align_mask);
515 dom->need_flush = true;
518 if (likely(address != -1)) {
519 dom->next_bit = address + pages;
520 address <<= PAGE_SHIFT;
522 address = bad_dma_address;
524 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
530 * The address free function.
532 * called with domain->lock held
534 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
535 unsigned long address,
538 address >>= PAGE_SHIFT;
539 iommu_area_free(dom->bitmap, address, pages);
541 if (address >= dom->next_bit)
542 dom->need_flush = true;
545 /****************************************************************************
547 * The next functions belong to the domain allocation. A domain is
548 * allocated for every IOMMU as the default domain. If device isolation
549 * is enabled, every device get its own domain. The most important thing
550 * about domains is the page table mapping the DMA address space they
553 ****************************************************************************/
555 static u16 domain_id_alloc(void)
560 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
561 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
563 if (id > 0 && id < MAX_DOMAIN_ID)
564 __set_bit(id, amd_iommu_pd_alloc_bitmap);
567 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
573 * Used to reserve address ranges in the aperture (e.g. for exclusion
576 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
577 unsigned long start_page,
580 unsigned int last_page = dom->aperture_size >> PAGE_SHIFT;
582 if (start_page + pages > last_page)
583 pages = last_page - start_page;
585 iommu_area_reserve(dom->bitmap, start_page, pages);
588 static void dma_ops_free_pagetable(struct dma_ops_domain *dma_dom)
593 p1 = dma_dom->domain.pt_root;
598 for (i = 0; i < 512; ++i) {
599 if (!IOMMU_PTE_PRESENT(p1[i]))
602 p2 = IOMMU_PTE_PAGE(p1[i]);
603 for (j = 0; j < 512; ++i) {
604 if (!IOMMU_PTE_PRESENT(p2[j]))
606 p3 = IOMMU_PTE_PAGE(p2[j]);
607 free_page((unsigned long)p3);
610 free_page((unsigned long)p2);
613 free_page((unsigned long)p1);
617 * Free a domain, only used if something went wrong in the
618 * allocation path and we need to free an already allocated page table
620 static void dma_ops_domain_free(struct dma_ops_domain *dom)
625 dma_ops_free_pagetable(dom);
627 kfree(dom->pte_pages);
635 * Allocates a new protection domain usable for the dma_ops functions.
636 * It also intializes the page table and the address allocator data
637 * structures required for the dma_ops interface
639 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu,
642 struct dma_ops_domain *dma_dom;
643 unsigned i, num_pte_pages;
648 * Currently the DMA aperture must be between 32 MB and 1GB in size
650 if ((order < 25) || (order > 30))
653 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
657 spin_lock_init(&dma_dom->domain.lock);
659 dma_dom->domain.id = domain_id_alloc();
660 if (dma_dom->domain.id == 0)
662 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
663 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
664 dma_dom->domain.priv = dma_dom;
665 if (!dma_dom->domain.pt_root)
667 dma_dom->aperture_size = (1ULL << order);
668 dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8),
670 if (!dma_dom->bitmap)
673 * mark the first page as allocated so we never return 0 as
674 * a valid dma-address. So we can use 0 as error value
676 dma_dom->bitmap[0] = 1;
677 dma_dom->next_bit = 0;
679 dma_dom->need_flush = false;
680 dma_dom->target_dev = 0xffff;
682 /* Intialize the exclusion range if necessary */
683 if (iommu->exclusion_start &&
684 iommu->exclusion_start < dma_dom->aperture_size) {
685 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
686 int pages = iommu_num_pages(iommu->exclusion_start,
687 iommu->exclusion_length,
689 dma_ops_reserve_addresses(dma_dom, startpage, pages);
693 * At the last step, build the page tables so we don't need to
694 * allocate page table pages in the dma_ops mapping/unmapping
697 num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512);
698 dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *),
700 if (!dma_dom->pte_pages)
703 l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL);
707 dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde));
709 for (i = 0; i < num_pte_pages; ++i) {
710 dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL);
711 if (!dma_dom->pte_pages[i])
713 address = virt_to_phys(dma_dom->pte_pages[i]);
714 l2_pde[i] = IOMMU_L1_PDE(address);
720 dma_ops_domain_free(dma_dom);
726 * Find out the protection domain structure for a given PCI device. This
727 * will give us the pointer to the page table root for example.
729 static struct protection_domain *domain_for_device(u16 devid)
731 struct protection_domain *dom;
734 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
735 dom = amd_iommu_pd_table[devid];
736 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
742 * If a device is not yet associated with a domain, this function does
743 * assigns it visible for the hardware
745 static void set_device_domain(struct amd_iommu *iommu,
746 struct protection_domain *domain,
751 u64 pte_root = virt_to_phys(domain->pt_root);
753 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
754 << DEV_ENTRY_MODE_SHIFT;
755 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
757 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
758 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
759 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
760 amd_iommu_dev_table[devid].data[2] = domain->id;
762 amd_iommu_pd_table[devid] = domain;
763 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
765 iommu_queue_inv_dev_entry(iommu, devid);
767 iommu->need_sync = 1;
770 /*****************************************************************************
772 * The next functions belong to the dma_ops mapping/unmapping code.
774 *****************************************************************************/
777 * This function checks if the driver got a valid device from the caller to
778 * avoid dereferencing invalid pointers.
780 static bool check_device(struct device *dev)
782 if (!dev || !dev->dma_mask)
789 * In this function the list of preallocated protection domains is traversed to
790 * find the domain for a specific device
792 static struct dma_ops_domain *find_protection_domain(u16 devid)
794 struct dma_ops_domain *entry, *ret = NULL;
797 if (list_empty(&iommu_pd_list))
800 spin_lock_irqsave(&iommu_pd_list_lock, flags);
802 list_for_each_entry(entry, &iommu_pd_list, list) {
803 if (entry->target_dev == devid) {
805 list_del(&ret->list);
810 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
816 * In the dma_ops path we only have the struct device. This function
817 * finds the corresponding IOMMU, the protection domain and the
818 * requestor id for a given device.
819 * If the device is not yet associated with a domain this is also done
822 static int get_device_resources(struct device *dev,
823 struct amd_iommu **iommu,
824 struct protection_domain **domain,
827 struct dma_ops_domain *dma_dom;
828 struct pci_dev *pcidev;
835 if (dev->bus != &pci_bus_type)
838 pcidev = to_pci_dev(dev);
839 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
841 /* device not translated by any IOMMU in the system? */
842 if (_bdf > amd_iommu_last_bdf)
845 *bdf = amd_iommu_alias_table[_bdf];
847 *iommu = amd_iommu_rlookup_table[*bdf];
850 *domain = domain_for_device(*bdf);
851 if (*domain == NULL) {
852 dma_dom = find_protection_domain(*bdf);
854 dma_dom = (*iommu)->default_dom;
855 *domain = &dma_dom->domain;
856 set_device_domain(*iommu, *domain, *bdf);
857 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
858 "device ", (*domain)->id);
859 print_devid(_bdf, 1);
866 * This is the generic map function. It maps one 4kb page at paddr to
867 * the given address in the DMA address space for the domain.
869 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
870 struct dma_ops_domain *dom,
871 unsigned long address,
877 WARN_ON(address > dom->aperture_size);
881 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
882 pte += IOMMU_PTE_L0_INDEX(address);
884 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
886 if (direction == DMA_TO_DEVICE)
887 __pte |= IOMMU_PTE_IR;
888 else if (direction == DMA_FROM_DEVICE)
889 __pte |= IOMMU_PTE_IW;
890 else if (direction == DMA_BIDIRECTIONAL)
891 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
897 return (dma_addr_t)address;
901 * The generic unmapping function for on page in the DMA address space.
903 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
904 struct dma_ops_domain *dom,
905 unsigned long address)
909 if (address >= dom->aperture_size)
912 WARN_ON(address & 0xfffULL || address > dom->aperture_size);
914 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
915 pte += IOMMU_PTE_L0_INDEX(address);
923 * This function contains common code for mapping of a physically
924 * contiguous memory region into DMA address space. It is uses by all
925 * mapping functions provided by this IOMMU driver.
926 * Must be called with the domain lock held.
928 static dma_addr_t __map_single(struct device *dev,
929 struct amd_iommu *iommu,
930 struct dma_ops_domain *dma_dom,
937 dma_addr_t offset = paddr & ~PAGE_MASK;
938 dma_addr_t address, start;
940 unsigned long align_mask = 0;
943 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
947 align_mask = (1UL << get_order(size)) - 1;
949 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
951 if (unlikely(address == bad_dma_address))
955 for (i = 0; i < pages; ++i) {
956 dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
962 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
963 iommu_flush_tlb(iommu, dma_dom->domain.id);
964 dma_dom->need_flush = false;
965 } else if (unlikely(iommu_has_npcache(iommu)))
966 iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
973 * Does the reverse of the __map_single function. Must be called with
974 * the domain lock held too
976 static void __unmap_single(struct amd_iommu *iommu,
977 struct dma_ops_domain *dma_dom,
985 if ((dma_addr == 0) || (dma_addr + size > dma_dom->aperture_size))
988 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
989 dma_addr &= PAGE_MASK;
992 for (i = 0; i < pages; ++i) {
993 dma_ops_domain_unmap(iommu, dma_dom, start);
997 dma_ops_free_addresses(dma_dom, dma_addr, pages);
999 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1000 iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
1001 dma_dom->need_flush = false;
1006 * The exported map_single function for dma_ops.
1008 static dma_addr_t map_single(struct device *dev, phys_addr_t paddr,
1009 size_t size, int dir)
1011 unsigned long flags;
1012 struct amd_iommu *iommu;
1013 struct protection_domain *domain;
1018 if (!check_device(dev))
1019 return bad_dma_address;
1021 dma_mask = *dev->dma_mask;
1023 get_device_resources(dev, &iommu, &domain, &devid);
1025 if (iommu == NULL || domain == NULL)
1026 /* device not handled by any AMD IOMMU */
1027 return (dma_addr_t)paddr;
1029 spin_lock_irqsave(&domain->lock, flags);
1030 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false,
1032 if (addr == bad_dma_address)
1035 if (unlikely(iommu->need_sync))
1036 iommu_completion_wait(iommu);
1039 spin_unlock_irqrestore(&domain->lock, flags);
1045 * The exported unmap_single function for dma_ops.
1047 static void unmap_single(struct device *dev, dma_addr_t dma_addr,
1048 size_t size, int dir)
1050 unsigned long flags;
1051 struct amd_iommu *iommu;
1052 struct protection_domain *domain;
1055 if (!check_device(dev) ||
1056 !get_device_resources(dev, &iommu, &domain, &devid))
1057 /* device not handled by any AMD IOMMU */
1060 spin_lock_irqsave(&domain->lock, flags);
1062 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
1064 if (unlikely(iommu->need_sync))
1065 iommu_completion_wait(iommu);
1067 spin_unlock_irqrestore(&domain->lock, flags);
1071 * This is a special map_sg function which is used if we should map a
1072 * device which is not handled by an AMD IOMMU in the system.
1074 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1075 int nelems, int dir)
1077 struct scatterlist *s;
1080 for_each_sg(sglist, s, nelems, i) {
1081 s->dma_address = (dma_addr_t)sg_phys(s);
1082 s->dma_length = s->length;
1089 * The exported map_sg function for dma_ops (handles scatter-gather
1092 static int map_sg(struct device *dev, struct scatterlist *sglist,
1093 int nelems, int dir)
1095 unsigned long flags;
1096 struct amd_iommu *iommu;
1097 struct protection_domain *domain;
1100 struct scatterlist *s;
1102 int mapped_elems = 0;
1105 if (!check_device(dev))
1108 dma_mask = *dev->dma_mask;
1110 get_device_resources(dev, &iommu, &domain, &devid);
1112 if (!iommu || !domain)
1113 return map_sg_no_iommu(dev, sglist, nelems, dir);
1115 spin_lock_irqsave(&domain->lock, flags);
1117 for_each_sg(sglist, s, nelems, i) {
1120 s->dma_address = __map_single(dev, iommu, domain->priv,
1121 paddr, s->length, dir, false,
1124 if (s->dma_address) {
1125 s->dma_length = s->length;
1131 if (unlikely(iommu->need_sync))
1132 iommu_completion_wait(iommu);
1135 spin_unlock_irqrestore(&domain->lock, flags);
1137 return mapped_elems;
1139 for_each_sg(sglist, s, mapped_elems, i) {
1141 __unmap_single(iommu, domain->priv, s->dma_address,
1142 s->dma_length, dir);
1143 s->dma_address = s->dma_length = 0;
1152 * The exported map_sg function for dma_ops (handles scatter-gather
1155 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1156 int nelems, int dir)
1158 unsigned long flags;
1159 struct amd_iommu *iommu;
1160 struct protection_domain *domain;
1161 struct scatterlist *s;
1165 if (!check_device(dev) ||
1166 !get_device_resources(dev, &iommu, &domain, &devid))
1169 spin_lock_irqsave(&domain->lock, flags);
1171 for_each_sg(sglist, s, nelems, i) {
1172 __unmap_single(iommu, domain->priv, s->dma_address,
1173 s->dma_length, dir);
1174 s->dma_address = s->dma_length = 0;
1177 if (unlikely(iommu->need_sync))
1178 iommu_completion_wait(iommu);
1180 spin_unlock_irqrestore(&domain->lock, flags);
1184 * The exported alloc_coherent function for dma_ops.
1186 static void *alloc_coherent(struct device *dev, size_t size,
1187 dma_addr_t *dma_addr, gfp_t flag)
1189 unsigned long flags;
1191 struct amd_iommu *iommu;
1192 struct protection_domain *domain;
1195 u64 dma_mask = dev->coherent_dma_mask;
1197 if (!check_device(dev))
1200 if (!get_device_resources(dev, &iommu, &domain, &devid))
1201 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
1204 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1208 paddr = virt_to_phys(virt_addr);
1210 if (!iommu || !domain) {
1211 *dma_addr = (dma_addr_t)paddr;
1216 dma_mask = *dev->dma_mask;
1218 spin_lock_irqsave(&domain->lock, flags);
1220 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1221 size, DMA_BIDIRECTIONAL, true, dma_mask);
1223 if (*dma_addr == bad_dma_address) {
1224 free_pages((unsigned long)virt_addr, get_order(size));
1229 if (unlikely(iommu->need_sync))
1230 iommu_completion_wait(iommu);
1233 spin_unlock_irqrestore(&domain->lock, flags);
1239 * The exported free_coherent function for dma_ops.
1241 static void free_coherent(struct device *dev, size_t size,
1242 void *virt_addr, dma_addr_t dma_addr)
1244 unsigned long flags;
1245 struct amd_iommu *iommu;
1246 struct protection_domain *domain;
1249 if (!check_device(dev))
1252 get_device_resources(dev, &iommu, &domain, &devid);
1254 if (!iommu || !domain)
1257 spin_lock_irqsave(&domain->lock, flags);
1259 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
1261 if (unlikely(iommu->need_sync))
1262 iommu_completion_wait(iommu);
1264 spin_unlock_irqrestore(&domain->lock, flags);
1267 free_pages((unsigned long)virt_addr, get_order(size));
1271 * This function is called by the DMA layer to find out if we can handle a
1272 * particular device. It is part of the dma_ops.
1274 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
1277 struct pci_dev *pcidev;
1279 /* No device or no PCI device */
1280 if (!dev || dev->bus != &pci_bus_type)
1283 pcidev = to_pci_dev(dev);
1285 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1287 /* Out of our scope? */
1288 if (bdf > amd_iommu_last_bdf)
1295 * The function for pre-allocating protection domains.
1297 * If the driver core informs the DMA layer if a driver grabs a device
1298 * we don't need to preallocate the protection domains anymore.
1299 * For now we have to.
1301 void prealloc_protection_domains(void)
1303 struct pci_dev *dev = NULL;
1304 struct dma_ops_domain *dma_dom;
1305 struct amd_iommu *iommu;
1306 int order = amd_iommu_aperture_order;
1309 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1310 devid = (dev->bus->number << 8) | dev->devfn;
1311 if (devid > amd_iommu_last_bdf)
1313 devid = amd_iommu_alias_table[devid];
1314 if (domain_for_device(devid))
1316 iommu = amd_iommu_rlookup_table[devid];
1319 dma_dom = dma_ops_domain_alloc(iommu, order);
1322 init_unity_mappings_for_device(dma_dom, devid);
1323 dma_dom->target_dev = devid;
1325 list_add_tail(&dma_dom->list, &iommu_pd_list);
1329 static struct dma_mapping_ops amd_iommu_dma_ops = {
1330 .alloc_coherent = alloc_coherent,
1331 .free_coherent = free_coherent,
1332 .map_single = map_single,
1333 .unmap_single = unmap_single,
1335 .unmap_sg = unmap_sg,
1336 .dma_supported = amd_iommu_dma_supported,
1340 * The function which clues the AMD IOMMU driver into dma_ops.
1342 int __init amd_iommu_init_dma_ops(void)
1344 struct amd_iommu *iommu;
1345 int order = amd_iommu_aperture_order;
1349 * first allocate a default protection domain for every IOMMU we
1350 * found in the system. Devices not assigned to any other
1351 * protection domain will be assigned to the default one.
1353 list_for_each_entry(iommu, &amd_iommu_list, list) {
1354 iommu->default_dom = dma_ops_domain_alloc(iommu, order);
1355 if (iommu->default_dom == NULL)
1357 ret = iommu_init_unity_mappings(iommu);
1363 * If device isolation is enabled, pre-allocate the protection
1364 * domains for each device.
1366 if (amd_iommu_isolate)
1367 prealloc_protection_domains();
1371 bad_dma_address = 0;
1372 #ifdef CONFIG_GART_IOMMU
1373 gart_iommu_aperture_disabled = 1;
1374 gart_iommu_aperture = 0;
1377 /* Make the driver finally visible to the drivers */
1378 dma_ops = &amd_iommu_dma_ops;
1384 list_for_each_entry(iommu, &amd_iommu_list, list) {
1385 if (iommu->default_dom)
1386 dma_ops_domain_free(iommu->default_dom);