2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/scatterlist.h>
24 #include <linux/iommu-helper.h>
25 #ifdef CONFIG_IOMMU_API
26 #include <linux/iommu.h>
28 #include <asm/proto.h>
29 #include <asm/iommu.h>
31 #include <asm/amd_iommu_types.h>
32 #include <asm/amd_iommu.h>
34 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
36 #define EXIT_LOOP_COUNT 10000000
38 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
40 /* A list of preallocated protection domains */
41 static LIST_HEAD(iommu_pd_list);
42 static DEFINE_SPINLOCK(iommu_pd_list_lock);
44 #ifdef CONFIG_IOMMU_API
45 static struct iommu_ops amd_iommu_ops;
49 * general struct to manage commands send to an IOMMU
55 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
56 struct unity_map_entry *e);
57 static struct dma_ops_domain *find_protection_domain(u16 devid);
60 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
61 static int iommu_has_npcache(struct amd_iommu *iommu)
63 return iommu->cap & (1UL << IOMMU_CAP_NPCACHE);
66 /****************************************************************************
68 * Interrupt handling functions
70 ****************************************************************************/
72 static void iommu_print_event(void *__evt)
75 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
76 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
77 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
78 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
79 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
81 printk(KERN_ERR "AMD IOMMU: Event logged [");
84 case EVENT_TYPE_ILL_DEV:
85 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
86 "address=0x%016llx flags=0x%04x]\n",
87 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
90 case EVENT_TYPE_IO_FAULT:
91 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
92 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
93 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
94 domid, address, flags);
96 case EVENT_TYPE_DEV_TAB_ERR:
97 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
98 "address=0x%016llx flags=0x%04x]\n",
99 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
102 case EVENT_TYPE_PAGE_TAB_ERR:
103 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
104 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
105 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
106 domid, address, flags);
108 case EVENT_TYPE_ILL_CMD:
109 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
111 case EVENT_TYPE_CMD_HARD_ERR:
112 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
113 "flags=0x%04x]\n", address, flags);
115 case EVENT_TYPE_IOTLB_INV_TO:
116 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
117 "address=0x%016llx]\n",
118 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
121 case EVENT_TYPE_INV_DEV_REQ:
122 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
123 "address=0x%016llx flags=0x%04x]\n",
124 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
128 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
132 static void iommu_poll_events(struct amd_iommu *iommu)
137 spin_lock_irqsave(&iommu->lock, flags);
139 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
140 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
142 while (head != tail) {
143 iommu_print_event(iommu->evt_buf + head);
144 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
147 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
149 spin_unlock_irqrestore(&iommu->lock, flags);
152 irqreturn_t amd_iommu_int_handler(int irq, void *data)
154 struct amd_iommu *iommu;
156 list_for_each_entry(iommu, &amd_iommu_list, list)
157 iommu_poll_events(iommu);
162 /****************************************************************************
164 * IOMMU command queuing functions
166 ****************************************************************************/
169 * Writes the command to the IOMMUs command buffer and informs the
170 * hardware about the new command. Must be called with iommu->lock held.
172 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
177 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
178 target = iommu->cmd_buf + tail;
179 memcpy_toio(target, cmd, sizeof(*cmd));
180 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
181 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
184 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
190 * General queuing function for commands. Takes iommu->lock and calls
191 * __iommu_queue_command().
193 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
198 spin_lock_irqsave(&iommu->lock, flags);
199 ret = __iommu_queue_command(iommu, cmd);
201 iommu->need_sync = 1;
202 spin_unlock_irqrestore(&iommu->lock, flags);
208 * This function waits until an IOMMU has completed a completion
211 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
217 while (!ready && (i < EXIT_LOOP_COUNT)) {
219 /* wait for the bit to become one */
220 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
221 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
224 /* set bit back to zero */
225 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
226 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
228 if (unlikely(i == EXIT_LOOP_COUNT))
229 panic("AMD IOMMU: Completion wait loop failed\n");
233 * This function queues a completion wait command into the command
236 static int __iommu_completion_wait(struct amd_iommu *iommu)
238 struct iommu_cmd cmd;
240 memset(&cmd, 0, sizeof(cmd));
241 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
242 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
244 return __iommu_queue_command(iommu, &cmd);
248 * This function is called whenever we need to ensure that the IOMMU has
249 * completed execution of all commands we sent. It sends a
250 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
251 * us about that by writing a value to a physical address we pass with
254 static int iommu_completion_wait(struct amd_iommu *iommu)
259 spin_lock_irqsave(&iommu->lock, flags);
261 if (!iommu->need_sync)
264 ret = __iommu_completion_wait(iommu);
266 iommu->need_sync = 0;
271 __iommu_wait_for_completion(iommu);
274 spin_unlock_irqrestore(&iommu->lock, flags);
280 * Command send function for invalidating a device table entry
282 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
284 struct iommu_cmd cmd;
287 BUG_ON(iommu == NULL);
289 memset(&cmd, 0, sizeof(cmd));
290 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
293 ret = iommu_queue_command(iommu, &cmd);
298 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
299 u16 domid, int pde, int s)
301 memset(cmd, 0, sizeof(*cmd));
302 address &= PAGE_MASK;
303 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
304 cmd->data[1] |= domid;
305 cmd->data[2] = lower_32_bits(address);
306 cmd->data[3] = upper_32_bits(address);
307 if (s) /* size bit - we flush more than one 4kb page */
308 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
309 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
310 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
314 * Generic command send function for invalidaing TLB entries
316 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
317 u64 address, u16 domid, int pde, int s)
319 struct iommu_cmd cmd;
322 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
324 ret = iommu_queue_command(iommu, &cmd);
330 * TLB invalidation function which is called from the mapping functions.
331 * It invalidates a single PTE if the range to flush is within a single
332 * page. Otherwise it flushes the whole TLB of the IOMMU.
334 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
335 u64 address, size_t size)
338 unsigned pages = iommu_num_pages(address, size, PAGE_SIZE);
340 address &= PAGE_MASK;
344 * If we have to flush more than one page, flush all
345 * TLB entries for this domain
347 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
351 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
356 /* Flush the whole IO/TLB for a given protection domain */
357 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
359 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
361 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
364 #ifdef CONFIG_IOMMU_API
366 * This function is used to flush the IO/TLB for a given protection domain
367 * on every IOMMU in the system
369 static void iommu_flush_domain(u16 domid)
372 struct amd_iommu *iommu;
373 struct iommu_cmd cmd;
375 __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
378 list_for_each_entry(iommu, &amd_iommu_list, list) {
379 spin_lock_irqsave(&iommu->lock, flags);
380 __iommu_queue_command(iommu, &cmd);
381 __iommu_completion_wait(iommu);
382 __iommu_wait_for_completion(iommu);
383 spin_unlock_irqrestore(&iommu->lock, flags);
388 /****************************************************************************
390 * The functions below are used the create the page table mappings for
391 * unity mapped regions.
393 ****************************************************************************/
396 * Generic mapping functions. It maps a physical address into a DMA
397 * address space. It allocates the page table pages if necessary.
398 * In the future it can be extended to a generic mapping function
399 * supporting all features of AMD IOMMU page tables like level skipping
400 * and full 64 bit address spaces.
402 static int iommu_map_page(struct protection_domain *dom,
403 unsigned long bus_addr,
404 unsigned long phys_addr,
407 u64 __pte, *pte, *page;
409 bus_addr = PAGE_ALIGN(bus_addr);
410 phys_addr = PAGE_ALIGN(phys_addr);
412 /* only support 512GB address spaces for now */
413 if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
416 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
418 if (!IOMMU_PTE_PRESENT(*pte)) {
419 page = (u64 *)get_zeroed_page(GFP_KERNEL);
422 *pte = IOMMU_L2_PDE(virt_to_phys(page));
425 pte = IOMMU_PTE_PAGE(*pte);
426 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
428 if (!IOMMU_PTE_PRESENT(*pte)) {
429 page = (u64 *)get_zeroed_page(GFP_KERNEL);
432 *pte = IOMMU_L1_PDE(virt_to_phys(page));
435 pte = IOMMU_PTE_PAGE(*pte);
436 pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)];
438 if (IOMMU_PTE_PRESENT(*pte))
441 __pte = phys_addr | IOMMU_PTE_P;
442 if (prot & IOMMU_PROT_IR)
443 __pte |= IOMMU_PTE_IR;
444 if (prot & IOMMU_PROT_IW)
445 __pte |= IOMMU_PTE_IW;
452 #ifdef CONFIG_IOMMU_API
453 static void iommu_unmap_page(struct protection_domain *dom,
454 unsigned long bus_addr)
458 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
460 if (!IOMMU_PTE_PRESENT(*pte))
463 pte = IOMMU_PTE_PAGE(*pte);
464 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
466 if (!IOMMU_PTE_PRESENT(*pte))
469 pte = IOMMU_PTE_PAGE(*pte);
470 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
477 * This function checks if a specific unity mapping entry is needed for
478 * this specific IOMMU.
480 static int iommu_for_unity_map(struct amd_iommu *iommu,
481 struct unity_map_entry *entry)
485 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
486 bdf = amd_iommu_alias_table[i];
487 if (amd_iommu_rlookup_table[bdf] == iommu)
495 * Init the unity mappings for a specific IOMMU in the system
497 * Basically iterates over all unity mapping entries and applies them to
498 * the default domain DMA of that IOMMU if necessary.
500 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
502 struct unity_map_entry *entry;
505 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
506 if (!iommu_for_unity_map(iommu, entry))
508 ret = dma_ops_unity_map(iommu->default_dom, entry);
517 * This function actually applies the mapping to the page table of the
520 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
521 struct unity_map_entry *e)
526 for (addr = e->address_start; addr < e->address_end;
528 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot);
532 * if unity mapping is in aperture range mark the page
533 * as allocated in the aperture
535 if (addr < dma_dom->aperture_size)
536 __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap);
543 * Inits the unity mappings required for a specific device
545 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
548 struct unity_map_entry *e;
551 list_for_each_entry(e, &amd_iommu_unity_map, list) {
552 if (!(devid >= e->devid_start && devid <= e->devid_end))
554 ret = dma_ops_unity_map(dma_dom, e);
562 /****************************************************************************
564 * The next functions belong to the address allocator for the dma_ops
565 * interface functions. They work like the allocators in the other IOMMU
566 * drivers. Its basically a bitmap which marks the allocated pages in
567 * the aperture. Maybe it could be enhanced in the future to a more
568 * efficient allocator.
570 ****************************************************************************/
573 * The address allocator core function.
575 * called with domain->lock held
577 static unsigned long dma_ops_alloc_addresses(struct device *dev,
578 struct dma_ops_domain *dom,
580 unsigned long align_mask,
584 unsigned long address;
585 unsigned long boundary_size;
587 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
588 PAGE_SIZE) >> PAGE_SHIFT;
589 limit = iommu_device_max_index(dom->aperture_size >> PAGE_SHIFT, 0,
590 dma_mask >> PAGE_SHIFT);
592 if (dom->next_bit >= limit) {
594 dom->need_flush = true;
597 address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages,
598 0 , boundary_size, align_mask);
600 address = iommu_area_alloc(dom->bitmap, limit, 0, pages,
601 0, boundary_size, align_mask);
602 dom->need_flush = true;
605 if (likely(address != -1)) {
606 dom->next_bit = address + pages;
607 address <<= PAGE_SHIFT;
609 address = bad_dma_address;
611 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
617 * The address free function.
619 * called with domain->lock held
621 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
622 unsigned long address,
625 address >>= PAGE_SHIFT;
626 iommu_area_free(dom->bitmap, address, pages);
628 if (address >= dom->next_bit)
629 dom->need_flush = true;
632 /****************************************************************************
634 * The next functions belong to the domain allocation. A domain is
635 * allocated for every IOMMU as the default domain. If device isolation
636 * is enabled, every device get its own domain. The most important thing
637 * about domains is the page table mapping the DMA address space they
640 ****************************************************************************/
642 static u16 domain_id_alloc(void)
647 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
648 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
650 if (id > 0 && id < MAX_DOMAIN_ID)
651 __set_bit(id, amd_iommu_pd_alloc_bitmap);
654 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
659 #ifdef CONFIG_IOMMU_API
660 static void domain_id_free(int id)
664 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
665 if (id > 0 && id < MAX_DOMAIN_ID)
666 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
667 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
672 * Used to reserve address ranges in the aperture (e.g. for exclusion
675 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
676 unsigned long start_page,
679 unsigned int last_page = dom->aperture_size >> PAGE_SHIFT;
681 if (start_page + pages > last_page)
682 pages = last_page - start_page;
684 iommu_area_reserve(dom->bitmap, start_page, pages);
687 static void free_pagetable(struct protection_domain *domain)
692 p1 = domain->pt_root;
697 for (i = 0; i < 512; ++i) {
698 if (!IOMMU_PTE_PRESENT(p1[i]))
701 p2 = IOMMU_PTE_PAGE(p1[i]);
702 for (j = 0; j < 512; ++j) {
703 if (!IOMMU_PTE_PRESENT(p2[j]))
705 p3 = IOMMU_PTE_PAGE(p2[j]);
706 free_page((unsigned long)p3);
709 free_page((unsigned long)p2);
712 free_page((unsigned long)p1);
714 domain->pt_root = NULL;
718 * Free a domain, only used if something went wrong in the
719 * allocation path and we need to free an already allocated page table
721 static void dma_ops_domain_free(struct dma_ops_domain *dom)
726 free_pagetable(&dom->domain);
728 kfree(dom->pte_pages);
736 * Allocates a new protection domain usable for the dma_ops functions.
737 * It also intializes the page table and the address allocator data
738 * structures required for the dma_ops interface
740 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu,
743 struct dma_ops_domain *dma_dom;
744 unsigned i, num_pte_pages;
749 * Currently the DMA aperture must be between 32 MB and 1GB in size
751 if ((order < 25) || (order > 30))
754 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
758 spin_lock_init(&dma_dom->domain.lock);
760 dma_dom->domain.id = domain_id_alloc();
761 if (dma_dom->domain.id == 0)
763 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
764 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
765 dma_dom->domain.flags = PD_DMA_OPS_MASK;
766 dma_dom->domain.priv = dma_dom;
767 if (!dma_dom->domain.pt_root)
769 dma_dom->aperture_size = (1ULL << order);
770 dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8),
772 if (!dma_dom->bitmap)
775 * mark the first page as allocated so we never return 0 as
776 * a valid dma-address. So we can use 0 as error value
778 dma_dom->bitmap[0] = 1;
779 dma_dom->next_bit = 0;
781 dma_dom->need_flush = false;
782 dma_dom->target_dev = 0xffff;
784 /* Intialize the exclusion range if necessary */
785 if (iommu->exclusion_start &&
786 iommu->exclusion_start < dma_dom->aperture_size) {
787 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
788 int pages = iommu_num_pages(iommu->exclusion_start,
789 iommu->exclusion_length,
791 dma_ops_reserve_addresses(dma_dom, startpage, pages);
795 * At the last step, build the page tables so we don't need to
796 * allocate page table pages in the dma_ops mapping/unmapping
799 num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512);
800 dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *),
802 if (!dma_dom->pte_pages)
805 l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL);
809 dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde));
811 for (i = 0; i < num_pte_pages; ++i) {
812 dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL);
813 if (!dma_dom->pte_pages[i])
815 address = virt_to_phys(dma_dom->pte_pages[i]);
816 l2_pde[i] = IOMMU_L1_PDE(address);
822 dma_ops_domain_free(dma_dom);
828 * little helper function to check whether a given protection domain is a
831 static bool dma_ops_domain(struct protection_domain *domain)
833 return domain->flags & PD_DMA_OPS_MASK;
837 * Find out the protection domain structure for a given PCI device. This
838 * will give us the pointer to the page table root for example.
840 static struct protection_domain *domain_for_device(u16 devid)
842 struct protection_domain *dom;
845 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
846 dom = amd_iommu_pd_table[devid];
847 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
853 * If a device is not yet associated with a domain, this function does
854 * assigns it visible for the hardware
856 static void attach_device(struct amd_iommu *iommu,
857 struct protection_domain *domain,
861 u64 pte_root = virt_to_phys(domain->pt_root);
863 domain->dev_cnt += 1;
865 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
866 << DEV_ENTRY_MODE_SHIFT;
867 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
869 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
870 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
871 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
872 amd_iommu_dev_table[devid].data[2] = domain->id;
874 amd_iommu_pd_table[devid] = domain;
875 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
877 iommu_queue_inv_dev_entry(iommu, devid);
881 * Removes a device from a protection domain (unlocked)
883 static void __detach_device(struct protection_domain *domain, u16 devid)
887 spin_lock(&domain->lock);
889 /* remove domain from the lookup table */
890 amd_iommu_pd_table[devid] = NULL;
892 /* remove entry from the device table seen by the hardware */
893 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
894 amd_iommu_dev_table[devid].data[1] = 0;
895 amd_iommu_dev_table[devid].data[2] = 0;
897 /* decrease reference counter */
898 domain->dev_cnt -= 1;
901 spin_unlock(&domain->lock);
905 * Removes a device from a protection domain (with devtable_lock held)
907 static void detach_device(struct protection_domain *domain, u16 devid)
911 /* lock device table */
912 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
913 __detach_device(domain, devid);
914 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
917 static int device_change_notifier(struct notifier_block *nb,
918 unsigned long action, void *data)
920 struct device *dev = data;
921 struct pci_dev *pdev = to_pci_dev(dev);
922 u16 devid = calc_devid(pdev->bus->number, pdev->devfn);
923 struct protection_domain *domain;
924 struct dma_ops_domain *dma_domain;
925 struct amd_iommu *iommu;
927 if (devid > amd_iommu_last_bdf)
930 devid = amd_iommu_alias_table[devid];
932 iommu = amd_iommu_rlookup_table[devid];
936 domain = domain_for_device(devid);
938 if (domain && !dma_ops_domain(domain))
939 WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound "
940 "to a non-dma-ops domain\n", dev_name(dev));
943 case BUS_NOTIFY_BOUND_DRIVER:
946 dma_domain = find_protection_domain(devid);
948 dma_domain = iommu->default_dom;
949 attach_device(iommu, &dma_domain->domain, devid);
950 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
951 "device %s\n", dma_domain->domain.id, dev_name(dev));
953 case BUS_NOTIFY_UNBIND_DRIVER:
956 detach_device(domain, devid);
962 iommu_queue_inv_dev_entry(iommu, devid);
963 iommu_completion_wait(iommu);
969 struct notifier_block device_nb = {
970 .notifier_call = device_change_notifier,
973 /*****************************************************************************
975 * The next functions belong to the dma_ops mapping/unmapping code.
977 *****************************************************************************/
980 * This function checks if the driver got a valid device from the caller to
981 * avoid dereferencing invalid pointers.
983 static bool check_device(struct device *dev)
985 if (!dev || !dev->dma_mask)
992 * In this function the list of preallocated protection domains is traversed to
993 * find the domain for a specific device
995 static struct dma_ops_domain *find_protection_domain(u16 devid)
997 struct dma_ops_domain *entry, *ret = NULL;
1000 if (list_empty(&iommu_pd_list))
1003 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1005 list_for_each_entry(entry, &iommu_pd_list, list) {
1006 if (entry->target_dev == devid) {
1012 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1018 * In the dma_ops path we only have the struct device. This function
1019 * finds the corresponding IOMMU, the protection domain and the
1020 * requestor id for a given device.
1021 * If the device is not yet associated with a domain this is also done
1024 static int get_device_resources(struct device *dev,
1025 struct amd_iommu **iommu,
1026 struct protection_domain **domain,
1029 struct dma_ops_domain *dma_dom;
1030 struct pci_dev *pcidev;
1037 if (dev->bus != &pci_bus_type)
1040 pcidev = to_pci_dev(dev);
1041 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1043 /* device not translated by any IOMMU in the system? */
1044 if (_bdf > amd_iommu_last_bdf)
1047 *bdf = amd_iommu_alias_table[_bdf];
1049 *iommu = amd_iommu_rlookup_table[*bdf];
1052 *domain = domain_for_device(*bdf);
1053 if (*domain == NULL) {
1054 dma_dom = find_protection_domain(*bdf);
1056 dma_dom = (*iommu)->default_dom;
1057 *domain = &dma_dom->domain;
1058 attach_device(*iommu, *domain, *bdf);
1059 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
1060 "device ", (*domain)->id);
1061 print_devid(_bdf, 1);
1064 if (domain_for_device(_bdf) == NULL)
1065 attach_device(*iommu, *domain, _bdf);
1071 * This is the generic map function. It maps one 4kb page at paddr to
1072 * the given address in the DMA address space for the domain.
1074 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
1075 struct dma_ops_domain *dom,
1076 unsigned long address,
1082 WARN_ON(address > dom->aperture_size);
1086 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
1087 pte += IOMMU_PTE_L0_INDEX(address);
1089 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1091 if (direction == DMA_TO_DEVICE)
1092 __pte |= IOMMU_PTE_IR;
1093 else if (direction == DMA_FROM_DEVICE)
1094 __pte |= IOMMU_PTE_IW;
1095 else if (direction == DMA_BIDIRECTIONAL)
1096 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1102 return (dma_addr_t)address;
1106 * The generic unmapping function for on page in the DMA address space.
1108 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
1109 struct dma_ops_domain *dom,
1110 unsigned long address)
1114 if (address >= dom->aperture_size)
1117 WARN_ON(address & ~PAGE_MASK || address >= dom->aperture_size);
1119 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
1120 pte += IOMMU_PTE_L0_INDEX(address);
1128 * This function contains common code for mapping of a physically
1129 * contiguous memory region into DMA address space. It is used by all
1130 * mapping functions provided with this IOMMU driver.
1131 * Must be called with the domain lock held.
1133 static dma_addr_t __map_single(struct device *dev,
1134 struct amd_iommu *iommu,
1135 struct dma_ops_domain *dma_dom,
1142 dma_addr_t offset = paddr & ~PAGE_MASK;
1143 dma_addr_t address, start;
1145 unsigned long align_mask = 0;
1148 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1152 align_mask = (1UL << get_order(size)) - 1;
1154 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1156 if (unlikely(address == bad_dma_address))
1160 for (i = 0; i < pages; ++i) {
1161 dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
1167 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1168 iommu_flush_tlb(iommu, dma_dom->domain.id);
1169 dma_dom->need_flush = false;
1170 } else if (unlikely(iommu_has_npcache(iommu)))
1171 iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
1178 * Does the reverse of the __map_single function. Must be called with
1179 * the domain lock held too
1181 static void __unmap_single(struct amd_iommu *iommu,
1182 struct dma_ops_domain *dma_dom,
1183 dma_addr_t dma_addr,
1187 dma_addr_t i, start;
1190 if ((dma_addr == bad_dma_address) ||
1191 (dma_addr + size > dma_dom->aperture_size))
1194 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1195 dma_addr &= PAGE_MASK;
1198 for (i = 0; i < pages; ++i) {
1199 dma_ops_domain_unmap(iommu, dma_dom, start);
1203 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1205 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1206 iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
1207 dma_dom->need_flush = false;
1212 * The exported map_single function for dma_ops.
1214 static dma_addr_t map_single(struct device *dev, phys_addr_t paddr,
1215 size_t size, int dir)
1217 unsigned long flags;
1218 struct amd_iommu *iommu;
1219 struct protection_domain *domain;
1224 if (!check_device(dev))
1225 return bad_dma_address;
1227 dma_mask = *dev->dma_mask;
1229 get_device_resources(dev, &iommu, &domain, &devid);
1231 if (iommu == NULL || domain == NULL)
1232 /* device not handled by any AMD IOMMU */
1233 return (dma_addr_t)paddr;
1235 if (!dma_ops_domain(domain))
1236 return bad_dma_address;
1238 spin_lock_irqsave(&domain->lock, flags);
1239 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false,
1241 if (addr == bad_dma_address)
1244 iommu_completion_wait(iommu);
1247 spin_unlock_irqrestore(&domain->lock, flags);
1253 * The exported unmap_single function for dma_ops.
1255 static void unmap_single(struct device *dev, dma_addr_t dma_addr,
1256 size_t size, int dir)
1258 unsigned long flags;
1259 struct amd_iommu *iommu;
1260 struct protection_domain *domain;
1263 if (!check_device(dev) ||
1264 !get_device_resources(dev, &iommu, &domain, &devid))
1265 /* device not handled by any AMD IOMMU */
1268 if (!dma_ops_domain(domain))
1271 spin_lock_irqsave(&domain->lock, flags);
1273 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
1275 iommu_completion_wait(iommu);
1277 spin_unlock_irqrestore(&domain->lock, flags);
1281 * This is a special map_sg function which is used if we should map a
1282 * device which is not handled by an AMD IOMMU in the system.
1284 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1285 int nelems, int dir)
1287 struct scatterlist *s;
1290 for_each_sg(sglist, s, nelems, i) {
1291 s->dma_address = (dma_addr_t)sg_phys(s);
1292 s->dma_length = s->length;
1299 * The exported map_sg function for dma_ops (handles scatter-gather
1302 static int map_sg(struct device *dev, struct scatterlist *sglist,
1303 int nelems, int dir)
1305 unsigned long flags;
1306 struct amd_iommu *iommu;
1307 struct protection_domain *domain;
1310 struct scatterlist *s;
1312 int mapped_elems = 0;
1315 if (!check_device(dev))
1318 dma_mask = *dev->dma_mask;
1320 get_device_resources(dev, &iommu, &domain, &devid);
1322 if (!iommu || !domain)
1323 return map_sg_no_iommu(dev, sglist, nelems, dir);
1325 if (!dma_ops_domain(domain))
1328 spin_lock_irqsave(&domain->lock, flags);
1330 for_each_sg(sglist, s, nelems, i) {
1333 s->dma_address = __map_single(dev, iommu, domain->priv,
1334 paddr, s->length, dir, false,
1337 if (s->dma_address) {
1338 s->dma_length = s->length;
1344 iommu_completion_wait(iommu);
1347 spin_unlock_irqrestore(&domain->lock, flags);
1349 return mapped_elems;
1351 for_each_sg(sglist, s, mapped_elems, i) {
1353 __unmap_single(iommu, domain->priv, s->dma_address,
1354 s->dma_length, dir);
1355 s->dma_address = s->dma_length = 0;
1364 * The exported map_sg function for dma_ops (handles scatter-gather
1367 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1368 int nelems, int dir)
1370 unsigned long flags;
1371 struct amd_iommu *iommu;
1372 struct protection_domain *domain;
1373 struct scatterlist *s;
1377 if (!check_device(dev) ||
1378 !get_device_resources(dev, &iommu, &domain, &devid))
1381 if (!dma_ops_domain(domain))
1384 spin_lock_irqsave(&domain->lock, flags);
1386 for_each_sg(sglist, s, nelems, i) {
1387 __unmap_single(iommu, domain->priv, s->dma_address,
1388 s->dma_length, dir);
1389 s->dma_address = s->dma_length = 0;
1392 iommu_completion_wait(iommu);
1394 spin_unlock_irqrestore(&domain->lock, flags);
1398 * The exported alloc_coherent function for dma_ops.
1400 static void *alloc_coherent(struct device *dev, size_t size,
1401 dma_addr_t *dma_addr, gfp_t flag)
1403 unsigned long flags;
1405 struct amd_iommu *iommu;
1406 struct protection_domain *domain;
1409 u64 dma_mask = dev->coherent_dma_mask;
1411 if (!check_device(dev))
1414 if (!get_device_resources(dev, &iommu, &domain, &devid))
1415 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
1418 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1422 paddr = virt_to_phys(virt_addr);
1424 if (!iommu || !domain) {
1425 *dma_addr = (dma_addr_t)paddr;
1429 if (!dma_ops_domain(domain))
1433 dma_mask = *dev->dma_mask;
1435 spin_lock_irqsave(&domain->lock, flags);
1437 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1438 size, DMA_BIDIRECTIONAL, true, dma_mask);
1440 if (*dma_addr == bad_dma_address)
1443 iommu_completion_wait(iommu);
1445 spin_unlock_irqrestore(&domain->lock, flags);
1451 free_pages((unsigned long)virt_addr, get_order(size));
1457 * The exported free_coherent function for dma_ops.
1459 static void free_coherent(struct device *dev, size_t size,
1460 void *virt_addr, dma_addr_t dma_addr)
1462 unsigned long flags;
1463 struct amd_iommu *iommu;
1464 struct protection_domain *domain;
1467 if (!check_device(dev))
1470 get_device_resources(dev, &iommu, &domain, &devid);
1472 if (!iommu || !domain)
1475 if (!dma_ops_domain(domain))
1478 spin_lock_irqsave(&domain->lock, flags);
1480 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
1482 iommu_completion_wait(iommu);
1484 spin_unlock_irqrestore(&domain->lock, flags);
1487 free_pages((unsigned long)virt_addr, get_order(size));
1491 * This function is called by the DMA layer to find out if we can handle a
1492 * particular device. It is part of the dma_ops.
1494 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
1497 struct pci_dev *pcidev;
1499 /* No device or no PCI device */
1500 if (!dev || dev->bus != &pci_bus_type)
1503 pcidev = to_pci_dev(dev);
1505 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1507 /* Out of our scope? */
1508 if (bdf > amd_iommu_last_bdf)
1515 * The function for pre-allocating protection domains.
1517 * If the driver core informs the DMA layer if a driver grabs a device
1518 * we don't need to preallocate the protection domains anymore.
1519 * For now we have to.
1521 void prealloc_protection_domains(void)
1523 struct pci_dev *dev = NULL;
1524 struct dma_ops_domain *dma_dom;
1525 struct amd_iommu *iommu;
1526 int order = amd_iommu_aperture_order;
1529 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1530 devid = (dev->bus->number << 8) | dev->devfn;
1531 if (devid > amd_iommu_last_bdf)
1533 devid = amd_iommu_alias_table[devid];
1534 if (domain_for_device(devid))
1536 iommu = amd_iommu_rlookup_table[devid];
1539 dma_dom = dma_ops_domain_alloc(iommu, order);
1542 init_unity_mappings_for_device(dma_dom, devid);
1543 dma_dom->target_dev = devid;
1545 list_add_tail(&dma_dom->list, &iommu_pd_list);
1549 static struct dma_mapping_ops amd_iommu_dma_ops = {
1550 .alloc_coherent = alloc_coherent,
1551 .free_coherent = free_coherent,
1552 .map_single = map_single,
1553 .unmap_single = unmap_single,
1555 .unmap_sg = unmap_sg,
1556 .dma_supported = amd_iommu_dma_supported,
1560 * The function which clues the AMD IOMMU driver into dma_ops.
1562 int __init amd_iommu_init_dma_ops(void)
1564 struct amd_iommu *iommu;
1565 int order = amd_iommu_aperture_order;
1569 * first allocate a default protection domain for every IOMMU we
1570 * found in the system. Devices not assigned to any other
1571 * protection domain will be assigned to the default one.
1573 list_for_each_entry(iommu, &amd_iommu_list, list) {
1574 iommu->default_dom = dma_ops_domain_alloc(iommu, order);
1575 if (iommu->default_dom == NULL)
1577 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
1578 ret = iommu_init_unity_mappings(iommu);
1584 * If device isolation is enabled, pre-allocate the protection
1585 * domains for each device.
1587 if (amd_iommu_isolate)
1588 prealloc_protection_domains();
1592 bad_dma_address = 0;
1593 #ifdef CONFIG_GART_IOMMU
1594 gart_iommu_aperture_disabled = 1;
1595 gart_iommu_aperture = 0;
1598 /* Make the driver finally visible to the drivers */
1599 dma_ops = &amd_iommu_dma_ops;
1601 #ifdef CONFIG_IOMMU_API
1602 register_iommu(&amd_iommu_ops);
1605 bus_register_notifier(&pci_bus_type, &device_nb);
1611 list_for_each_entry(iommu, &amd_iommu_list, list) {
1612 if (iommu->default_dom)
1613 dma_ops_domain_free(iommu->default_dom);
1619 /*****************************************************************************
1621 * The following functions belong to the exported interface of AMD IOMMU
1623 * This interface allows access to lower level functions of the IOMMU
1624 * like protection domain handling and assignement of devices to domains
1625 * which is not possible with the dma_ops interface.
1627 *****************************************************************************/
1629 #ifdef CONFIG_IOMMU_API
1631 static void cleanup_domain(struct protection_domain *domain)
1633 unsigned long flags;
1636 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1638 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1639 if (amd_iommu_pd_table[devid] == domain)
1640 __detach_device(domain, devid);
1642 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1645 static int amd_iommu_domain_init(struct iommu_domain *dom)
1647 struct protection_domain *domain;
1649 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
1653 spin_lock_init(&domain->lock);
1654 domain->mode = PAGE_MODE_3_LEVEL;
1655 domain->id = domain_id_alloc();
1658 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1659 if (!domain->pt_root)
1672 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
1674 struct protection_domain *domain = dom->priv;
1679 if (domain->dev_cnt > 0)
1680 cleanup_domain(domain);
1682 BUG_ON(domain->dev_cnt != 0);
1684 free_pagetable(domain);
1686 domain_id_free(domain->id);
1693 static void amd_iommu_detach_device(struct iommu_domain *dom,
1696 struct protection_domain *domain = dom->priv;
1697 struct amd_iommu *iommu;
1698 struct pci_dev *pdev;
1701 if (dev->bus != &pci_bus_type)
1704 pdev = to_pci_dev(dev);
1706 devid = calc_devid(pdev->bus->number, pdev->devfn);
1709 detach_device(domain, devid);
1711 iommu = amd_iommu_rlookup_table[devid];
1715 iommu_queue_inv_dev_entry(iommu, devid);
1716 iommu_completion_wait(iommu);
1719 static int amd_iommu_attach_device(struct iommu_domain *dom,
1722 struct protection_domain *domain = dom->priv;
1723 struct protection_domain *old_domain;
1724 struct amd_iommu *iommu;
1725 struct pci_dev *pdev;
1728 if (dev->bus != &pci_bus_type)
1731 pdev = to_pci_dev(dev);
1733 devid = calc_devid(pdev->bus->number, pdev->devfn);
1735 if (devid >= amd_iommu_last_bdf ||
1736 devid != amd_iommu_alias_table[devid])
1739 iommu = amd_iommu_rlookup_table[devid];
1743 old_domain = domain_for_device(devid);
1747 attach_device(iommu, domain, devid);
1749 iommu_completion_wait(iommu);
1754 static int amd_iommu_map_range(struct iommu_domain *dom,
1755 unsigned long iova, phys_addr_t paddr,
1756 size_t size, int iommu_prot)
1758 struct protection_domain *domain = dom->priv;
1759 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
1763 if (iommu_prot & IOMMU_READ)
1764 prot |= IOMMU_PROT_IR;
1765 if (iommu_prot & IOMMU_WRITE)
1766 prot |= IOMMU_PROT_IW;
1771 for (i = 0; i < npages; ++i) {
1772 ret = iommu_map_page(domain, iova, paddr, prot);
1783 static void amd_iommu_unmap_range(struct iommu_domain *dom,
1784 unsigned long iova, size_t size)
1787 struct protection_domain *domain = dom->priv;
1788 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
1792 for (i = 0; i < npages; ++i) {
1793 iommu_unmap_page(domain, iova);
1797 iommu_flush_domain(domain->id);
1800 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
1803 struct protection_domain *domain = dom->priv;
1804 unsigned long offset = iova & ~PAGE_MASK;
1808 pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)];
1810 if (!IOMMU_PTE_PRESENT(*pte))
1813 pte = IOMMU_PTE_PAGE(*pte);
1814 pte = &pte[IOMMU_PTE_L1_INDEX(iova)];
1816 if (!IOMMU_PTE_PRESENT(*pte))
1819 pte = IOMMU_PTE_PAGE(*pte);
1820 pte = &pte[IOMMU_PTE_L0_INDEX(iova)];
1822 if (!IOMMU_PTE_PRESENT(*pte))
1825 paddr = *pte & IOMMU_PAGE_MASK;
1831 static struct iommu_ops amd_iommu_ops = {
1832 .domain_init = amd_iommu_domain_init,
1833 .domain_destroy = amd_iommu_domain_destroy,
1834 .attach_dev = amd_iommu_attach_device,
1835 .detach_dev = amd_iommu_detach_device,
1836 .map = amd_iommu_map_range,
1837 .unmap = amd_iommu_unmap_range,
1838 .iova_to_phys = amd_iommu_iova_to_phys,