2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/iommu-helper.h>
27 #include <linux/iommu.h>
28 #include <asm/proto.h>
29 #include <asm/iommu.h>
31 #include <asm/amd_iommu_types.h>
32 #include <asm/amd_iommu.h>
34 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
36 #define EXIT_LOOP_COUNT 10000000
38 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
40 /* A list of preallocated protection domains */
41 static LIST_HEAD(iommu_pd_list);
42 static DEFINE_SPINLOCK(iommu_pd_list_lock);
44 #ifdef CONFIG_IOMMU_API
45 static struct iommu_ops amd_iommu_ops;
49 * general struct to manage commands send to an IOMMU
55 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
56 struct unity_map_entry *e);
57 static struct dma_ops_domain *find_protection_domain(u16 devid);
58 static u64* alloc_pte(struct protection_domain *dom,
59 unsigned long address, u64
60 **pte_page, gfp_t gfp);
61 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
62 unsigned long start_page,
65 #ifdef CONFIG_AMD_IOMMU_STATS
68 * Initialization code for statistics collection
71 DECLARE_STATS_COUNTER(compl_wait);
72 DECLARE_STATS_COUNTER(cnt_map_single);
73 DECLARE_STATS_COUNTER(cnt_unmap_single);
74 DECLARE_STATS_COUNTER(cnt_map_sg);
75 DECLARE_STATS_COUNTER(cnt_unmap_sg);
76 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
77 DECLARE_STATS_COUNTER(cnt_free_coherent);
78 DECLARE_STATS_COUNTER(cross_page);
79 DECLARE_STATS_COUNTER(domain_flush_single);
80 DECLARE_STATS_COUNTER(domain_flush_all);
81 DECLARE_STATS_COUNTER(alloced_io_mem);
82 DECLARE_STATS_COUNTER(total_map_requests);
84 static struct dentry *stats_dir;
85 static struct dentry *de_isolate;
86 static struct dentry *de_fflush;
88 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
90 if (stats_dir == NULL)
93 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
97 static void amd_iommu_stats_init(void)
99 stats_dir = debugfs_create_dir("amd-iommu", NULL);
100 if (stats_dir == NULL)
103 de_isolate = debugfs_create_bool("isolation", 0444, stats_dir,
104 (u32 *)&amd_iommu_isolate);
106 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
107 (u32 *)&amd_iommu_unmap_flush);
109 amd_iommu_stats_add(&compl_wait);
110 amd_iommu_stats_add(&cnt_map_single);
111 amd_iommu_stats_add(&cnt_unmap_single);
112 amd_iommu_stats_add(&cnt_map_sg);
113 amd_iommu_stats_add(&cnt_unmap_sg);
114 amd_iommu_stats_add(&cnt_alloc_coherent);
115 amd_iommu_stats_add(&cnt_free_coherent);
116 amd_iommu_stats_add(&cross_page);
117 amd_iommu_stats_add(&domain_flush_single);
118 amd_iommu_stats_add(&domain_flush_all);
119 amd_iommu_stats_add(&alloced_io_mem);
120 amd_iommu_stats_add(&total_map_requests);
125 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
126 static int iommu_has_npcache(struct amd_iommu *iommu)
128 return iommu->cap & (1UL << IOMMU_CAP_NPCACHE);
131 /****************************************************************************
133 * Interrupt handling functions
135 ****************************************************************************/
137 static void iommu_print_event(void *__evt)
140 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
141 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
142 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
143 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
144 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
146 printk(KERN_ERR "AMD IOMMU: Event logged [");
149 case EVENT_TYPE_ILL_DEV:
150 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
151 "address=0x%016llx flags=0x%04x]\n",
152 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
155 case EVENT_TYPE_IO_FAULT:
156 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
157 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
158 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
159 domid, address, flags);
161 case EVENT_TYPE_DEV_TAB_ERR:
162 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
163 "address=0x%016llx flags=0x%04x]\n",
164 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
167 case EVENT_TYPE_PAGE_TAB_ERR:
168 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
169 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
170 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
171 domid, address, flags);
173 case EVENT_TYPE_ILL_CMD:
174 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
176 case EVENT_TYPE_CMD_HARD_ERR:
177 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
178 "flags=0x%04x]\n", address, flags);
180 case EVENT_TYPE_IOTLB_INV_TO:
181 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
182 "address=0x%016llx]\n",
183 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
186 case EVENT_TYPE_INV_DEV_REQ:
187 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
188 "address=0x%016llx flags=0x%04x]\n",
189 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
193 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
197 static void iommu_poll_events(struct amd_iommu *iommu)
202 spin_lock_irqsave(&iommu->lock, flags);
204 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
205 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
207 while (head != tail) {
208 iommu_print_event(iommu->evt_buf + head);
209 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
212 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
214 spin_unlock_irqrestore(&iommu->lock, flags);
217 irqreturn_t amd_iommu_int_handler(int irq, void *data)
219 struct amd_iommu *iommu;
221 list_for_each_entry(iommu, &amd_iommu_list, list)
222 iommu_poll_events(iommu);
227 /****************************************************************************
229 * IOMMU command queuing functions
231 ****************************************************************************/
234 * Writes the command to the IOMMUs command buffer and informs the
235 * hardware about the new command. Must be called with iommu->lock held.
237 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
242 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
243 target = iommu->cmd_buf + tail;
244 memcpy_toio(target, cmd, sizeof(*cmd));
245 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
246 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
249 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
255 * General queuing function for commands. Takes iommu->lock and calls
256 * __iommu_queue_command().
258 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
263 spin_lock_irqsave(&iommu->lock, flags);
264 ret = __iommu_queue_command(iommu, cmd);
266 iommu->need_sync = true;
267 spin_unlock_irqrestore(&iommu->lock, flags);
273 * This function waits until an IOMMU has completed a completion
276 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
282 INC_STATS_COUNTER(compl_wait);
284 while (!ready && (i < EXIT_LOOP_COUNT)) {
286 /* wait for the bit to become one */
287 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
288 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
291 /* set bit back to zero */
292 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
293 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
295 if (unlikely(i == EXIT_LOOP_COUNT))
296 panic("AMD IOMMU: Completion wait loop failed\n");
300 * This function queues a completion wait command into the command
303 static int __iommu_completion_wait(struct amd_iommu *iommu)
305 struct iommu_cmd cmd;
307 memset(&cmd, 0, sizeof(cmd));
308 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
309 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
311 return __iommu_queue_command(iommu, &cmd);
315 * This function is called whenever we need to ensure that the IOMMU has
316 * completed execution of all commands we sent. It sends a
317 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
318 * us about that by writing a value to a physical address we pass with
321 static int iommu_completion_wait(struct amd_iommu *iommu)
326 spin_lock_irqsave(&iommu->lock, flags);
328 if (!iommu->need_sync)
331 ret = __iommu_completion_wait(iommu);
333 iommu->need_sync = false;
338 __iommu_wait_for_completion(iommu);
341 spin_unlock_irqrestore(&iommu->lock, flags);
347 * Command send function for invalidating a device table entry
349 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
351 struct iommu_cmd cmd;
354 BUG_ON(iommu == NULL);
356 memset(&cmd, 0, sizeof(cmd));
357 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
360 ret = iommu_queue_command(iommu, &cmd);
365 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
366 u16 domid, int pde, int s)
368 memset(cmd, 0, sizeof(*cmd));
369 address &= PAGE_MASK;
370 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
371 cmd->data[1] |= domid;
372 cmd->data[2] = lower_32_bits(address);
373 cmd->data[3] = upper_32_bits(address);
374 if (s) /* size bit - we flush more than one 4kb page */
375 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
376 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
377 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
381 * Generic command send function for invalidaing TLB entries
383 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
384 u64 address, u16 domid, int pde, int s)
386 struct iommu_cmd cmd;
389 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
391 ret = iommu_queue_command(iommu, &cmd);
397 * TLB invalidation function which is called from the mapping functions.
398 * It invalidates a single PTE if the range to flush is within a single
399 * page. Otherwise it flushes the whole TLB of the IOMMU.
401 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
402 u64 address, size_t size)
405 unsigned pages = iommu_num_pages(address, size, PAGE_SIZE);
407 address &= PAGE_MASK;
411 * If we have to flush more than one page, flush all
412 * TLB entries for this domain
414 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
418 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
423 /* Flush the whole IO/TLB for a given protection domain */
424 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
426 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
428 INC_STATS_COUNTER(domain_flush_single);
430 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
434 * This function is used to flush the IO/TLB for a given protection domain
435 * on every IOMMU in the system
437 static void iommu_flush_domain(u16 domid)
440 struct amd_iommu *iommu;
441 struct iommu_cmd cmd;
443 INC_STATS_COUNTER(domain_flush_all);
445 __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
448 list_for_each_entry(iommu, &amd_iommu_list, list) {
449 spin_lock_irqsave(&iommu->lock, flags);
450 __iommu_queue_command(iommu, &cmd);
451 __iommu_completion_wait(iommu);
452 __iommu_wait_for_completion(iommu);
453 spin_unlock_irqrestore(&iommu->lock, flags);
457 /****************************************************************************
459 * The functions below are used the create the page table mappings for
460 * unity mapped regions.
462 ****************************************************************************/
465 * Generic mapping functions. It maps a physical address into a DMA
466 * address space. It allocates the page table pages if necessary.
467 * In the future it can be extended to a generic mapping function
468 * supporting all features of AMD IOMMU page tables like level skipping
469 * and full 64 bit address spaces.
471 static int iommu_map_page(struct protection_domain *dom,
472 unsigned long bus_addr,
473 unsigned long phys_addr,
478 bus_addr = PAGE_ALIGN(bus_addr);
479 phys_addr = PAGE_ALIGN(phys_addr);
481 /* only support 512GB address spaces for now */
482 if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
485 pte = alloc_pte(dom, bus_addr, NULL, GFP_KERNEL);
487 if (IOMMU_PTE_PRESENT(*pte))
490 __pte = phys_addr | IOMMU_PTE_P;
491 if (prot & IOMMU_PROT_IR)
492 __pte |= IOMMU_PTE_IR;
493 if (prot & IOMMU_PROT_IW)
494 __pte |= IOMMU_PTE_IW;
501 static void iommu_unmap_page(struct protection_domain *dom,
502 unsigned long bus_addr)
506 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
508 if (!IOMMU_PTE_PRESENT(*pte))
511 pte = IOMMU_PTE_PAGE(*pte);
512 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
514 if (!IOMMU_PTE_PRESENT(*pte))
517 pte = IOMMU_PTE_PAGE(*pte);
518 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
524 * This function checks if a specific unity mapping entry is needed for
525 * this specific IOMMU.
527 static int iommu_for_unity_map(struct amd_iommu *iommu,
528 struct unity_map_entry *entry)
532 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
533 bdf = amd_iommu_alias_table[i];
534 if (amd_iommu_rlookup_table[bdf] == iommu)
542 * Init the unity mappings for a specific IOMMU in the system
544 * Basically iterates over all unity mapping entries and applies them to
545 * the default domain DMA of that IOMMU if necessary.
547 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
549 struct unity_map_entry *entry;
552 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
553 if (!iommu_for_unity_map(iommu, entry))
555 ret = dma_ops_unity_map(iommu->default_dom, entry);
564 * This function actually applies the mapping to the page table of the
567 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
568 struct unity_map_entry *e)
573 for (addr = e->address_start; addr < e->address_end;
575 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot);
579 * if unity mapping is in aperture range mark the page
580 * as allocated in the aperture
582 if (addr < dma_dom->aperture_size)
583 __set_bit(addr >> PAGE_SHIFT,
584 dma_dom->aperture[0]->bitmap);
591 * Inits the unity mappings required for a specific device
593 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
596 struct unity_map_entry *e;
599 list_for_each_entry(e, &amd_iommu_unity_map, list) {
600 if (!(devid >= e->devid_start && devid <= e->devid_end))
602 ret = dma_ops_unity_map(dma_dom, e);
610 /****************************************************************************
612 * The next functions belong to the address allocator for the dma_ops
613 * interface functions. They work like the allocators in the other IOMMU
614 * drivers. Its basically a bitmap which marks the allocated pages in
615 * the aperture. Maybe it could be enhanced in the future to a more
616 * efficient allocator.
618 ****************************************************************************/
621 * The address allocator core functions.
623 * called with domain->lock held
627 * This function checks if there is a PTE for a given dma address. If
628 * there is one, it returns the pointer to it.
630 static u64* fetch_pte(struct protection_domain *domain,
631 unsigned long address)
635 pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(address)];
637 if (!IOMMU_PTE_PRESENT(*pte))
640 pte = IOMMU_PTE_PAGE(*pte);
641 pte = &pte[IOMMU_PTE_L1_INDEX(address)];
643 if (!IOMMU_PTE_PRESENT(*pte))
646 pte = IOMMU_PTE_PAGE(*pte);
647 pte = &pte[IOMMU_PTE_L0_INDEX(address)];
653 * This function is used to add a new aperture range to an existing
654 * aperture in case of dma_ops domain allocation or address allocation
657 static int alloc_new_range(struct amd_iommu *iommu,
658 struct dma_ops_domain *dma_dom,
659 bool populate, gfp_t gfp)
661 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
664 if (index >= APERTURE_MAX_RANGES)
667 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
668 if (!dma_dom->aperture[index])
671 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
672 if (!dma_dom->aperture[index]->bitmap)
675 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
678 unsigned long address = dma_dom->aperture_size;
679 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
682 for (i = 0; i < num_ptes; ++i) {
683 pte = alloc_pte(&dma_dom->domain, address,
688 dma_dom->aperture[index]->pte_pages[i] = pte_page;
690 address += APERTURE_RANGE_SIZE / 64;
694 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
696 /* Intialize the exclusion range if necessary */
697 if (iommu->exclusion_start &&
698 iommu->exclusion_start >= dma_dom->aperture[index]->offset &&
699 iommu->exclusion_start < dma_dom->aperture_size) {
700 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
701 int pages = iommu_num_pages(iommu->exclusion_start,
702 iommu->exclusion_length,
704 dma_ops_reserve_addresses(dma_dom, startpage, pages);
708 * Check for areas already mapped as present in the new aperture
709 * range and mark those pages as reserved in the allocator. Such
710 * mappings may already exist as a result of requested unity
711 * mappings for devices.
713 for (i = dma_dom->aperture[index]->offset;
714 i < dma_dom->aperture_size;
716 u64 *pte = fetch_pte(&dma_dom->domain, i);
717 if (!pte || !IOMMU_PTE_PRESENT(*pte))
720 dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1);
726 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
728 kfree(dma_dom->aperture[index]);
729 dma_dom->aperture[index] = NULL;
734 static unsigned long dma_ops_area_alloc(struct device *dev,
735 struct dma_ops_domain *dom,
737 unsigned long align_mask,
741 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
742 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
743 int i = start >> APERTURE_RANGE_SHIFT;
744 unsigned long boundary_size;
745 unsigned long address = -1;
748 next_bit >>= PAGE_SHIFT;
750 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
751 PAGE_SIZE) >> PAGE_SHIFT;
753 for (;i < max_index; ++i) {
754 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
756 if (dom->aperture[i]->offset >= dma_mask)
759 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
760 dma_mask >> PAGE_SHIFT);
762 address = iommu_area_alloc(dom->aperture[i]->bitmap,
763 limit, next_bit, pages, 0,
764 boundary_size, align_mask);
766 address = dom->aperture[i]->offset +
767 (address << PAGE_SHIFT);
768 dom->next_address = address + (pages << PAGE_SHIFT);
778 static unsigned long dma_ops_alloc_addresses(struct device *dev,
779 struct dma_ops_domain *dom,
781 unsigned long align_mask,
784 unsigned long address;
786 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
787 dma_mask, dom->next_address);
790 dom->next_address = 0;
791 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
793 dom->need_flush = true;
796 if (unlikely(address == -1))
797 address = bad_dma_address;
799 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
805 * The address free function.
807 * called with domain->lock held
809 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
810 unsigned long address,
813 unsigned i = address >> APERTURE_RANGE_SHIFT;
814 struct aperture_range *range = dom->aperture[i];
816 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
818 if (address >= dom->next_address)
819 dom->need_flush = true;
821 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
823 iommu_area_free(range->bitmap, address, pages);
827 /****************************************************************************
829 * The next functions belong to the domain allocation. A domain is
830 * allocated for every IOMMU as the default domain. If device isolation
831 * is enabled, every device get its own domain. The most important thing
832 * about domains is the page table mapping the DMA address space they
835 ****************************************************************************/
837 static u16 domain_id_alloc(void)
842 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
843 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
845 if (id > 0 && id < MAX_DOMAIN_ID)
846 __set_bit(id, amd_iommu_pd_alloc_bitmap);
849 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
854 static void domain_id_free(int id)
858 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
859 if (id > 0 && id < MAX_DOMAIN_ID)
860 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
861 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
865 * Used to reserve address ranges in the aperture (e.g. for exclusion
868 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
869 unsigned long start_page,
872 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
874 if (start_page + pages > last_page)
875 pages = last_page - start_page;
877 for (i = start_page; i < start_page + pages; ++i) {
878 int index = i / APERTURE_RANGE_PAGES;
879 int page = i % APERTURE_RANGE_PAGES;
880 __set_bit(page, dom->aperture[index]->bitmap);
884 static void free_pagetable(struct protection_domain *domain)
889 p1 = domain->pt_root;
894 for (i = 0; i < 512; ++i) {
895 if (!IOMMU_PTE_PRESENT(p1[i]))
898 p2 = IOMMU_PTE_PAGE(p1[i]);
899 for (j = 0; j < 512; ++j) {
900 if (!IOMMU_PTE_PRESENT(p2[j]))
902 p3 = IOMMU_PTE_PAGE(p2[j]);
903 free_page((unsigned long)p3);
906 free_page((unsigned long)p2);
909 free_page((unsigned long)p1);
911 domain->pt_root = NULL;
915 * Free a domain, only used if something went wrong in the
916 * allocation path and we need to free an already allocated page table
918 static void dma_ops_domain_free(struct dma_ops_domain *dom)
925 free_pagetable(&dom->domain);
927 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
928 if (!dom->aperture[i])
930 free_page((unsigned long)dom->aperture[i]->bitmap);
931 kfree(dom->aperture[i]);
938 * Allocates a new protection domain usable for the dma_ops functions.
939 * It also intializes the page table and the address allocator data
940 * structures required for the dma_ops interface
942 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu)
944 struct dma_ops_domain *dma_dom;
946 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
950 spin_lock_init(&dma_dom->domain.lock);
952 dma_dom->domain.id = domain_id_alloc();
953 if (dma_dom->domain.id == 0)
955 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
956 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
957 dma_dom->domain.flags = PD_DMA_OPS_MASK;
958 dma_dom->domain.priv = dma_dom;
959 if (!dma_dom->domain.pt_root)
962 dma_dom->need_flush = false;
963 dma_dom->target_dev = 0xffff;
965 if (alloc_new_range(iommu, dma_dom, true, GFP_KERNEL))
969 * mark the first page as allocated so we never return 0 as
970 * a valid dma-address. So we can use 0 as error value
972 dma_dom->aperture[0]->bitmap[0] = 1;
973 dma_dom->next_address = 0;
979 dma_ops_domain_free(dma_dom);
985 * little helper function to check whether a given protection domain is a
988 static bool dma_ops_domain(struct protection_domain *domain)
990 return domain->flags & PD_DMA_OPS_MASK;
994 * Find out the protection domain structure for a given PCI device. This
995 * will give us the pointer to the page table root for example.
997 static struct protection_domain *domain_for_device(u16 devid)
999 struct protection_domain *dom;
1000 unsigned long flags;
1002 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
1003 dom = amd_iommu_pd_table[devid];
1004 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1010 * If a device is not yet associated with a domain, this function does
1011 * assigns it visible for the hardware
1013 static void attach_device(struct amd_iommu *iommu,
1014 struct protection_domain *domain,
1017 unsigned long flags;
1018 u64 pte_root = virt_to_phys(domain->pt_root);
1020 domain->dev_cnt += 1;
1022 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1023 << DEV_ENTRY_MODE_SHIFT;
1024 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1026 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1027 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
1028 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
1029 amd_iommu_dev_table[devid].data[2] = domain->id;
1031 amd_iommu_pd_table[devid] = domain;
1032 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1034 iommu_queue_inv_dev_entry(iommu, devid);
1038 * Removes a device from a protection domain (unlocked)
1040 static void __detach_device(struct protection_domain *domain, u16 devid)
1044 spin_lock(&domain->lock);
1046 /* remove domain from the lookup table */
1047 amd_iommu_pd_table[devid] = NULL;
1049 /* remove entry from the device table seen by the hardware */
1050 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1051 amd_iommu_dev_table[devid].data[1] = 0;
1052 amd_iommu_dev_table[devid].data[2] = 0;
1054 /* decrease reference counter */
1055 domain->dev_cnt -= 1;
1058 spin_unlock(&domain->lock);
1062 * Removes a device from a protection domain (with devtable_lock held)
1064 static void detach_device(struct protection_domain *domain, u16 devid)
1066 unsigned long flags;
1068 /* lock device table */
1069 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1070 __detach_device(domain, devid);
1071 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1074 static int device_change_notifier(struct notifier_block *nb,
1075 unsigned long action, void *data)
1077 struct device *dev = data;
1078 struct pci_dev *pdev = to_pci_dev(dev);
1079 u16 devid = calc_devid(pdev->bus->number, pdev->devfn);
1080 struct protection_domain *domain;
1081 struct dma_ops_domain *dma_domain;
1082 struct amd_iommu *iommu;
1083 unsigned long flags;
1085 if (devid > amd_iommu_last_bdf)
1088 devid = amd_iommu_alias_table[devid];
1090 iommu = amd_iommu_rlookup_table[devid];
1094 domain = domain_for_device(devid);
1096 if (domain && !dma_ops_domain(domain))
1097 WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound "
1098 "to a non-dma-ops domain\n", dev_name(dev));
1101 case BUS_NOTIFY_BOUND_DRIVER:
1104 dma_domain = find_protection_domain(devid);
1106 dma_domain = iommu->default_dom;
1107 attach_device(iommu, &dma_domain->domain, devid);
1108 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
1109 "device %s\n", dma_domain->domain.id, dev_name(dev));
1111 case BUS_NOTIFY_UNBIND_DRIVER:
1114 detach_device(domain, devid);
1116 case BUS_NOTIFY_ADD_DEVICE:
1117 /* allocate a protection domain if a device is added */
1118 dma_domain = find_protection_domain(devid);
1121 dma_domain = dma_ops_domain_alloc(iommu);
1124 dma_domain->target_dev = devid;
1126 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1127 list_add_tail(&dma_domain->list, &iommu_pd_list);
1128 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1135 iommu_queue_inv_dev_entry(iommu, devid);
1136 iommu_completion_wait(iommu);
1142 struct notifier_block device_nb = {
1143 .notifier_call = device_change_notifier,
1146 /*****************************************************************************
1148 * The next functions belong to the dma_ops mapping/unmapping code.
1150 *****************************************************************************/
1153 * This function checks if the driver got a valid device from the caller to
1154 * avoid dereferencing invalid pointers.
1156 static bool check_device(struct device *dev)
1158 if (!dev || !dev->dma_mask)
1165 * In this function the list of preallocated protection domains is traversed to
1166 * find the domain for a specific device
1168 static struct dma_ops_domain *find_protection_domain(u16 devid)
1170 struct dma_ops_domain *entry, *ret = NULL;
1171 unsigned long flags;
1173 if (list_empty(&iommu_pd_list))
1176 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1178 list_for_each_entry(entry, &iommu_pd_list, list) {
1179 if (entry->target_dev == devid) {
1185 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1191 * In the dma_ops path we only have the struct device. This function
1192 * finds the corresponding IOMMU, the protection domain and the
1193 * requestor id for a given device.
1194 * If the device is not yet associated with a domain this is also done
1197 static int get_device_resources(struct device *dev,
1198 struct amd_iommu **iommu,
1199 struct protection_domain **domain,
1202 struct dma_ops_domain *dma_dom;
1203 struct pci_dev *pcidev;
1210 if (dev->bus != &pci_bus_type)
1213 pcidev = to_pci_dev(dev);
1214 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1216 /* device not translated by any IOMMU in the system? */
1217 if (_bdf > amd_iommu_last_bdf)
1220 *bdf = amd_iommu_alias_table[_bdf];
1222 *iommu = amd_iommu_rlookup_table[*bdf];
1225 *domain = domain_for_device(*bdf);
1226 if (*domain == NULL) {
1227 dma_dom = find_protection_domain(*bdf);
1229 dma_dom = (*iommu)->default_dom;
1230 *domain = &dma_dom->domain;
1231 attach_device(*iommu, *domain, *bdf);
1232 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
1233 "device %s\n", (*domain)->id, dev_name(dev));
1236 if (domain_for_device(_bdf) == NULL)
1237 attach_device(*iommu, *domain, _bdf);
1243 * If the pte_page is not yet allocated this function is called
1245 static u64* alloc_pte(struct protection_domain *dom,
1246 unsigned long address, u64 **pte_page, gfp_t gfp)
1250 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(address)];
1252 if (!IOMMU_PTE_PRESENT(*pte)) {
1253 page = (u64 *)get_zeroed_page(gfp);
1256 *pte = IOMMU_L2_PDE(virt_to_phys(page));
1259 pte = IOMMU_PTE_PAGE(*pte);
1260 pte = &pte[IOMMU_PTE_L1_INDEX(address)];
1262 if (!IOMMU_PTE_PRESENT(*pte)) {
1263 page = (u64 *)get_zeroed_page(gfp);
1266 *pte = IOMMU_L1_PDE(virt_to_phys(page));
1269 pte = IOMMU_PTE_PAGE(*pte);
1274 pte = &pte[IOMMU_PTE_L0_INDEX(address)];
1280 * This function fetches the PTE for a given address in the aperture
1282 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
1283 unsigned long address)
1285 struct aperture_range *aperture;
1286 u64 *pte, *pte_page;
1288 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1292 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1294 pte = alloc_pte(&dom->domain, address, &pte_page, GFP_ATOMIC);
1295 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
1297 pte += IOMMU_PTE_L0_INDEX(address);
1303 * This is the generic map function. It maps one 4kb page at paddr to
1304 * the given address in the DMA address space for the domain.
1306 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
1307 struct dma_ops_domain *dom,
1308 unsigned long address,
1314 WARN_ON(address > dom->aperture_size);
1318 pte = dma_ops_get_pte(dom, address);
1320 return bad_dma_address;
1322 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1324 if (direction == DMA_TO_DEVICE)
1325 __pte |= IOMMU_PTE_IR;
1326 else if (direction == DMA_FROM_DEVICE)
1327 __pte |= IOMMU_PTE_IW;
1328 else if (direction == DMA_BIDIRECTIONAL)
1329 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1335 return (dma_addr_t)address;
1339 * The generic unmapping function for on page in the DMA address space.
1341 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
1342 struct dma_ops_domain *dom,
1343 unsigned long address)
1345 struct aperture_range *aperture;
1348 if (address >= dom->aperture_size)
1351 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1355 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1359 pte += IOMMU_PTE_L0_INDEX(address);
1367 * This function contains common code for mapping of a physically
1368 * contiguous memory region into DMA address space. It is used by all
1369 * mapping functions provided with this IOMMU driver.
1370 * Must be called with the domain lock held.
1372 static dma_addr_t __map_single(struct device *dev,
1373 struct amd_iommu *iommu,
1374 struct dma_ops_domain *dma_dom,
1381 dma_addr_t offset = paddr & ~PAGE_MASK;
1382 dma_addr_t address, start, ret;
1384 unsigned long align_mask = 0;
1387 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1390 INC_STATS_COUNTER(total_map_requests);
1393 INC_STATS_COUNTER(cross_page);
1396 align_mask = (1UL << get_order(size)) - 1;
1399 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1401 if (unlikely(address == bad_dma_address)) {
1403 * setting next_address here will let the address
1404 * allocator only scan the new allocated range in the
1405 * first run. This is a small optimization.
1407 dma_dom->next_address = dma_dom->aperture_size;
1409 if (alloc_new_range(iommu, dma_dom, false, GFP_ATOMIC))
1413 * aperture was sucessfully enlarged by 128 MB, try
1420 for (i = 0; i < pages; ++i) {
1421 ret = dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
1422 if (ret == bad_dma_address)
1430 ADD_STATS_COUNTER(alloced_io_mem, size);
1432 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1433 iommu_flush_tlb(iommu, dma_dom->domain.id);
1434 dma_dom->need_flush = false;
1435 } else if (unlikely(iommu_has_npcache(iommu)))
1436 iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
1443 for (--i; i >= 0; --i) {
1445 dma_ops_domain_unmap(iommu, dma_dom, start);
1448 dma_ops_free_addresses(dma_dom, address, pages);
1450 return bad_dma_address;
1454 * Does the reverse of the __map_single function. Must be called with
1455 * the domain lock held too
1457 static void __unmap_single(struct amd_iommu *iommu,
1458 struct dma_ops_domain *dma_dom,
1459 dma_addr_t dma_addr,
1463 dma_addr_t i, start;
1466 if ((dma_addr == bad_dma_address) ||
1467 (dma_addr + size > dma_dom->aperture_size))
1470 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1471 dma_addr &= PAGE_MASK;
1474 for (i = 0; i < pages; ++i) {
1475 dma_ops_domain_unmap(iommu, dma_dom, start);
1479 SUB_STATS_COUNTER(alloced_io_mem, size);
1481 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1483 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1484 iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
1485 dma_dom->need_flush = false;
1490 * The exported map_single function for dma_ops.
1492 static dma_addr_t map_page(struct device *dev, struct page *page,
1493 unsigned long offset, size_t size,
1494 enum dma_data_direction dir,
1495 struct dma_attrs *attrs)
1497 unsigned long flags;
1498 struct amd_iommu *iommu;
1499 struct protection_domain *domain;
1503 phys_addr_t paddr = page_to_phys(page) + offset;
1505 INC_STATS_COUNTER(cnt_map_single);
1507 if (!check_device(dev))
1508 return bad_dma_address;
1510 dma_mask = *dev->dma_mask;
1512 get_device_resources(dev, &iommu, &domain, &devid);
1514 if (iommu == NULL || domain == NULL)
1515 /* device not handled by any AMD IOMMU */
1516 return (dma_addr_t)paddr;
1518 if (!dma_ops_domain(domain))
1519 return bad_dma_address;
1521 spin_lock_irqsave(&domain->lock, flags);
1522 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false,
1524 if (addr == bad_dma_address)
1527 iommu_completion_wait(iommu);
1530 spin_unlock_irqrestore(&domain->lock, flags);
1536 * The exported unmap_single function for dma_ops.
1538 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
1539 enum dma_data_direction dir, struct dma_attrs *attrs)
1541 unsigned long flags;
1542 struct amd_iommu *iommu;
1543 struct protection_domain *domain;
1546 INC_STATS_COUNTER(cnt_unmap_single);
1548 if (!check_device(dev) ||
1549 !get_device_resources(dev, &iommu, &domain, &devid))
1550 /* device not handled by any AMD IOMMU */
1553 if (!dma_ops_domain(domain))
1556 spin_lock_irqsave(&domain->lock, flags);
1558 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
1560 iommu_completion_wait(iommu);
1562 spin_unlock_irqrestore(&domain->lock, flags);
1566 * This is a special map_sg function which is used if we should map a
1567 * device which is not handled by an AMD IOMMU in the system.
1569 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1570 int nelems, int dir)
1572 struct scatterlist *s;
1575 for_each_sg(sglist, s, nelems, i) {
1576 s->dma_address = (dma_addr_t)sg_phys(s);
1577 s->dma_length = s->length;
1584 * The exported map_sg function for dma_ops (handles scatter-gather
1587 static int map_sg(struct device *dev, struct scatterlist *sglist,
1588 int nelems, enum dma_data_direction dir,
1589 struct dma_attrs *attrs)
1591 unsigned long flags;
1592 struct amd_iommu *iommu;
1593 struct protection_domain *domain;
1596 struct scatterlist *s;
1598 int mapped_elems = 0;
1601 INC_STATS_COUNTER(cnt_map_sg);
1603 if (!check_device(dev))
1606 dma_mask = *dev->dma_mask;
1608 get_device_resources(dev, &iommu, &domain, &devid);
1610 if (!iommu || !domain)
1611 return map_sg_no_iommu(dev, sglist, nelems, dir);
1613 if (!dma_ops_domain(domain))
1616 spin_lock_irqsave(&domain->lock, flags);
1618 for_each_sg(sglist, s, nelems, i) {
1621 s->dma_address = __map_single(dev, iommu, domain->priv,
1622 paddr, s->length, dir, false,
1625 if (s->dma_address) {
1626 s->dma_length = s->length;
1632 iommu_completion_wait(iommu);
1635 spin_unlock_irqrestore(&domain->lock, flags);
1637 return mapped_elems;
1639 for_each_sg(sglist, s, mapped_elems, i) {
1641 __unmap_single(iommu, domain->priv, s->dma_address,
1642 s->dma_length, dir);
1643 s->dma_address = s->dma_length = 0;
1652 * The exported map_sg function for dma_ops (handles scatter-gather
1655 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1656 int nelems, enum dma_data_direction dir,
1657 struct dma_attrs *attrs)
1659 unsigned long flags;
1660 struct amd_iommu *iommu;
1661 struct protection_domain *domain;
1662 struct scatterlist *s;
1666 INC_STATS_COUNTER(cnt_unmap_sg);
1668 if (!check_device(dev) ||
1669 !get_device_resources(dev, &iommu, &domain, &devid))
1672 if (!dma_ops_domain(domain))
1675 spin_lock_irqsave(&domain->lock, flags);
1677 for_each_sg(sglist, s, nelems, i) {
1678 __unmap_single(iommu, domain->priv, s->dma_address,
1679 s->dma_length, dir);
1680 s->dma_address = s->dma_length = 0;
1683 iommu_completion_wait(iommu);
1685 spin_unlock_irqrestore(&domain->lock, flags);
1689 * The exported alloc_coherent function for dma_ops.
1691 static void *alloc_coherent(struct device *dev, size_t size,
1692 dma_addr_t *dma_addr, gfp_t flag)
1694 unsigned long flags;
1696 struct amd_iommu *iommu;
1697 struct protection_domain *domain;
1700 u64 dma_mask = dev->coherent_dma_mask;
1702 INC_STATS_COUNTER(cnt_alloc_coherent);
1704 if (!check_device(dev))
1707 if (!get_device_resources(dev, &iommu, &domain, &devid))
1708 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
1711 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1715 paddr = virt_to_phys(virt_addr);
1717 if (!iommu || !domain) {
1718 *dma_addr = (dma_addr_t)paddr;
1722 if (!dma_ops_domain(domain))
1726 dma_mask = *dev->dma_mask;
1728 spin_lock_irqsave(&domain->lock, flags);
1730 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1731 size, DMA_BIDIRECTIONAL, true, dma_mask);
1733 if (*dma_addr == bad_dma_address)
1736 iommu_completion_wait(iommu);
1738 spin_unlock_irqrestore(&domain->lock, flags);
1744 free_pages((unsigned long)virt_addr, get_order(size));
1750 * The exported free_coherent function for dma_ops.
1752 static void free_coherent(struct device *dev, size_t size,
1753 void *virt_addr, dma_addr_t dma_addr)
1755 unsigned long flags;
1756 struct amd_iommu *iommu;
1757 struct protection_domain *domain;
1760 INC_STATS_COUNTER(cnt_free_coherent);
1762 if (!check_device(dev))
1765 get_device_resources(dev, &iommu, &domain, &devid);
1767 if (!iommu || !domain)
1770 if (!dma_ops_domain(domain))
1773 spin_lock_irqsave(&domain->lock, flags);
1775 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
1777 iommu_completion_wait(iommu);
1779 spin_unlock_irqrestore(&domain->lock, flags);
1782 free_pages((unsigned long)virt_addr, get_order(size));
1786 * This function is called by the DMA layer to find out if we can handle a
1787 * particular device. It is part of the dma_ops.
1789 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
1792 struct pci_dev *pcidev;
1794 /* No device or no PCI device */
1795 if (!dev || dev->bus != &pci_bus_type)
1798 pcidev = to_pci_dev(dev);
1800 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1802 /* Out of our scope? */
1803 if (bdf > amd_iommu_last_bdf)
1810 * The function for pre-allocating protection domains.
1812 * If the driver core informs the DMA layer if a driver grabs a device
1813 * we don't need to preallocate the protection domains anymore.
1814 * For now we have to.
1816 static void prealloc_protection_domains(void)
1818 struct pci_dev *dev = NULL;
1819 struct dma_ops_domain *dma_dom;
1820 struct amd_iommu *iommu;
1823 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1824 devid = calc_devid(dev->bus->number, dev->devfn);
1825 if (devid > amd_iommu_last_bdf)
1827 devid = amd_iommu_alias_table[devid];
1828 if (domain_for_device(devid))
1830 iommu = amd_iommu_rlookup_table[devid];
1833 dma_dom = dma_ops_domain_alloc(iommu);
1836 init_unity_mappings_for_device(dma_dom, devid);
1837 dma_dom->target_dev = devid;
1839 list_add_tail(&dma_dom->list, &iommu_pd_list);
1843 static struct dma_map_ops amd_iommu_dma_ops = {
1844 .alloc_coherent = alloc_coherent,
1845 .free_coherent = free_coherent,
1846 .map_page = map_page,
1847 .unmap_page = unmap_page,
1849 .unmap_sg = unmap_sg,
1850 .dma_supported = amd_iommu_dma_supported,
1854 * The function which clues the AMD IOMMU driver into dma_ops.
1856 int __init amd_iommu_init_dma_ops(void)
1858 struct amd_iommu *iommu;
1862 * first allocate a default protection domain for every IOMMU we
1863 * found in the system. Devices not assigned to any other
1864 * protection domain will be assigned to the default one.
1866 list_for_each_entry(iommu, &amd_iommu_list, list) {
1867 iommu->default_dom = dma_ops_domain_alloc(iommu);
1868 if (iommu->default_dom == NULL)
1870 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
1871 ret = iommu_init_unity_mappings(iommu);
1877 * If device isolation is enabled, pre-allocate the protection
1878 * domains for each device.
1880 if (amd_iommu_isolate)
1881 prealloc_protection_domains();
1885 bad_dma_address = 0;
1886 #ifdef CONFIG_GART_IOMMU
1887 gart_iommu_aperture_disabled = 1;
1888 gart_iommu_aperture = 0;
1891 /* Make the driver finally visible to the drivers */
1892 dma_ops = &amd_iommu_dma_ops;
1894 register_iommu(&amd_iommu_ops);
1896 bus_register_notifier(&pci_bus_type, &device_nb);
1898 amd_iommu_stats_init();
1904 list_for_each_entry(iommu, &amd_iommu_list, list) {
1905 if (iommu->default_dom)
1906 dma_ops_domain_free(iommu->default_dom);
1912 /*****************************************************************************
1914 * The following functions belong to the exported interface of AMD IOMMU
1916 * This interface allows access to lower level functions of the IOMMU
1917 * like protection domain handling and assignement of devices to domains
1918 * which is not possible with the dma_ops interface.
1920 *****************************************************************************/
1922 static void cleanup_domain(struct protection_domain *domain)
1924 unsigned long flags;
1927 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1929 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1930 if (amd_iommu_pd_table[devid] == domain)
1931 __detach_device(domain, devid);
1933 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1936 static int amd_iommu_domain_init(struct iommu_domain *dom)
1938 struct protection_domain *domain;
1940 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
1944 spin_lock_init(&domain->lock);
1945 domain->mode = PAGE_MODE_3_LEVEL;
1946 domain->id = domain_id_alloc();
1949 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1950 if (!domain->pt_root)
1963 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
1965 struct protection_domain *domain = dom->priv;
1970 if (domain->dev_cnt > 0)
1971 cleanup_domain(domain);
1973 BUG_ON(domain->dev_cnt != 0);
1975 free_pagetable(domain);
1977 domain_id_free(domain->id);
1984 static void amd_iommu_detach_device(struct iommu_domain *dom,
1987 struct protection_domain *domain = dom->priv;
1988 struct amd_iommu *iommu;
1989 struct pci_dev *pdev;
1992 if (dev->bus != &pci_bus_type)
1995 pdev = to_pci_dev(dev);
1997 devid = calc_devid(pdev->bus->number, pdev->devfn);
2000 detach_device(domain, devid);
2002 iommu = amd_iommu_rlookup_table[devid];
2006 iommu_queue_inv_dev_entry(iommu, devid);
2007 iommu_completion_wait(iommu);
2010 static int amd_iommu_attach_device(struct iommu_domain *dom,
2013 struct protection_domain *domain = dom->priv;
2014 struct protection_domain *old_domain;
2015 struct amd_iommu *iommu;
2016 struct pci_dev *pdev;
2019 if (dev->bus != &pci_bus_type)
2022 pdev = to_pci_dev(dev);
2024 devid = calc_devid(pdev->bus->number, pdev->devfn);
2026 if (devid >= amd_iommu_last_bdf ||
2027 devid != amd_iommu_alias_table[devid])
2030 iommu = amd_iommu_rlookup_table[devid];
2034 old_domain = domain_for_device(devid);
2038 attach_device(iommu, domain, devid);
2040 iommu_completion_wait(iommu);
2045 static int amd_iommu_map_range(struct iommu_domain *dom,
2046 unsigned long iova, phys_addr_t paddr,
2047 size_t size, int iommu_prot)
2049 struct protection_domain *domain = dom->priv;
2050 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
2054 if (iommu_prot & IOMMU_READ)
2055 prot |= IOMMU_PROT_IR;
2056 if (iommu_prot & IOMMU_WRITE)
2057 prot |= IOMMU_PROT_IW;
2062 for (i = 0; i < npages; ++i) {
2063 ret = iommu_map_page(domain, iova, paddr, prot);
2074 static void amd_iommu_unmap_range(struct iommu_domain *dom,
2075 unsigned long iova, size_t size)
2078 struct protection_domain *domain = dom->priv;
2079 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
2083 for (i = 0; i < npages; ++i) {
2084 iommu_unmap_page(domain, iova);
2088 iommu_flush_domain(domain->id);
2091 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2094 struct protection_domain *domain = dom->priv;
2095 unsigned long offset = iova & ~PAGE_MASK;
2099 pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)];
2101 if (!IOMMU_PTE_PRESENT(*pte))
2104 pte = IOMMU_PTE_PAGE(*pte);
2105 pte = &pte[IOMMU_PTE_L1_INDEX(iova)];
2107 if (!IOMMU_PTE_PRESENT(*pte))
2110 pte = IOMMU_PTE_PAGE(*pte);
2111 pte = &pte[IOMMU_PTE_L0_INDEX(iova)];
2113 if (!IOMMU_PTE_PRESENT(*pte))
2116 paddr = *pte & IOMMU_PAGE_MASK;
2122 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
2128 static struct iommu_ops amd_iommu_ops = {
2129 .domain_init = amd_iommu_domain_init,
2130 .domain_destroy = amd_iommu_domain_destroy,
2131 .attach_dev = amd_iommu_attach_device,
2132 .detach_dev = amd_iommu_detach_device,
2133 .map = amd_iommu_map_range,
2134 .unmap = amd_iommu_unmap_range,
2135 .iova_to_phys = amd_iommu_iova_to_phys,
2136 .domain_has_cap = amd_iommu_domain_has_cap,