2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/iommu-helper.h>
27 #include <linux/iommu.h>
28 #include <asm/proto.h>
29 #include <asm/iommu.h>
31 #include <asm/amd_iommu_types.h>
32 #include <asm/amd_iommu.h>
34 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
36 #define EXIT_LOOP_COUNT 10000000
38 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
40 /* A list of preallocated protection domains */
41 static LIST_HEAD(iommu_pd_list);
42 static DEFINE_SPINLOCK(iommu_pd_list_lock);
44 #ifdef CONFIG_IOMMU_API
45 static struct iommu_ops amd_iommu_ops;
49 * general struct to manage commands send to an IOMMU
55 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
56 struct unity_map_entry *e);
57 static struct dma_ops_domain *find_protection_domain(u16 devid);
58 static u64* alloc_pte(struct protection_domain *dom,
59 unsigned long address, u64
60 **pte_page, gfp_t gfp);
62 #ifdef CONFIG_AMD_IOMMU_STATS
65 * Initialization code for statistics collection
68 DECLARE_STATS_COUNTER(compl_wait);
69 DECLARE_STATS_COUNTER(cnt_map_single);
70 DECLARE_STATS_COUNTER(cnt_unmap_single);
71 DECLARE_STATS_COUNTER(cnt_map_sg);
72 DECLARE_STATS_COUNTER(cnt_unmap_sg);
73 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
74 DECLARE_STATS_COUNTER(cnt_free_coherent);
75 DECLARE_STATS_COUNTER(cross_page);
76 DECLARE_STATS_COUNTER(domain_flush_single);
77 DECLARE_STATS_COUNTER(domain_flush_all);
78 DECLARE_STATS_COUNTER(alloced_io_mem);
79 DECLARE_STATS_COUNTER(total_map_requests);
81 static struct dentry *stats_dir;
82 static struct dentry *de_isolate;
83 static struct dentry *de_fflush;
85 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
87 if (stats_dir == NULL)
90 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
94 static void amd_iommu_stats_init(void)
96 stats_dir = debugfs_create_dir("amd-iommu", NULL);
97 if (stats_dir == NULL)
100 de_isolate = debugfs_create_bool("isolation", 0444, stats_dir,
101 (u32 *)&amd_iommu_isolate);
103 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
104 (u32 *)&amd_iommu_unmap_flush);
106 amd_iommu_stats_add(&compl_wait);
107 amd_iommu_stats_add(&cnt_map_single);
108 amd_iommu_stats_add(&cnt_unmap_single);
109 amd_iommu_stats_add(&cnt_map_sg);
110 amd_iommu_stats_add(&cnt_unmap_sg);
111 amd_iommu_stats_add(&cnt_alloc_coherent);
112 amd_iommu_stats_add(&cnt_free_coherent);
113 amd_iommu_stats_add(&cross_page);
114 amd_iommu_stats_add(&domain_flush_single);
115 amd_iommu_stats_add(&domain_flush_all);
116 amd_iommu_stats_add(&alloced_io_mem);
117 amd_iommu_stats_add(&total_map_requests);
122 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
123 static int iommu_has_npcache(struct amd_iommu *iommu)
125 return iommu->cap & (1UL << IOMMU_CAP_NPCACHE);
128 /****************************************************************************
130 * Interrupt handling functions
132 ****************************************************************************/
134 static void iommu_print_event(void *__evt)
137 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
138 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
139 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
140 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
141 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
143 printk(KERN_ERR "AMD IOMMU: Event logged [");
146 case EVENT_TYPE_ILL_DEV:
147 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
148 "address=0x%016llx flags=0x%04x]\n",
149 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
152 case EVENT_TYPE_IO_FAULT:
153 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
154 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
155 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
156 domid, address, flags);
158 case EVENT_TYPE_DEV_TAB_ERR:
159 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
160 "address=0x%016llx flags=0x%04x]\n",
161 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
164 case EVENT_TYPE_PAGE_TAB_ERR:
165 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
166 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
167 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
168 domid, address, flags);
170 case EVENT_TYPE_ILL_CMD:
171 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
173 case EVENT_TYPE_CMD_HARD_ERR:
174 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
175 "flags=0x%04x]\n", address, flags);
177 case EVENT_TYPE_IOTLB_INV_TO:
178 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
179 "address=0x%016llx]\n",
180 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
183 case EVENT_TYPE_INV_DEV_REQ:
184 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
185 "address=0x%016llx flags=0x%04x]\n",
186 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
190 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
194 static void iommu_poll_events(struct amd_iommu *iommu)
199 spin_lock_irqsave(&iommu->lock, flags);
201 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
202 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
204 while (head != tail) {
205 iommu_print_event(iommu->evt_buf + head);
206 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
209 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
211 spin_unlock_irqrestore(&iommu->lock, flags);
214 irqreturn_t amd_iommu_int_handler(int irq, void *data)
216 struct amd_iommu *iommu;
218 list_for_each_entry(iommu, &amd_iommu_list, list)
219 iommu_poll_events(iommu);
224 /****************************************************************************
226 * IOMMU command queuing functions
228 ****************************************************************************/
231 * Writes the command to the IOMMUs command buffer and informs the
232 * hardware about the new command. Must be called with iommu->lock held.
234 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
239 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
240 target = iommu->cmd_buf + tail;
241 memcpy_toio(target, cmd, sizeof(*cmd));
242 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
243 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
246 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
252 * General queuing function for commands. Takes iommu->lock and calls
253 * __iommu_queue_command().
255 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
260 spin_lock_irqsave(&iommu->lock, flags);
261 ret = __iommu_queue_command(iommu, cmd);
263 iommu->need_sync = true;
264 spin_unlock_irqrestore(&iommu->lock, flags);
270 * This function waits until an IOMMU has completed a completion
273 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
279 INC_STATS_COUNTER(compl_wait);
281 while (!ready && (i < EXIT_LOOP_COUNT)) {
283 /* wait for the bit to become one */
284 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
285 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
288 /* set bit back to zero */
289 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
290 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
292 if (unlikely(i == EXIT_LOOP_COUNT))
293 panic("AMD IOMMU: Completion wait loop failed\n");
297 * This function queues a completion wait command into the command
300 static int __iommu_completion_wait(struct amd_iommu *iommu)
302 struct iommu_cmd cmd;
304 memset(&cmd, 0, sizeof(cmd));
305 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
306 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
308 return __iommu_queue_command(iommu, &cmd);
312 * This function is called whenever we need to ensure that the IOMMU has
313 * completed execution of all commands we sent. It sends a
314 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
315 * us about that by writing a value to a physical address we pass with
318 static int iommu_completion_wait(struct amd_iommu *iommu)
323 spin_lock_irqsave(&iommu->lock, flags);
325 if (!iommu->need_sync)
328 ret = __iommu_completion_wait(iommu);
330 iommu->need_sync = false;
335 __iommu_wait_for_completion(iommu);
338 spin_unlock_irqrestore(&iommu->lock, flags);
344 * Command send function for invalidating a device table entry
346 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
348 struct iommu_cmd cmd;
351 BUG_ON(iommu == NULL);
353 memset(&cmd, 0, sizeof(cmd));
354 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
357 ret = iommu_queue_command(iommu, &cmd);
362 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
363 u16 domid, int pde, int s)
365 memset(cmd, 0, sizeof(*cmd));
366 address &= PAGE_MASK;
367 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
368 cmd->data[1] |= domid;
369 cmd->data[2] = lower_32_bits(address);
370 cmd->data[3] = upper_32_bits(address);
371 if (s) /* size bit - we flush more than one 4kb page */
372 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
373 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
374 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
378 * Generic command send function for invalidaing TLB entries
380 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
381 u64 address, u16 domid, int pde, int s)
383 struct iommu_cmd cmd;
386 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
388 ret = iommu_queue_command(iommu, &cmd);
394 * TLB invalidation function which is called from the mapping functions.
395 * It invalidates a single PTE if the range to flush is within a single
396 * page. Otherwise it flushes the whole TLB of the IOMMU.
398 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
399 u64 address, size_t size)
402 unsigned pages = iommu_num_pages(address, size, PAGE_SIZE);
404 address &= PAGE_MASK;
408 * If we have to flush more than one page, flush all
409 * TLB entries for this domain
411 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
415 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
420 /* Flush the whole IO/TLB for a given protection domain */
421 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
423 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
425 INC_STATS_COUNTER(domain_flush_single);
427 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
431 * This function is used to flush the IO/TLB for a given protection domain
432 * on every IOMMU in the system
434 static void iommu_flush_domain(u16 domid)
437 struct amd_iommu *iommu;
438 struct iommu_cmd cmd;
440 INC_STATS_COUNTER(domain_flush_all);
442 __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
445 list_for_each_entry(iommu, &amd_iommu_list, list) {
446 spin_lock_irqsave(&iommu->lock, flags);
447 __iommu_queue_command(iommu, &cmd);
448 __iommu_completion_wait(iommu);
449 __iommu_wait_for_completion(iommu);
450 spin_unlock_irqrestore(&iommu->lock, flags);
454 /****************************************************************************
456 * The functions below are used the create the page table mappings for
457 * unity mapped regions.
459 ****************************************************************************/
462 * Generic mapping functions. It maps a physical address into a DMA
463 * address space. It allocates the page table pages if necessary.
464 * In the future it can be extended to a generic mapping function
465 * supporting all features of AMD IOMMU page tables like level skipping
466 * and full 64 bit address spaces.
468 static int iommu_map_page(struct protection_domain *dom,
469 unsigned long bus_addr,
470 unsigned long phys_addr,
475 bus_addr = PAGE_ALIGN(bus_addr);
476 phys_addr = PAGE_ALIGN(phys_addr);
478 /* only support 512GB address spaces for now */
479 if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
482 pte = alloc_pte(dom, bus_addr, NULL, GFP_KERNEL);
484 if (IOMMU_PTE_PRESENT(*pte))
487 __pte = phys_addr | IOMMU_PTE_P;
488 if (prot & IOMMU_PROT_IR)
489 __pte |= IOMMU_PTE_IR;
490 if (prot & IOMMU_PROT_IW)
491 __pte |= IOMMU_PTE_IW;
498 static void iommu_unmap_page(struct protection_domain *dom,
499 unsigned long bus_addr)
503 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
505 if (!IOMMU_PTE_PRESENT(*pte))
508 pte = IOMMU_PTE_PAGE(*pte);
509 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
511 if (!IOMMU_PTE_PRESENT(*pte))
514 pte = IOMMU_PTE_PAGE(*pte);
515 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
521 * This function checks if a specific unity mapping entry is needed for
522 * this specific IOMMU.
524 static int iommu_for_unity_map(struct amd_iommu *iommu,
525 struct unity_map_entry *entry)
529 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
530 bdf = amd_iommu_alias_table[i];
531 if (amd_iommu_rlookup_table[bdf] == iommu)
539 * Init the unity mappings for a specific IOMMU in the system
541 * Basically iterates over all unity mapping entries and applies them to
542 * the default domain DMA of that IOMMU if necessary.
544 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
546 struct unity_map_entry *entry;
549 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
550 if (!iommu_for_unity_map(iommu, entry))
552 ret = dma_ops_unity_map(iommu->default_dom, entry);
561 * This function actually applies the mapping to the page table of the
564 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
565 struct unity_map_entry *e)
570 for (addr = e->address_start; addr < e->address_end;
572 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot);
576 * if unity mapping is in aperture range mark the page
577 * as allocated in the aperture
579 if (addr < dma_dom->aperture_size)
580 __set_bit(addr >> PAGE_SHIFT,
581 dma_dom->aperture[0]->bitmap);
588 * Inits the unity mappings required for a specific device
590 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
593 struct unity_map_entry *e;
596 list_for_each_entry(e, &amd_iommu_unity_map, list) {
597 if (!(devid >= e->devid_start && devid <= e->devid_end))
599 ret = dma_ops_unity_map(dma_dom, e);
607 /****************************************************************************
609 * The next functions belong to the address allocator for the dma_ops
610 * interface functions. They work like the allocators in the other IOMMU
611 * drivers. Its basically a bitmap which marks the allocated pages in
612 * the aperture. Maybe it could be enhanced in the future to a more
613 * efficient allocator.
615 ****************************************************************************/
618 * The address allocator core functions.
620 * called with domain->lock held
623 static unsigned long dma_ops_area_alloc(struct device *dev,
624 struct dma_ops_domain *dom,
626 unsigned long align_mask,
630 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
631 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
632 int i = start >> APERTURE_RANGE_SHIFT;
633 unsigned long boundary_size;
634 unsigned long address = -1;
637 next_bit >>= PAGE_SHIFT;
639 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
640 PAGE_SIZE) >> PAGE_SHIFT;
642 for (;i < max_index; ++i) {
643 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
645 if (dom->aperture[i]->offset >= dma_mask)
648 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
649 dma_mask >> PAGE_SHIFT);
651 address = iommu_area_alloc(dom->aperture[i]->bitmap,
652 limit, next_bit, pages, 0,
653 boundary_size, align_mask);
655 address = dom->aperture[i]->offset +
656 (address << PAGE_SHIFT);
657 dom->next_address = address + (pages << PAGE_SHIFT);
667 static unsigned long dma_ops_alloc_addresses(struct device *dev,
668 struct dma_ops_domain *dom,
670 unsigned long align_mask,
673 unsigned long address;
675 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
676 dma_mask, dom->next_address);
679 dom->next_address = 0;
680 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
682 dom->need_flush = true;
685 if (unlikely(address == -1))
686 address = bad_dma_address;
688 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
694 * The address free function.
696 * called with domain->lock held
698 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
699 unsigned long address,
702 unsigned i = address >> APERTURE_RANGE_SHIFT;
703 struct aperture_range *range = dom->aperture[i];
705 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
707 if (address >= dom->next_address)
708 dom->need_flush = true;
710 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
712 iommu_area_free(range->bitmap, address, pages);
716 /****************************************************************************
718 * The next functions belong to the domain allocation. A domain is
719 * allocated for every IOMMU as the default domain. If device isolation
720 * is enabled, every device get its own domain. The most important thing
721 * about domains is the page table mapping the DMA address space they
724 ****************************************************************************/
726 static u16 domain_id_alloc(void)
731 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
732 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
734 if (id > 0 && id < MAX_DOMAIN_ID)
735 __set_bit(id, amd_iommu_pd_alloc_bitmap);
738 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
743 static void domain_id_free(int id)
747 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
748 if (id > 0 && id < MAX_DOMAIN_ID)
749 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
750 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
754 * Used to reserve address ranges in the aperture (e.g. for exclusion
757 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
758 unsigned long start_page,
761 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
763 if (start_page + pages > last_page)
764 pages = last_page - start_page;
766 for (i = start_page; i < start_page + pages; ++i) {
767 int index = i / APERTURE_RANGE_PAGES;
768 int page = i % APERTURE_RANGE_PAGES;
769 __set_bit(page, dom->aperture[index]->bitmap);
773 static void free_pagetable(struct protection_domain *domain)
778 p1 = domain->pt_root;
783 for (i = 0; i < 512; ++i) {
784 if (!IOMMU_PTE_PRESENT(p1[i]))
787 p2 = IOMMU_PTE_PAGE(p1[i]);
788 for (j = 0; j < 512; ++j) {
789 if (!IOMMU_PTE_PRESENT(p2[j]))
791 p3 = IOMMU_PTE_PAGE(p2[j]);
792 free_page((unsigned long)p3);
795 free_page((unsigned long)p2);
798 free_page((unsigned long)p1);
800 domain->pt_root = NULL;
804 * Free a domain, only used if something went wrong in the
805 * allocation path and we need to free an already allocated page table
807 static void dma_ops_domain_free(struct dma_ops_domain *dom)
814 free_pagetable(&dom->domain);
816 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
817 if (!dom->aperture[i])
819 free_page((unsigned long)dom->aperture[i]->bitmap);
820 kfree(dom->aperture[i]);
827 * Allocates a new protection domain usable for the dma_ops functions.
828 * It also intializes the page table and the address allocator data
829 * structures required for the dma_ops interface
831 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu,
834 struct dma_ops_domain *dma_dom;
835 unsigned i, num_pte_pages;
840 * Currently the DMA aperture must be between 32 MB and 1GB in size
842 if ((order < 25) || (order > 30))
845 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
849 dma_dom->aperture[0] = kzalloc(sizeof(struct aperture_range),
851 if (!dma_dom->aperture[0])
854 spin_lock_init(&dma_dom->domain.lock);
856 dma_dom->domain.id = domain_id_alloc();
857 if (dma_dom->domain.id == 0)
859 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
860 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
861 dma_dom->domain.flags = PD_DMA_OPS_MASK;
862 dma_dom->domain.priv = dma_dom;
863 if (!dma_dom->domain.pt_root)
865 dma_dom->aperture_size = APERTURE_RANGE_SIZE;
866 dma_dom->aperture[0]->bitmap = (void *)get_zeroed_page(GFP_KERNEL);
867 if (!dma_dom->aperture[0]->bitmap)
870 * mark the first page as allocated so we never return 0 as
871 * a valid dma-address. So we can use 0 as error value
873 dma_dom->aperture[0]->bitmap[0] = 1;
874 dma_dom->next_address = 0;
876 dma_dom->need_flush = false;
877 dma_dom->target_dev = 0xffff;
879 /* Intialize the exclusion range if necessary */
880 if (iommu->exclusion_start &&
881 iommu->exclusion_start < dma_dom->aperture_size) {
882 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
883 int pages = iommu_num_pages(iommu->exclusion_start,
884 iommu->exclusion_length,
886 dma_ops_reserve_addresses(dma_dom, startpage, pages);
890 * At the last step, build the page tables so we don't need to
891 * allocate page table pages in the dma_ops mapping/unmapping
892 * path for the first 128MB of dma address space.
894 num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512);
896 l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL);
900 dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde));
902 for (i = 0; i < num_pte_pages; ++i) {
903 u64 **pte_page = &dma_dom->aperture[0]->pte_pages[i];
904 *pte_page = (u64 *)get_zeroed_page(GFP_KERNEL);
907 address = virt_to_phys(*pte_page);
908 l2_pde[i] = IOMMU_L1_PDE(address);
914 dma_ops_domain_free(dma_dom);
920 * little helper function to check whether a given protection domain is a
923 static bool dma_ops_domain(struct protection_domain *domain)
925 return domain->flags & PD_DMA_OPS_MASK;
929 * Find out the protection domain structure for a given PCI device. This
930 * will give us the pointer to the page table root for example.
932 static struct protection_domain *domain_for_device(u16 devid)
934 struct protection_domain *dom;
937 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
938 dom = amd_iommu_pd_table[devid];
939 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
945 * If a device is not yet associated with a domain, this function does
946 * assigns it visible for the hardware
948 static void attach_device(struct amd_iommu *iommu,
949 struct protection_domain *domain,
953 u64 pte_root = virt_to_phys(domain->pt_root);
955 domain->dev_cnt += 1;
957 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
958 << DEV_ENTRY_MODE_SHIFT;
959 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
961 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
962 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
963 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
964 amd_iommu_dev_table[devid].data[2] = domain->id;
966 amd_iommu_pd_table[devid] = domain;
967 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
969 iommu_queue_inv_dev_entry(iommu, devid);
973 * Removes a device from a protection domain (unlocked)
975 static void __detach_device(struct protection_domain *domain, u16 devid)
979 spin_lock(&domain->lock);
981 /* remove domain from the lookup table */
982 amd_iommu_pd_table[devid] = NULL;
984 /* remove entry from the device table seen by the hardware */
985 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
986 amd_iommu_dev_table[devid].data[1] = 0;
987 amd_iommu_dev_table[devid].data[2] = 0;
989 /* decrease reference counter */
990 domain->dev_cnt -= 1;
993 spin_unlock(&domain->lock);
997 * Removes a device from a protection domain (with devtable_lock held)
999 static void detach_device(struct protection_domain *domain, u16 devid)
1001 unsigned long flags;
1003 /* lock device table */
1004 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1005 __detach_device(domain, devid);
1006 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1009 static int device_change_notifier(struct notifier_block *nb,
1010 unsigned long action, void *data)
1012 struct device *dev = data;
1013 struct pci_dev *pdev = to_pci_dev(dev);
1014 u16 devid = calc_devid(pdev->bus->number, pdev->devfn);
1015 struct protection_domain *domain;
1016 struct dma_ops_domain *dma_domain;
1017 struct amd_iommu *iommu;
1018 int order = amd_iommu_aperture_order;
1019 unsigned long flags;
1021 if (devid > amd_iommu_last_bdf)
1024 devid = amd_iommu_alias_table[devid];
1026 iommu = amd_iommu_rlookup_table[devid];
1030 domain = domain_for_device(devid);
1032 if (domain && !dma_ops_domain(domain))
1033 WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound "
1034 "to a non-dma-ops domain\n", dev_name(dev));
1037 case BUS_NOTIFY_BOUND_DRIVER:
1040 dma_domain = find_protection_domain(devid);
1042 dma_domain = iommu->default_dom;
1043 attach_device(iommu, &dma_domain->domain, devid);
1044 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
1045 "device %s\n", dma_domain->domain.id, dev_name(dev));
1047 case BUS_NOTIFY_UNBIND_DRIVER:
1050 detach_device(domain, devid);
1052 case BUS_NOTIFY_ADD_DEVICE:
1053 /* allocate a protection domain if a device is added */
1054 dma_domain = find_protection_domain(devid);
1057 dma_domain = dma_ops_domain_alloc(iommu, order);
1060 dma_domain->target_dev = devid;
1062 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1063 list_add_tail(&dma_domain->list, &iommu_pd_list);
1064 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1071 iommu_queue_inv_dev_entry(iommu, devid);
1072 iommu_completion_wait(iommu);
1078 struct notifier_block device_nb = {
1079 .notifier_call = device_change_notifier,
1082 /*****************************************************************************
1084 * The next functions belong to the dma_ops mapping/unmapping code.
1086 *****************************************************************************/
1089 * This function checks if the driver got a valid device from the caller to
1090 * avoid dereferencing invalid pointers.
1092 static bool check_device(struct device *dev)
1094 if (!dev || !dev->dma_mask)
1101 * In this function the list of preallocated protection domains is traversed to
1102 * find the domain for a specific device
1104 static struct dma_ops_domain *find_protection_domain(u16 devid)
1106 struct dma_ops_domain *entry, *ret = NULL;
1107 unsigned long flags;
1109 if (list_empty(&iommu_pd_list))
1112 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1114 list_for_each_entry(entry, &iommu_pd_list, list) {
1115 if (entry->target_dev == devid) {
1121 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1127 * In the dma_ops path we only have the struct device. This function
1128 * finds the corresponding IOMMU, the protection domain and the
1129 * requestor id for a given device.
1130 * If the device is not yet associated with a domain this is also done
1133 static int get_device_resources(struct device *dev,
1134 struct amd_iommu **iommu,
1135 struct protection_domain **domain,
1138 struct dma_ops_domain *dma_dom;
1139 struct pci_dev *pcidev;
1146 if (dev->bus != &pci_bus_type)
1149 pcidev = to_pci_dev(dev);
1150 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1152 /* device not translated by any IOMMU in the system? */
1153 if (_bdf > amd_iommu_last_bdf)
1156 *bdf = amd_iommu_alias_table[_bdf];
1158 *iommu = amd_iommu_rlookup_table[*bdf];
1161 *domain = domain_for_device(*bdf);
1162 if (*domain == NULL) {
1163 dma_dom = find_protection_domain(*bdf);
1165 dma_dom = (*iommu)->default_dom;
1166 *domain = &dma_dom->domain;
1167 attach_device(*iommu, *domain, *bdf);
1168 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
1169 "device %s\n", (*domain)->id, dev_name(dev));
1172 if (domain_for_device(_bdf) == NULL)
1173 attach_device(*iommu, *domain, _bdf);
1179 * If the pte_page is not yet allocated this function is called
1181 static u64* alloc_pte(struct protection_domain *dom,
1182 unsigned long address, u64 **pte_page, gfp_t gfp)
1186 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(address)];
1188 if (!IOMMU_PTE_PRESENT(*pte)) {
1189 page = (u64 *)get_zeroed_page(gfp);
1192 *pte = IOMMU_L2_PDE(virt_to_phys(page));
1195 pte = IOMMU_PTE_PAGE(*pte);
1196 pte = &pte[IOMMU_PTE_L1_INDEX(address)];
1198 if (!IOMMU_PTE_PRESENT(*pte)) {
1199 page = (u64 *)get_zeroed_page(gfp);
1202 *pte = IOMMU_L1_PDE(virt_to_phys(page));
1205 pte = IOMMU_PTE_PAGE(*pte);
1210 pte = &pte[IOMMU_PTE_L0_INDEX(address)];
1216 * This function fetches the PTE for a given address in the aperture
1218 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
1219 unsigned long address)
1221 struct aperture_range *aperture;
1222 u64 *pte, *pte_page;
1224 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1228 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1230 pte = alloc_pte(&dom->domain, address, &pte_page, GFP_ATOMIC);
1231 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
1233 pte += IOMMU_PTE_L0_INDEX(address);
1239 * This is the generic map function. It maps one 4kb page at paddr to
1240 * the given address in the DMA address space for the domain.
1242 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
1243 struct dma_ops_domain *dom,
1244 unsigned long address,
1250 WARN_ON(address > dom->aperture_size);
1254 pte = dma_ops_get_pte(dom, address);
1256 return bad_dma_address;
1258 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1260 if (direction == DMA_TO_DEVICE)
1261 __pte |= IOMMU_PTE_IR;
1262 else if (direction == DMA_FROM_DEVICE)
1263 __pte |= IOMMU_PTE_IW;
1264 else if (direction == DMA_BIDIRECTIONAL)
1265 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1271 return (dma_addr_t)address;
1275 * The generic unmapping function for on page in the DMA address space.
1277 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
1278 struct dma_ops_domain *dom,
1279 unsigned long address)
1281 struct aperture_range *aperture;
1284 if (address >= dom->aperture_size)
1287 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1291 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1295 pte += IOMMU_PTE_L0_INDEX(address);
1303 * This function contains common code for mapping of a physically
1304 * contiguous memory region into DMA address space. It is used by all
1305 * mapping functions provided with this IOMMU driver.
1306 * Must be called with the domain lock held.
1308 static dma_addr_t __map_single(struct device *dev,
1309 struct amd_iommu *iommu,
1310 struct dma_ops_domain *dma_dom,
1317 dma_addr_t offset = paddr & ~PAGE_MASK;
1318 dma_addr_t address, start, ret;
1320 unsigned long align_mask = 0;
1323 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1326 INC_STATS_COUNTER(total_map_requests);
1329 INC_STATS_COUNTER(cross_page);
1332 align_mask = (1UL << get_order(size)) - 1;
1334 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1336 if (unlikely(address == bad_dma_address))
1340 for (i = 0; i < pages; ++i) {
1341 ret = dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
1342 if (ret == bad_dma_address)
1350 ADD_STATS_COUNTER(alloced_io_mem, size);
1352 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1353 iommu_flush_tlb(iommu, dma_dom->domain.id);
1354 dma_dom->need_flush = false;
1355 } else if (unlikely(iommu_has_npcache(iommu)))
1356 iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
1363 for (--i; i >= 0; --i) {
1365 dma_ops_domain_unmap(iommu, dma_dom, start);
1368 dma_ops_free_addresses(dma_dom, address, pages);
1370 return bad_dma_address;
1374 * Does the reverse of the __map_single function. Must be called with
1375 * the domain lock held too
1377 static void __unmap_single(struct amd_iommu *iommu,
1378 struct dma_ops_domain *dma_dom,
1379 dma_addr_t dma_addr,
1383 dma_addr_t i, start;
1386 if ((dma_addr == bad_dma_address) ||
1387 (dma_addr + size > dma_dom->aperture_size))
1390 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1391 dma_addr &= PAGE_MASK;
1394 for (i = 0; i < pages; ++i) {
1395 dma_ops_domain_unmap(iommu, dma_dom, start);
1399 SUB_STATS_COUNTER(alloced_io_mem, size);
1401 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1403 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1404 iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
1405 dma_dom->need_flush = false;
1410 * The exported map_single function for dma_ops.
1412 static dma_addr_t map_page(struct device *dev, struct page *page,
1413 unsigned long offset, size_t size,
1414 enum dma_data_direction dir,
1415 struct dma_attrs *attrs)
1417 unsigned long flags;
1418 struct amd_iommu *iommu;
1419 struct protection_domain *domain;
1423 phys_addr_t paddr = page_to_phys(page) + offset;
1425 INC_STATS_COUNTER(cnt_map_single);
1427 if (!check_device(dev))
1428 return bad_dma_address;
1430 dma_mask = *dev->dma_mask;
1432 get_device_resources(dev, &iommu, &domain, &devid);
1434 if (iommu == NULL || domain == NULL)
1435 /* device not handled by any AMD IOMMU */
1436 return (dma_addr_t)paddr;
1438 if (!dma_ops_domain(domain))
1439 return bad_dma_address;
1441 spin_lock_irqsave(&domain->lock, flags);
1442 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false,
1444 if (addr == bad_dma_address)
1447 iommu_completion_wait(iommu);
1450 spin_unlock_irqrestore(&domain->lock, flags);
1456 * The exported unmap_single function for dma_ops.
1458 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
1459 enum dma_data_direction dir, struct dma_attrs *attrs)
1461 unsigned long flags;
1462 struct amd_iommu *iommu;
1463 struct protection_domain *domain;
1466 INC_STATS_COUNTER(cnt_unmap_single);
1468 if (!check_device(dev) ||
1469 !get_device_resources(dev, &iommu, &domain, &devid))
1470 /* device not handled by any AMD IOMMU */
1473 if (!dma_ops_domain(domain))
1476 spin_lock_irqsave(&domain->lock, flags);
1478 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
1480 iommu_completion_wait(iommu);
1482 spin_unlock_irqrestore(&domain->lock, flags);
1486 * This is a special map_sg function which is used if we should map a
1487 * device which is not handled by an AMD IOMMU in the system.
1489 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1490 int nelems, int dir)
1492 struct scatterlist *s;
1495 for_each_sg(sglist, s, nelems, i) {
1496 s->dma_address = (dma_addr_t)sg_phys(s);
1497 s->dma_length = s->length;
1504 * The exported map_sg function for dma_ops (handles scatter-gather
1507 static int map_sg(struct device *dev, struct scatterlist *sglist,
1508 int nelems, enum dma_data_direction dir,
1509 struct dma_attrs *attrs)
1511 unsigned long flags;
1512 struct amd_iommu *iommu;
1513 struct protection_domain *domain;
1516 struct scatterlist *s;
1518 int mapped_elems = 0;
1521 INC_STATS_COUNTER(cnt_map_sg);
1523 if (!check_device(dev))
1526 dma_mask = *dev->dma_mask;
1528 get_device_resources(dev, &iommu, &domain, &devid);
1530 if (!iommu || !domain)
1531 return map_sg_no_iommu(dev, sglist, nelems, dir);
1533 if (!dma_ops_domain(domain))
1536 spin_lock_irqsave(&domain->lock, flags);
1538 for_each_sg(sglist, s, nelems, i) {
1541 s->dma_address = __map_single(dev, iommu, domain->priv,
1542 paddr, s->length, dir, false,
1545 if (s->dma_address) {
1546 s->dma_length = s->length;
1552 iommu_completion_wait(iommu);
1555 spin_unlock_irqrestore(&domain->lock, flags);
1557 return mapped_elems;
1559 for_each_sg(sglist, s, mapped_elems, i) {
1561 __unmap_single(iommu, domain->priv, s->dma_address,
1562 s->dma_length, dir);
1563 s->dma_address = s->dma_length = 0;
1572 * The exported map_sg function for dma_ops (handles scatter-gather
1575 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1576 int nelems, enum dma_data_direction dir,
1577 struct dma_attrs *attrs)
1579 unsigned long flags;
1580 struct amd_iommu *iommu;
1581 struct protection_domain *domain;
1582 struct scatterlist *s;
1586 INC_STATS_COUNTER(cnt_unmap_sg);
1588 if (!check_device(dev) ||
1589 !get_device_resources(dev, &iommu, &domain, &devid))
1592 if (!dma_ops_domain(domain))
1595 spin_lock_irqsave(&domain->lock, flags);
1597 for_each_sg(sglist, s, nelems, i) {
1598 __unmap_single(iommu, domain->priv, s->dma_address,
1599 s->dma_length, dir);
1600 s->dma_address = s->dma_length = 0;
1603 iommu_completion_wait(iommu);
1605 spin_unlock_irqrestore(&domain->lock, flags);
1609 * The exported alloc_coherent function for dma_ops.
1611 static void *alloc_coherent(struct device *dev, size_t size,
1612 dma_addr_t *dma_addr, gfp_t flag)
1614 unsigned long flags;
1616 struct amd_iommu *iommu;
1617 struct protection_domain *domain;
1620 u64 dma_mask = dev->coherent_dma_mask;
1622 INC_STATS_COUNTER(cnt_alloc_coherent);
1624 if (!check_device(dev))
1627 if (!get_device_resources(dev, &iommu, &domain, &devid))
1628 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
1631 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1635 paddr = virt_to_phys(virt_addr);
1637 if (!iommu || !domain) {
1638 *dma_addr = (dma_addr_t)paddr;
1642 if (!dma_ops_domain(domain))
1646 dma_mask = *dev->dma_mask;
1648 spin_lock_irqsave(&domain->lock, flags);
1650 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1651 size, DMA_BIDIRECTIONAL, true, dma_mask);
1653 if (*dma_addr == bad_dma_address)
1656 iommu_completion_wait(iommu);
1658 spin_unlock_irqrestore(&domain->lock, flags);
1664 free_pages((unsigned long)virt_addr, get_order(size));
1670 * The exported free_coherent function for dma_ops.
1672 static void free_coherent(struct device *dev, size_t size,
1673 void *virt_addr, dma_addr_t dma_addr)
1675 unsigned long flags;
1676 struct amd_iommu *iommu;
1677 struct protection_domain *domain;
1680 INC_STATS_COUNTER(cnt_free_coherent);
1682 if (!check_device(dev))
1685 get_device_resources(dev, &iommu, &domain, &devid);
1687 if (!iommu || !domain)
1690 if (!dma_ops_domain(domain))
1693 spin_lock_irqsave(&domain->lock, flags);
1695 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
1697 iommu_completion_wait(iommu);
1699 spin_unlock_irqrestore(&domain->lock, flags);
1702 free_pages((unsigned long)virt_addr, get_order(size));
1706 * This function is called by the DMA layer to find out if we can handle a
1707 * particular device. It is part of the dma_ops.
1709 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
1712 struct pci_dev *pcidev;
1714 /* No device or no PCI device */
1715 if (!dev || dev->bus != &pci_bus_type)
1718 pcidev = to_pci_dev(dev);
1720 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1722 /* Out of our scope? */
1723 if (bdf > amd_iommu_last_bdf)
1730 * The function for pre-allocating protection domains.
1732 * If the driver core informs the DMA layer if a driver grabs a device
1733 * we don't need to preallocate the protection domains anymore.
1734 * For now we have to.
1736 static void prealloc_protection_domains(void)
1738 struct pci_dev *dev = NULL;
1739 struct dma_ops_domain *dma_dom;
1740 struct amd_iommu *iommu;
1741 int order = amd_iommu_aperture_order;
1744 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1745 devid = calc_devid(dev->bus->number, dev->devfn);
1746 if (devid > amd_iommu_last_bdf)
1748 devid = amd_iommu_alias_table[devid];
1749 if (domain_for_device(devid))
1751 iommu = amd_iommu_rlookup_table[devid];
1754 dma_dom = dma_ops_domain_alloc(iommu, order);
1757 init_unity_mappings_for_device(dma_dom, devid);
1758 dma_dom->target_dev = devid;
1760 list_add_tail(&dma_dom->list, &iommu_pd_list);
1764 static struct dma_map_ops amd_iommu_dma_ops = {
1765 .alloc_coherent = alloc_coherent,
1766 .free_coherent = free_coherent,
1767 .map_page = map_page,
1768 .unmap_page = unmap_page,
1770 .unmap_sg = unmap_sg,
1771 .dma_supported = amd_iommu_dma_supported,
1775 * The function which clues the AMD IOMMU driver into dma_ops.
1777 int __init amd_iommu_init_dma_ops(void)
1779 struct amd_iommu *iommu;
1780 int order = amd_iommu_aperture_order;
1784 * first allocate a default protection domain for every IOMMU we
1785 * found in the system. Devices not assigned to any other
1786 * protection domain will be assigned to the default one.
1788 list_for_each_entry(iommu, &amd_iommu_list, list) {
1789 iommu->default_dom = dma_ops_domain_alloc(iommu, order);
1790 if (iommu->default_dom == NULL)
1792 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
1793 ret = iommu_init_unity_mappings(iommu);
1799 * If device isolation is enabled, pre-allocate the protection
1800 * domains for each device.
1802 if (amd_iommu_isolate)
1803 prealloc_protection_domains();
1807 bad_dma_address = 0;
1808 #ifdef CONFIG_GART_IOMMU
1809 gart_iommu_aperture_disabled = 1;
1810 gart_iommu_aperture = 0;
1813 /* Make the driver finally visible to the drivers */
1814 dma_ops = &amd_iommu_dma_ops;
1816 register_iommu(&amd_iommu_ops);
1818 bus_register_notifier(&pci_bus_type, &device_nb);
1820 amd_iommu_stats_init();
1826 list_for_each_entry(iommu, &amd_iommu_list, list) {
1827 if (iommu->default_dom)
1828 dma_ops_domain_free(iommu->default_dom);
1834 /*****************************************************************************
1836 * The following functions belong to the exported interface of AMD IOMMU
1838 * This interface allows access to lower level functions of the IOMMU
1839 * like protection domain handling and assignement of devices to domains
1840 * which is not possible with the dma_ops interface.
1842 *****************************************************************************/
1844 static void cleanup_domain(struct protection_domain *domain)
1846 unsigned long flags;
1849 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1851 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1852 if (amd_iommu_pd_table[devid] == domain)
1853 __detach_device(domain, devid);
1855 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1858 static int amd_iommu_domain_init(struct iommu_domain *dom)
1860 struct protection_domain *domain;
1862 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
1866 spin_lock_init(&domain->lock);
1867 domain->mode = PAGE_MODE_3_LEVEL;
1868 domain->id = domain_id_alloc();
1871 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1872 if (!domain->pt_root)
1885 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
1887 struct protection_domain *domain = dom->priv;
1892 if (domain->dev_cnt > 0)
1893 cleanup_domain(domain);
1895 BUG_ON(domain->dev_cnt != 0);
1897 free_pagetable(domain);
1899 domain_id_free(domain->id);
1906 static void amd_iommu_detach_device(struct iommu_domain *dom,
1909 struct protection_domain *domain = dom->priv;
1910 struct amd_iommu *iommu;
1911 struct pci_dev *pdev;
1914 if (dev->bus != &pci_bus_type)
1917 pdev = to_pci_dev(dev);
1919 devid = calc_devid(pdev->bus->number, pdev->devfn);
1922 detach_device(domain, devid);
1924 iommu = amd_iommu_rlookup_table[devid];
1928 iommu_queue_inv_dev_entry(iommu, devid);
1929 iommu_completion_wait(iommu);
1932 static int amd_iommu_attach_device(struct iommu_domain *dom,
1935 struct protection_domain *domain = dom->priv;
1936 struct protection_domain *old_domain;
1937 struct amd_iommu *iommu;
1938 struct pci_dev *pdev;
1941 if (dev->bus != &pci_bus_type)
1944 pdev = to_pci_dev(dev);
1946 devid = calc_devid(pdev->bus->number, pdev->devfn);
1948 if (devid >= amd_iommu_last_bdf ||
1949 devid != amd_iommu_alias_table[devid])
1952 iommu = amd_iommu_rlookup_table[devid];
1956 old_domain = domain_for_device(devid);
1960 attach_device(iommu, domain, devid);
1962 iommu_completion_wait(iommu);
1967 static int amd_iommu_map_range(struct iommu_domain *dom,
1968 unsigned long iova, phys_addr_t paddr,
1969 size_t size, int iommu_prot)
1971 struct protection_domain *domain = dom->priv;
1972 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
1976 if (iommu_prot & IOMMU_READ)
1977 prot |= IOMMU_PROT_IR;
1978 if (iommu_prot & IOMMU_WRITE)
1979 prot |= IOMMU_PROT_IW;
1984 for (i = 0; i < npages; ++i) {
1985 ret = iommu_map_page(domain, iova, paddr, prot);
1996 static void amd_iommu_unmap_range(struct iommu_domain *dom,
1997 unsigned long iova, size_t size)
2000 struct protection_domain *domain = dom->priv;
2001 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
2005 for (i = 0; i < npages; ++i) {
2006 iommu_unmap_page(domain, iova);
2010 iommu_flush_domain(domain->id);
2013 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2016 struct protection_domain *domain = dom->priv;
2017 unsigned long offset = iova & ~PAGE_MASK;
2021 pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)];
2023 if (!IOMMU_PTE_PRESENT(*pte))
2026 pte = IOMMU_PTE_PAGE(*pte);
2027 pte = &pte[IOMMU_PTE_L1_INDEX(iova)];
2029 if (!IOMMU_PTE_PRESENT(*pte))
2032 pte = IOMMU_PTE_PAGE(*pte);
2033 pte = &pte[IOMMU_PTE_L0_INDEX(iova)];
2035 if (!IOMMU_PTE_PRESENT(*pte))
2038 paddr = *pte & IOMMU_PAGE_MASK;
2044 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
2050 static struct iommu_ops amd_iommu_ops = {
2051 .domain_init = amd_iommu_domain_init,
2052 .domain_destroy = amd_iommu_domain_destroy,
2053 .attach_dev = amd_iommu_attach_device,
2054 .detach_dev = amd_iommu_detach_device,
2055 .map = amd_iommu_map_range,
2056 .unmap = amd_iommu_unmap_range,
2057 .iova_to_phys = amd_iommu_iova_to_phys,
2058 .domain_has_cap = amd_iommu_domain_has_cap,