2 * Copyright (C) 2007-2009 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/iommu-helper.h>
27 #include <linux/iommu.h>
28 #include <asm/proto.h>
29 #include <asm/iommu.h>
31 #include <asm/amd_iommu_proto.h>
32 #include <asm/amd_iommu_types.h>
33 #include <asm/amd_iommu.h>
35 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
37 #define EXIT_LOOP_COUNT 10000000
39 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
41 /* A list of preallocated protection domains */
42 static LIST_HEAD(iommu_pd_list);
43 static DEFINE_SPINLOCK(iommu_pd_list_lock);
46 * Domain for untranslated devices - only allocated
47 * if iommu=pt passed on kernel cmd line.
49 static struct protection_domain *pt_domain;
51 static struct iommu_ops amd_iommu_ops;
54 * general struct to manage commands send to an IOMMU
60 static void reset_iommu_command_buffer(struct amd_iommu *iommu);
61 static void update_domain(struct protection_domain *domain);
63 /****************************************************************************
67 ****************************************************************************/
69 static inline u16 get_device_id(struct device *dev)
71 struct pci_dev *pdev = to_pci_dev(dev);
73 return calc_devid(pdev->bus->number, pdev->devfn);
76 static struct iommu_dev_data *get_dev_data(struct device *dev)
78 return dev->archdata.iommu;
82 * In this function the list of preallocated protection domains is traversed to
83 * find the domain for a specific device
85 static struct dma_ops_domain *find_protection_domain(u16 devid)
87 struct dma_ops_domain *entry, *ret = NULL;
89 u16 alias = amd_iommu_alias_table[devid];
91 if (list_empty(&iommu_pd_list))
94 spin_lock_irqsave(&iommu_pd_list_lock, flags);
96 list_for_each_entry(entry, &iommu_pd_list, list) {
97 if (entry->target_dev == devid ||
98 entry->target_dev == alias) {
104 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
110 * This function checks if the driver got a valid device from the caller to
111 * avoid dereferencing invalid pointers.
113 static bool check_device(struct device *dev)
117 if (!dev || !dev->dma_mask)
120 /* No device or no PCI device */
121 if (!dev || dev->bus != &pci_bus_type)
124 devid = get_device_id(dev);
126 /* Out of our scope? */
127 if (devid > amd_iommu_last_bdf)
130 if (amd_iommu_rlookup_table[devid] == NULL)
136 static int iommu_init_device(struct device *dev)
138 struct iommu_dev_data *dev_data;
139 struct pci_dev *pdev;
142 if (dev->archdata.iommu)
145 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
151 devid = get_device_id(dev);
152 alias = amd_iommu_alias_table[devid];
153 pdev = pci_get_bus_and_slot(PCI_BUS(alias), alias & 0xff);
155 dev_data->alias = &pdev->dev;
157 atomic_set(&dev_data->bind, 0);
159 dev->archdata.iommu = dev_data;
165 static void iommu_uninit_device(struct device *dev)
167 kfree(dev->archdata.iommu);
169 #ifdef CONFIG_AMD_IOMMU_STATS
172 * Initialization code for statistics collection
175 DECLARE_STATS_COUNTER(compl_wait);
176 DECLARE_STATS_COUNTER(cnt_map_single);
177 DECLARE_STATS_COUNTER(cnt_unmap_single);
178 DECLARE_STATS_COUNTER(cnt_map_sg);
179 DECLARE_STATS_COUNTER(cnt_unmap_sg);
180 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
181 DECLARE_STATS_COUNTER(cnt_free_coherent);
182 DECLARE_STATS_COUNTER(cross_page);
183 DECLARE_STATS_COUNTER(domain_flush_single);
184 DECLARE_STATS_COUNTER(domain_flush_all);
185 DECLARE_STATS_COUNTER(alloced_io_mem);
186 DECLARE_STATS_COUNTER(total_map_requests);
188 static struct dentry *stats_dir;
189 static struct dentry *de_fflush;
191 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
193 if (stats_dir == NULL)
196 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
200 static void amd_iommu_stats_init(void)
202 stats_dir = debugfs_create_dir("amd-iommu", NULL);
203 if (stats_dir == NULL)
206 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
207 (u32 *)&amd_iommu_unmap_flush);
209 amd_iommu_stats_add(&compl_wait);
210 amd_iommu_stats_add(&cnt_map_single);
211 amd_iommu_stats_add(&cnt_unmap_single);
212 amd_iommu_stats_add(&cnt_map_sg);
213 amd_iommu_stats_add(&cnt_unmap_sg);
214 amd_iommu_stats_add(&cnt_alloc_coherent);
215 amd_iommu_stats_add(&cnt_free_coherent);
216 amd_iommu_stats_add(&cross_page);
217 amd_iommu_stats_add(&domain_flush_single);
218 amd_iommu_stats_add(&domain_flush_all);
219 amd_iommu_stats_add(&alloced_io_mem);
220 amd_iommu_stats_add(&total_map_requests);
225 /****************************************************************************
227 * Interrupt handling functions
229 ****************************************************************************/
231 static void dump_dte_entry(u16 devid)
235 for (i = 0; i < 8; ++i)
236 pr_err("AMD-Vi: DTE[%d]: %08x\n", i,
237 amd_iommu_dev_table[devid].data[i]);
240 static void dump_command(unsigned long phys_addr)
242 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
245 for (i = 0; i < 4; ++i)
246 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
249 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
252 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
253 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
254 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
255 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
256 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
258 printk(KERN_ERR "AMD-Vi: Event logged [");
261 case EVENT_TYPE_ILL_DEV:
262 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
263 "address=0x%016llx flags=0x%04x]\n",
264 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
266 dump_dte_entry(devid);
268 case EVENT_TYPE_IO_FAULT:
269 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
270 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
271 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
272 domid, address, flags);
274 case EVENT_TYPE_DEV_TAB_ERR:
275 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
276 "address=0x%016llx flags=0x%04x]\n",
277 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
280 case EVENT_TYPE_PAGE_TAB_ERR:
281 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
282 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
283 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
284 domid, address, flags);
286 case EVENT_TYPE_ILL_CMD:
287 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
288 iommu->reset_in_progress = true;
289 reset_iommu_command_buffer(iommu);
290 dump_command(address);
292 case EVENT_TYPE_CMD_HARD_ERR:
293 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
294 "flags=0x%04x]\n", address, flags);
296 case EVENT_TYPE_IOTLB_INV_TO:
297 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
298 "address=0x%016llx]\n",
299 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
302 case EVENT_TYPE_INV_DEV_REQ:
303 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
304 "address=0x%016llx flags=0x%04x]\n",
305 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
309 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
313 static void iommu_poll_events(struct amd_iommu *iommu)
318 spin_lock_irqsave(&iommu->lock, flags);
320 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
321 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
323 while (head != tail) {
324 iommu_print_event(iommu, iommu->evt_buf + head);
325 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
328 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
330 spin_unlock_irqrestore(&iommu->lock, flags);
333 irqreturn_t amd_iommu_int_handler(int irq, void *data)
335 struct amd_iommu *iommu;
337 for_each_iommu(iommu)
338 iommu_poll_events(iommu);
343 /****************************************************************************
345 * IOMMU command queuing functions
347 ****************************************************************************/
350 * Writes the command to the IOMMUs command buffer and informs the
351 * hardware about the new command. Must be called with iommu->lock held.
353 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
358 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
359 target = iommu->cmd_buf + tail;
360 memcpy_toio(target, cmd, sizeof(*cmd));
361 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
362 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
365 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
371 * General queuing function for commands. Takes iommu->lock and calls
372 * __iommu_queue_command().
374 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
379 spin_lock_irqsave(&iommu->lock, flags);
380 ret = __iommu_queue_command(iommu, cmd);
382 iommu->need_sync = true;
383 spin_unlock_irqrestore(&iommu->lock, flags);
389 * This function waits until an IOMMU has completed a completion
392 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
398 INC_STATS_COUNTER(compl_wait);
400 while (!ready && (i < EXIT_LOOP_COUNT)) {
402 /* wait for the bit to become one */
403 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
404 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
407 /* set bit back to zero */
408 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
409 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
411 if (unlikely(i == EXIT_LOOP_COUNT))
412 iommu->reset_in_progress = true;
416 * This function queues a completion wait command into the command
419 static int __iommu_completion_wait(struct amd_iommu *iommu)
421 struct iommu_cmd cmd;
423 memset(&cmd, 0, sizeof(cmd));
424 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
425 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
427 return __iommu_queue_command(iommu, &cmd);
431 * This function is called whenever we need to ensure that the IOMMU has
432 * completed execution of all commands we sent. It sends a
433 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
434 * us about that by writing a value to a physical address we pass with
437 static int iommu_completion_wait(struct amd_iommu *iommu)
442 spin_lock_irqsave(&iommu->lock, flags);
444 if (!iommu->need_sync)
447 ret = __iommu_completion_wait(iommu);
449 iommu->need_sync = false;
454 __iommu_wait_for_completion(iommu);
457 spin_unlock_irqrestore(&iommu->lock, flags);
459 if (iommu->reset_in_progress)
460 reset_iommu_command_buffer(iommu);
465 static void iommu_flush_complete(struct protection_domain *domain)
469 for (i = 0; i < amd_iommus_present; ++i) {
470 if (!domain->dev_iommu[i])
474 * Devices of this domain are behind this IOMMU
475 * We need to wait for completion of all commands.
477 iommu_completion_wait(amd_iommus[i]);
482 * Command send function for invalidating a device table entry
484 static int iommu_flush_device(struct device *dev)
486 struct amd_iommu *iommu;
487 struct iommu_cmd cmd;
490 devid = get_device_id(dev);
491 iommu = amd_iommu_rlookup_table[devid];
494 memset(&cmd, 0, sizeof(cmd));
495 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
498 return iommu_queue_command(iommu, &cmd);
501 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
502 u16 domid, int pde, int s)
504 memset(cmd, 0, sizeof(*cmd));
505 address &= PAGE_MASK;
506 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
507 cmd->data[1] |= domid;
508 cmd->data[2] = lower_32_bits(address);
509 cmd->data[3] = upper_32_bits(address);
510 if (s) /* size bit - we flush more than one 4kb page */
511 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
512 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
513 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
517 * Generic command send function for invalidaing TLB entries
519 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
520 u64 address, u16 domid, int pde, int s)
522 struct iommu_cmd cmd;
525 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
527 ret = iommu_queue_command(iommu, &cmd);
533 * TLB invalidation function which is called from the mapping functions.
534 * It invalidates a single PTE if the range to flush is within a single
535 * page. Otherwise it flushes the whole TLB of the IOMMU.
537 static void __iommu_flush_pages(struct protection_domain *domain,
538 u64 address, size_t size, int pde)
541 unsigned long pages = iommu_num_pages(address, size, PAGE_SIZE);
543 address &= PAGE_MASK;
547 * If we have to flush more than one page, flush all
548 * TLB entries for this domain
550 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
555 for (i = 0; i < amd_iommus_present; ++i) {
556 if (!domain->dev_iommu[i])
560 * Devices of this domain are behind this IOMMU
561 * We need a TLB flush
563 iommu_queue_inv_iommu_pages(amd_iommus[i], address,
570 static void iommu_flush_pages(struct protection_domain *domain,
571 u64 address, size_t size)
573 __iommu_flush_pages(domain, address, size, 0);
576 /* Flush the whole IO/TLB for a given protection domain */
577 static void iommu_flush_tlb(struct protection_domain *domain)
579 __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
582 /* Flush the whole IO/TLB for a given protection domain - including PDE */
583 static void iommu_flush_tlb_pde(struct protection_domain *domain)
585 __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
590 * This function flushes the DTEs for all devices in domain
592 static void iommu_flush_domain_devices(struct protection_domain *domain)
594 struct iommu_dev_data *dev_data;
597 spin_lock_irqsave(&domain->lock, flags);
599 list_for_each_entry(dev_data, &domain->dev_list, list)
600 iommu_flush_device(dev_data->dev);
602 spin_unlock_irqrestore(&domain->lock, flags);
605 static void iommu_flush_all_domain_devices(void)
607 struct protection_domain *domain;
610 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
612 list_for_each_entry(domain, &amd_iommu_pd_list, list) {
613 iommu_flush_domain_devices(domain);
614 iommu_flush_complete(domain);
617 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
620 void amd_iommu_flush_all_devices(void)
622 iommu_flush_all_domain_devices();
626 * This function uses heavy locking and may disable irqs for some time. But
627 * this is no issue because it is only called during resume.
629 void amd_iommu_flush_all_domains(void)
631 struct protection_domain *domain;
634 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
636 list_for_each_entry(domain, &amd_iommu_pd_list, list) {
637 spin_lock(&domain->lock);
638 iommu_flush_tlb_pde(domain);
639 iommu_flush_complete(domain);
640 spin_unlock(&domain->lock);
643 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
646 static void reset_iommu_command_buffer(struct amd_iommu *iommu)
648 pr_err("AMD-Vi: Resetting IOMMU command buffer\n");
650 if (iommu->reset_in_progress)
651 panic("AMD-Vi: ILLEGAL_COMMAND_ERROR while resetting command buffer\n");
653 amd_iommu_reset_cmd_buffer(iommu);
654 amd_iommu_flush_all_devices();
655 amd_iommu_flush_all_domains();
657 iommu->reset_in_progress = false;
660 /****************************************************************************
662 * The functions below are used the create the page table mappings for
663 * unity mapped regions.
665 ****************************************************************************/
668 * This function is used to add another level to an IO page table. Adding
669 * another level increases the size of the address space by 9 bits to a size up
672 static bool increase_address_space(struct protection_domain *domain,
677 if (domain->mode == PAGE_MODE_6_LEVEL)
678 /* address space already 64 bit large */
681 pte = (void *)get_zeroed_page(gfp);
685 *pte = PM_LEVEL_PDE(domain->mode,
686 virt_to_phys(domain->pt_root));
687 domain->pt_root = pte;
689 domain->updated = true;
694 static u64 *alloc_pte(struct protection_domain *domain,
695 unsigned long address,
703 while (address > PM_LEVEL_SIZE(domain->mode))
704 increase_address_space(domain, gfp);
706 level = domain->mode - 1;
707 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
709 while (level > end_lvl) {
710 if (!IOMMU_PTE_PRESENT(*pte)) {
711 page = (u64 *)get_zeroed_page(gfp);
714 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
719 pte = IOMMU_PTE_PAGE(*pte);
721 if (pte_page && level == end_lvl)
724 pte = &pte[PM_LEVEL_INDEX(level, address)];
731 * This function checks if there is a PTE for a given dma address. If
732 * there is one, it returns the pointer to it.
734 static u64 *fetch_pte(struct protection_domain *domain,
735 unsigned long address, int map_size)
740 level = domain->mode - 1;
741 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
743 while (level > map_size) {
744 if (!IOMMU_PTE_PRESENT(*pte))
749 pte = IOMMU_PTE_PAGE(*pte);
750 pte = &pte[PM_LEVEL_INDEX(level, address)];
752 if ((PM_PTE_LEVEL(*pte) == 0) && level != map_size) {
762 * Generic mapping functions. It maps a physical address into a DMA
763 * address space. It allocates the page table pages if necessary.
764 * In the future it can be extended to a generic mapping function
765 * supporting all features of AMD IOMMU page tables like level skipping
766 * and full 64 bit address spaces.
768 static int iommu_map_page(struct protection_domain *dom,
769 unsigned long bus_addr,
770 unsigned long phys_addr,
776 bus_addr = PAGE_ALIGN(bus_addr);
777 phys_addr = PAGE_ALIGN(phys_addr);
779 BUG_ON(!PM_ALIGNED(map_size, bus_addr));
780 BUG_ON(!PM_ALIGNED(map_size, phys_addr));
782 if (!(prot & IOMMU_PROT_MASK))
785 pte = alloc_pte(dom, bus_addr, map_size, NULL, GFP_KERNEL);
787 if (IOMMU_PTE_PRESENT(*pte))
790 __pte = phys_addr | IOMMU_PTE_P;
791 if (prot & IOMMU_PROT_IR)
792 __pte |= IOMMU_PTE_IR;
793 if (prot & IOMMU_PROT_IW)
794 __pte |= IOMMU_PTE_IW;
803 static void iommu_unmap_page(struct protection_domain *dom,
804 unsigned long bus_addr, int map_size)
806 u64 *pte = fetch_pte(dom, bus_addr, map_size);
813 * This function checks if a specific unity mapping entry is needed for
814 * this specific IOMMU.
816 static int iommu_for_unity_map(struct amd_iommu *iommu,
817 struct unity_map_entry *entry)
821 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
822 bdf = amd_iommu_alias_table[i];
823 if (amd_iommu_rlookup_table[bdf] == iommu)
831 * This function actually applies the mapping to the page table of the
834 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
835 struct unity_map_entry *e)
840 for (addr = e->address_start; addr < e->address_end;
842 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
847 * if unity mapping is in aperture range mark the page
848 * as allocated in the aperture
850 if (addr < dma_dom->aperture_size)
851 __set_bit(addr >> PAGE_SHIFT,
852 dma_dom->aperture[0]->bitmap);
859 * Init the unity mappings for a specific IOMMU in the system
861 * Basically iterates over all unity mapping entries and applies them to
862 * the default domain DMA of that IOMMU if necessary.
864 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
866 struct unity_map_entry *entry;
869 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
870 if (!iommu_for_unity_map(iommu, entry))
872 ret = dma_ops_unity_map(iommu->default_dom, entry);
881 * Inits the unity mappings required for a specific device
883 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
886 struct unity_map_entry *e;
889 list_for_each_entry(e, &amd_iommu_unity_map, list) {
890 if (!(devid >= e->devid_start && devid <= e->devid_end))
892 ret = dma_ops_unity_map(dma_dom, e);
900 /****************************************************************************
902 * The next functions belong to the address allocator for the dma_ops
903 * interface functions. They work like the allocators in the other IOMMU
904 * drivers. Its basically a bitmap which marks the allocated pages in
905 * the aperture. Maybe it could be enhanced in the future to a more
906 * efficient allocator.
908 ****************************************************************************/
911 * The address allocator core functions.
913 * called with domain->lock held
917 * Used to reserve address ranges in the aperture (e.g. for exclusion
920 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
921 unsigned long start_page,
924 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
926 if (start_page + pages > last_page)
927 pages = last_page - start_page;
929 for (i = start_page; i < start_page + pages; ++i) {
930 int index = i / APERTURE_RANGE_PAGES;
931 int page = i % APERTURE_RANGE_PAGES;
932 __set_bit(page, dom->aperture[index]->bitmap);
937 * This function is used to add a new aperture range to an existing
938 * aperture in case of dma_ops domain allocation or address allocation
941 static int alloc_new_range(struct dma_ops_domain *dma_dom,
942 bool populate, gfp_t gfp)
944 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
945 struct amd_iommu *iommu;
948 #ifdef CONFIG_IOMMU_STRESS
952 if (index >= APERTURE_MAX_RANGES)
955 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
956 if (!dma_dom->aperture[index])
959 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
960 if (!dma_dom->aperture[index]->bitmap)
963 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
966 unsigned long address = dma_dom->aperture_size;
967 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
970 for (i = 0; i < num_ptes; ++i) {
971 pte = alloc_pte(&dma_dom->domain, address, PM_MAP_4k,
976 dma_dom->aperture[index]->pte_pages[i] = pte_page;
978 address += APERTURE_RANGE_SIZE / 64;
982 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
984 /* Intialize the exclusion range if necessary */
985 for_each_iommu(iommu) {
986 if (iommu->exclusion_start &&
987 iommu->exclusion_start >= dma_dom->aperture[index]->offset
988 && iommu->exclusion_start < dma_dom->aperture_size) {
989 unsigned long startpage;
990 int pages = iommu_num_pages(iommu->exclusion_start,
991 iommu->exclusion_length,
993 startpage = iommu->exclusion_start >> PAGE_SHIFT;
994 dma_ops_reserve_addresses(dma_dom, startpage, pages);
999 * Check for areas already mapped as present in the new aperture
1000 * range and mark those pages as reserved in the allocator. Such
1001 * mappings may already exist as a result of requested unity
1002 * mappings for devices.
1004 for (i = dma_dom->aperture[index]->offset;
1005 i < dma_dom->aperture_size;
1007 u64 *pte = fetch_pte(&dma_dom->domain, i, PM_MAP_4k);
1008 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1011 dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1);
1014 update_domain(&dma_dom->domain);
1019 update_domain(&dma_dom->domain);
1021 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1023 kfree(dma_dom->aperture[index]);
1024 dma_dom->aperture[index] = NULL;
1029 static unsigned long dma_ops_area_alloc(struct device *dev,
1030 struct dma_ops_domain *dom,
1032 unsigned long align_mask,
1034 unsigned long start)
1036 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
1037 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1038 int i = start >> APERTURE_RANGE_SHIFT;
1039 unsigned long boundary_size;
1040 unsigned long address = -1;
1041 unsigned long limit;
1043 next_bit >>= PAGE_SHIFT;
1045 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
1046 PAGE_SIZE) >> PAGE_SHIFT;
1048 for (;i < max_index; ++i) {
1049 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1051 if (dom->aperture[i]->offset >= dma_mask)
1054 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1055 dma_mask >> PAGE_SHIFT);
1057 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1058 limit, next_bit, pages, 0,
1059 boundary_size, align_mask);
1060 if (address != -1) {
1061 address = dom->aperture[i]->offset +
1062 (address << PAGE_SHIFT);
1063 dom->next_address = address + (pages << PAGE_SHIFT);
1073 static unsigned long dma_ops_alloc_addresses(struct device *dev,
1074 struct dma_ops_domain *dom,
1076 unsigned long align_mask,
1079 unsigned long address;
1081 #ifdef CONFIG_IOMMU_STRESS
1082 dom->next_address = 0;
1083 dom->need_flush = true;
1086 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1087 dma_mask, dom->next_address);
1089 if (address == -1) {
1090 dom->next_address = 0;
1091 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1093 dom->need_flush = true;
1096 if (unlikely(address == -1))
1097 address = DMA_ERROR_CODE;
1099 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1105 * The address free function.
1107 * called with domain->lock held
1109 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1110 unsigned long address,
1113 unsigned i = address >> APERTURE_RANGE_SHIFT;
1114 struct aperture_range *range = dom->aperture[i];
1116 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1118 #ifdef CONFIG_IOMMU_STRESS
1123 if (address >= dom->next_address)
1124 dom->need_flush = true;
1126 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1128 iommu_area_free(range->bitmap, address, pages);
1132 /****************************************************************************
1134 * The next functions belong to the domain allocation. A domain is
1135 * allocated for every IOMMU as the default domain. If device isolation
1136 * is enabled, every device get its own domain. The most important thing
1137 * about domains is the page table mapping the DMA address space they
1140 ****************************************************************************/
1143 * This function adds a protection domain to the global protection domain list
1145 static void add_domain_to_list(struct protection_domain *domain)
1147 unsigned long flags;
1149 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1150 list_add(&domain->list, &amd_iommu_pd_list);
1151 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1155 * This function removes a protection domain to the global
1156 * protection domain list
1158 static void del_domain_from_list(struct protection_domain *domain)
1160 unsigned long flags;
1162 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1163 list_del(&domain->list);
1164 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1167 static u16 domain_id_alloc(void)
1169 unsigned long flags;
1172 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1173 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1175 if (id > 0 && id < MAX_DOMAIN_ID)
1176 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1179 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1184 static void domain_id_free(int id)
1186 unsigned long flags;
1188 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1189 if (id > 0 && id < MAX_DOMAIN_ID)
1190 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1191 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1194 static void free_pagetable(struct protection_domain *domain)
1199 p1 = domain->pt_root;
1204 for (i = 0; i < 512; ++i) {
1205 if (!IOMMU_PTE_PRESENT(p1[i]))
1208 p2 = IOMMU_PTE_PAGE(p1[i]);
1209 for (j = 0; j < 512; ++j) {
1210 if (!IOMMU_PTE_PRESENT(p2[j]))
1212 p3 = IOMMU_PTE_PAGE(p2[j]);
1213 free_page((unsigned long)p3);
1216 free_page((unsigned long)p2);
1219 free_page((unsigned long)p1);
1221 domain->pt_root = NULL;
1225 * Free a domain, only used if something went wrong in the
1226 * allocation path and we need to free an already allocated page table
1228 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1235 del_domain_from_list(&dom->domain);
1237 free_pagetable(&dom->domain);
1239 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1240 if (!dom->aperture[i])
1242 free_page((unsigned long)dom->aperture[i]->bitmap);
1243 kfree(dom->aperture[i]);
1250 * Allocates a new protection domain usable for the dma_ops functions.
1251 * It also intializes the page table and the address allocator data
1252 * structures required for the dma_ops interface
1254 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1256 struct dma_ops_domain *dma_dom;
1258 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1262 spin_lock_init(&dma_dom->domain.lock);
1264 dma_dom->domain.id = domain_id_alloc();
1265 if (dma_dom->domain.id == 0)
1267 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
1268 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
1269 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1270 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1271 dma_dom->domain.priv = dma_dom;
1272 if (!dma_dom->domain.pt_root)
1275 dma_dom->need_flush = false;
1276 dma_dom->target_dev = 0xffff;
1278 add_domain_to_list(&dma_dom->domain);
1280 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
1284 * mark the first page as allocated so we never return 0 as
1285 * a valid dma-address. So we can use 0 as error value
1287 dma_dom->aperture[0]->bitmap[0] = 1;
1288 dma_dom->next_address = 0;
1294 dma_ops_domain_free(dma_dom);
1300 * little helper function to check whether a given protection domain is a
1303 static bool dma_ops_domain(struct protection_domain *domain)
1305 return domain->flags & PD_DMA_OPS_MASK;
1308 static void set_dte_entry(u16 devid, struct protection_domain *domain)
1310 u64 pte_root = virt_to_phys(domain->pt_root);
1312 BUG_ON(amd_iommu_pd_table[devid] != NULL);
1314 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1315 << DEV_ENTRY_MODE_SHIFT;
1316 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1318 amd_iommu_dev_table[devid].data[2] = domain->id;
1319 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
1320 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
1322 amd_iommu_pd_table[devid] = domain;
1326 static void clear_dte_entry(u16 devid)
1328 struct protection_domain *domain = amd_iommu_pd_table[devid];
1330 BUG_ON(domain == NULL);
1332 /* remove domain from the lookup table */
1333 amd_iommu_pd_table[devid] = NULL;
1335 /* remove entry from the device table seen by the hardware */
1336 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1337 amd_iommu_dev_table[devid].data[1] = 0;
1338 amd_iommu_dev_table[devid].data[2] = 0;
1340 amd_iommu_apply_erratum_63(devid);
1343 static void do_attach(struct device *dev, struct protection_domain *domain)
1345 struct iommu_dev_data *dev_data;
1346 struct amd_iommu *iommu;
1349 devid = get_device_id(dev);
1350 iommu = amd_iommu_rlookup_table[devid];
1351 dev_data = get_dev_data(dev);
1353 /* Update data structures */
1354 dev_data->domain = domain;
1355 list_add(&dev_data->list, &domain->dev_list);
1356 set_dte_entry(devid, domain);
1358 /* Do reference counting */
1359 domain->dev_iommu[iommu->index] += 1;
1360 domain->dev_cnt += 1;
1362 /* Flush the DTE entry */
1363 iommu_flush_device(dev);
1366 static void do_detach(struct device *dev)
1368 struct iommu_dev_data *dev_data;
1369 struct amd_iommu *iommu;
1372 devid = get_device_id(dev);
1373 iommu = amd_iommu_rlookup_table[devid];
1374 dev_data = get_dev_data(dev);
1376 /* decrease reference counters */
1377 dev_data->domain->dev_iommu[iommu->index] -= 1;
1378 dev_data->domain->dev_cnt -= 1;
1380 /* Update data structures */
1381 dev_data->domain = NULL;
1382 list_del(&dev_data->list);
1383 clear_dte_entry(devid);
1385 /* Flush the DTE entry */
1386 iommu_flush_device(dev);
1390 * If a device is not yet associated with a domain, this function does
1391 * assigns it visible for the hardware
1393 static int __attach_device(struct device *dev,
1394 struct protection_domain *domain)
1396 struct iommu_dev_data *dev_data, *alias_data;
1398 dev_data = get_dev_data(dev);
1399 alias_data = get_dev_data(dev_data->alias);
1405 spin_lock(&domain->lock);
1407 /* Some sanity checks */
1408 if (alias_data->domain != NULL &&
1409 alias_data->domain != domain)
1412 if (dev_data->domain != NULL &&
1413 dev_data->domain != domain)
1416 /* Do real assignment */
1417 if (dev_data->alias != dev) {
1418 alias_data = get_dev_data(dev_data->alias);
1419 if (alias_data->domain == NULL)
1420 do_attach(dev_data->alias, domain);
1422 atomic_inc(&alias_data->bind);
1425 if (dev_data->domain == NULL)
1426 do_attach(dev, domain);
1428 atomic_inc(&dev_data->bind);
1431 spin_unlock(&domain->lock);
1437 * If a device is not yet associated with a domain, this function does
1438 * assigns it visible for the hardware
1440 static int attach_device(struct device *dev,
1441 struct protection_domain *domain)
1443 unsigned long flags;
1446 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1447 ret = __attach_device(dev, domain);
1448 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1451 * We might boot into a crash-kernel here. The crashed kernel
1452 * left the caches in the IOMMU dirty. So we have to flush
1453 * here to evict all dirty stuff.
1455 iommu_flush_tlb_pde(domain);
1461 * Removes a device from a protection domain (unlocked)
1463 static void __detach_device(struct device *dev)
1465 struct iommu_dev_data *dev_data = get_dev_data(dev);
1466 struct iommu_dev_data *alias_data;
1467 unsigned long flags;
1469 BUG_ON(!dev_data->domain);
1471 spin_lock_irqsave(&dev_data->domain->lock, flags);
1473 if (dev_data->alias != dev) {
1474 alias_data = get_dev_data(dev_data->alias);
1475 if (atomic_dec_and_test(&alias_data->bind))
1476 do_detach(dev_data->alias);
1479 if (atomic_dec_and_test(&dev_data->bind))
1482 spin_unlock_irqrestore(&dev_data->domain->lock, flags);
1485 * If we run in passthrough mode the device must be assigned to the
1486 * passthrough domain if it is detached from any other domain
1488 if (iommu_pass_through && dev_data->domain == NULL)
1489 __attach_device(dev, pt_domain);
1493 * Removes a device from a protection domain (with devtable_lock held)
1495 static void detach_device(struct device *dev)
1497 unsigned long flags;
1499 /* lock device table */
1500 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1501 __detach_device(dev);
1502 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1506 * Find out the protection domain structure for a given PCI device. This
1507 * will give us the pointer to the page table root for example.
1509 static struct protection_domain *domain_for_device(struct device *dev)
1511 struct protection_domain *dom;
1512 struct iommu_dev_data *dev_data, *alias_data;
1513 unsigned long flags;
1516 devid = get_device_id(dev);
1517 alias = amd_iommu_alias_table[devid];
1518 dev_data = get_dev_data(dev);
1519 alias_data = get_dev_data(dev_data->alias);
1523 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
1524 dom = dev_data->domain;
1526 alias_data->domain != NULL) {
1527 __attach_device(dev, alias_data->domain);
1528 dom = alias_data->domain;
1531 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1536 static int device_change_notifier(struct notifier_block *nb,
1537 unsigned long action, void *data)
1539 struct device *dev = data;
1541 struct protection_domain *domain;
1542 struct dma_ops_domain *dma_domain;
1543 struct amd_iommu *iommu;
1544 unsigned long flags;
1546 if (!check_device(dev))
1549 devid = get_device_id(dev);
1550 iommu = amd_iommu_rlookup_table[devid];
1553 case BUS_NOTIFY_UNBOUND_DRIVER:
1555 domain = domain_for_device(dev);
1559 if (iommu_pass_through)
1563 case BUS_NOTIFY_ADD_DEVICE:
1565 iommu_init_device(dev);
1567 domain = domain_for_device(dev);
1569 /* allocate a protection domain if a device is added */
1570 dma_domain = find_protection_domain(devid);
1573 dma_domain = dma_ops_domain_alloc();
1576 dma_domain->target_dev = devid;
1578 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1579 list_add_tail(&dma_domain->list, &iommu_pd_list);
1580 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1583 case BUS_NOTIFY_DEL_DEVICE:
1585 iommu_uninit_device(dev);
1591 iommu_flush_device(dev);
1592 iommu_completion_wait(iommu);
1598 static struct notifier_block device_nb = {
1599 .notifier_call = device_change_notifier,
1602 /*****************************************************************************
1604 * The next functions belong to the dma_ops mapping/unmapping code.
1606 *****************************************************************************/
1609 * In the dma_ops path we only have the struct device. This function
1610 * finds the corresponding IOMMU, the protection domain and the
1611 * requestor id for a given device.
1612 * If the device is not yet associated with a domain this is also done
1615 static struct protection_domain *get_domain(struct device *dev)
1617 struct protection_domain *domain;
1618 struct dma_ops_domain *dma_dom;
1619 u16 devid = get_device_id(dev);
1621 if (!check_device(dev))
1622 return ERR_PTR(-EINVAL);
1624 domain = domain_for_device(dev);
1625 if (domain != NULL && !dma_ops_domain(domain))
1626 return ERR_PTR(-EBUSY);
1631 /* Device not bount yet - bind it */
1632 dma_dom = find_protection_domain(devid);
1634 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
1635 attach_device(dev, &dma_dom->domain);
1636 DUMP_printk("Using protection domain %d for device %s\n",
1637 dma_dom->domain.id, dev_name(dev));
1639 return &dma_dom->domain;
1642 static void update_device_table(struct protection_domain *domain)
1644 unsigned long flags;
1647 for (i = 0; i <= amd_iommu_last_bdf; ++i) {
1648 if (amd_iommu_pd_table[i] != domain)
1650 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1651 set_dte_entry(i, domain);
1652 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1656 static void update_domain(struct protection_domain *domain)
1658 if (!domain->updated)
1661 update_device_table(domain);
1662 iommu_flush_domain_devices(domain);
1663 iommu_flush_tlb_pde(domain);
1665 domain->updated = false;
1669 * This function fetches the PTE for a given address in the aperture
1671 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
1672 unsigned long address)
1674 struct aperture_range *aperture;
1675 u64 *pte, *pte_page;
1677 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1681 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1683 pte = alloc_pte(&dom->domain, address, PM_MAP_4k, &pte_page,
1685 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
1687 pte += PM_LEVEL_INDEX(0, address);
1689 update_domain(&dom->domain);
1695 * This is the generic map function. It maps one 4kb page at paddr to
1696 * the given address in the DMA address space for the domain.
1698 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
1699 unsigned long address,
1705 WARN_ON(address > dom->aperture_size);
1709 pte = dma_ops_get_pte(dom, address);
1711 return DMA_ERROR_CODE;
1713 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1715 if (direction == DMA_TO_DEVICE)
1716 __pte |= IOMMU_PTE_IR;
1717 else if (direction == DMA_FROM_DEVICE)
1718 __pte |= IOMMU_PTE_IW;
1719 else if (direction == DMA_BIDIRECTIONAL)
1720 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1726 return (dma_addr_t)address;
1730 * The generic unmapping function for on page in the DMA address space.
1732 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
1733 unsigned long address)
1735 struct aperture_range *aperture;
1738 if (address >= dom->aperture_size)
1741 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1745 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1749 pte += PM_LEVEL_INDEX(0, address);
1757 * This function contains common code for mapping of a physically
1758 * contiguous memory region into DMA address space. It is used by all
1759 * mapping functions provided with this IOMMU driver.
1760 * Must be called with the domain lock held.
1762 static dma_addr_t __map_single(struct device *dev,
1763 struct dma_ops_domain *dma_dom,
1770 dma_addr_t offset = paddr & ~PAGE_MASK;
1771 dma_addr_t address, start, ret;
1773 unsigned long align_mask = 0;
1776 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1779 INC_STATS_COUNTER(total_map_requests);
1782 INC_STATS_COUNTER(cross_page);
1785 align_mask = (1UL << get_order(size)) - 1;
1788 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1790 if (unlikely(address == DMA_ERROR_CODE)) {
1792 * setting next_address here will let the address
1793 * allocator only scan the new allocated range in the
1794 * first run. This is a small optimization.
1796 dma_dom->next_address = dma_dom->aperture_size;
1798 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
1802 * aperture was sucessfully enlarged by 128 MB, try
1809 for (i = 0; i < pages; ++i) {
1810 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
1811 if (ret == DMA_ERROR_CODE)
1819 ADD_STATS_COUNTER(alloced_io_mem, size);
1821 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1822 iommu_flush_tlb(&dma_dom->domain);
1823 dma_dom->need_flush = false;
1824 } else if (unlikely(amd_iommu_np_cache))
1825 iommu_flush_pages(&dma_dom->domain, address, size);
1832 for (--i; i >= 0; --i) {
1834 dma_ops_domain_unmap(dma_dom, start);
1837 dma_ops_free_addresses(dma_dom, address, pages);
1839 return DMA_ERROR_CODE;
1843 * Does the reverse of the __map_single function. Must be called with
1844 * the domain lock held too
1846 static void __unmap_single(struct dma_ops_domain *dma_dom,
1847 dma_addr_t dma_addr,
1851 dma_addr_t i, start;
1854 if ((dma_addr == DMA_ERROR_CODE) ||
1855 (dma_addr + size > dma_dom->aperture_size))
1858 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1859 dma_addr &= PAGE_MASK;
1862 for (i = 0; i < pages; ++i) {
1863 dma_ops_domain_unmap(dma_dom, start);
1867 SUB_STATS_COUNTER(alloced_io_mem, size);
1869 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1871 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1872 iommu_flush_pages(&dma_dom->domain, dma_addr, size);
1873 dma_dom->need_flush = false;
1878 * The exported map_single function for dma_ops.
1880 static dma_addr_t map_page(struct device *dev, struct page *page,
1881 unsigned long offset, size_t size,
1882 enum dma_data_direction dir,
1883 struct dma_attrs *attrs)
1885 unsigned long flags;
1886 struct protection_domain *domain;
1889 phys_addr_t paddr = page_to_phys(page) + offset;
1891 INC_STATS_COUNTER(cnt_map_single);
1893 domain = get_domain(dev);
1894 if (PTR_ERR(domain) == -EINVAL)
1895 return (dma_addr_t)paddr;
1896 else if (IS_ERR(domain))
1897 return DMA_ERROR_CODE;
1899 dma_mask = *dev->dma_mask;
1901 spin_lock_irqsave(&domain->lock, flags);
1903 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
1905 if (addr == DMA_ERROR_CODE)
1908 iommu_flush_complete(domain);
1911 spin_unlock_irqrestore(&domain->lock, flags);
1917 * The exported unmap_single function for dma_ops.
1919 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
1920 enum dma_data_direction dir, struct dma_attrs *attrs)
1922 unsigned long flags;
1923 struct protection_domain *domain;
1925 INC_STATS_COUNTER(cnt_unmap_single);
1927 domain = get_domain(dev);
1931 spin_lock_irqsave(&domain->lock, flags);
1933 __unmap_single(domain->priv, dma_addr, size, dir);
1935 iommu_flush_complete(domain);
1937 spin_unlock_irqrestore(&domain->lock, flags);
1941 * This is a special map_sg function which is used if we should map a
1942 * device which is not handled by an AMD IOMMU in the system.
1944 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1945 int nelems, int dir)
1947 struct scatterlist *s;
1950 for_each_sg(sglist, s, nelems, i) {
1951 s->dma_address = (dma_addr_t)sg_phys(s);
1952 s->dma_length = s->length;
1959 * The exported map_sg function for dma_ops (handles scatter-gather
1962 static int map_sg(struct device *dev, struct scatterlist *sglist,
1963 int nelems, enum dma_data_direction dir,
1964 struct dma_attrs *attrs)
1966 unsigned long flags;
1967 struct protection_domain *domain;
1969 struct scatterlist *s;
1971 int mapped_elems = 0;
1974 INC_STATS_COUNTER(cnt_map_sg);
1976 domain = get_domain(dev);
1977 if (PTR_ERR(domain) == -EINVAL)
1978 return map_sg_no_iommu(dev, sglist, nelems, dir);
1979 else if (IS_ERR(domain))
1982 dma_mask = *dev->dma_mask;
1984 spin_lock_irqsave(&domain->lock, flags);
1986 for_each_sg(sglist, s, nelems, i) {
1989 s->dma_address = __map_single(dev, domain->priv,
1990 paddr, s->length, dir, false,
1993 if (s->dma_address) {
1994 s->dma_length = s->length;
2000 iommu_flush_complete(domain);
2003 spin_unlock_irqrestore(&domain->lock, flags);
2005 return mapped_elems;
2007 for_each_sg(sglist, s, mapped_elems, i) {
2009 __unmap_single(domain->priv, s->dma_address,
2010 s->dma_length, dir);
2011 s->dma_address = s->dma_length = 0;
2020 * The exported map_sg function for dma_ops (handles scatter-gather
2023 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2024 int nelems, enum dma_data_direction dir,
2025 struct dma_attrs *attrs)
2027 unsigned long flags;
2028 struct protection_domain *domain;
2029 struct scatterlist *s;
2032 INC_STATS_COUNTER(cnt_unmap_sg);
2034 domain = get_domain(dev);
2038 spin_lock_irqsave(&domain->lock, flags);
2040 for_each_sg(sglist, s, nelems, i) {
2041 __unmap_single(domain->priv, s->dma_address,
2042 s->dma_length, dir);
2043 s->dma_address = s->dma_length = 0;
2046 iommu_flush_complete(domain);
2048 spin_unlock_irqrestore(&domain->lock, flags);
2052 * The exported alloc_coherent function for dma_ops.
2054 static void *alloc_coherent(struct device *dev, size_t size,
2055 dma_addr_t *dma_addr, gfp_t flag)
2057 unsigned long flags;
2059 struct protection_domain *domain;
2061 u64 dma_mask = dev->coherent_dma_mask;
2063 INC_STATS_COUNTER(cnt_alloc_coherent);
2065 domain = get_domain(dev);
2066 if (PTR_ERR(domain) == -EINVAL) {
2067 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2068 *dma_addr = __pa(virt_addr);
2070 } else if (IS_ERR(domain))
2073 dma_mask = dev->coherent_dma_mask;
2074 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2077 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2081 paddr = virt_to_phys(virt_addr);
2084 dma_mask = *dev->dma_mask;
2086 spin_lock_irqsave(&domain->lock, flags);
2088 *dma_addr = __map_single(dev, domain->priv, paddr,
2089 size, DMA_BIDIRECTIONAL, true, dma_mask);
2091 if (*dma_addr == DMA_ERROR_CODE) {
2092 spin_unlock_irqrestore(&domain->lock, flags);
2096 iommu_flush_complete(domain);
2098 spin_unlock_irqrestore(&domain->lock, flags);
2104 free_pages((unsigned long)virt_addr, get_order(size));
2110 * The exported free_coherent function for dma_ops.
2112 static void free_coherent(struct device *dev, size_t size,
2113 void *virt_addr, dma_addr_t dma_addr)
2115 unsigned long flags;
2116 struct protection_domain *domain;
2118 INC_STATS_COUNTER(cnt_free_coherent);
2120 domain = get_domain(dev);
2124 spin_lock_irqsave(&domain->lock, flags);
2126 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2128 iommu_flush_complete(domain);
2130 spin_unlock_irqrestore(&domain->lock, flags);
2133 free_pages((unsigned long)virt_addr, get_order(size));
2137 * This function is called by the DMA layer to find out if we can handle a
2138 * particular device. It is part of the dma_ops.
2140 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2142 return check_device(dev);
2146 * The function for pre-allocating protection domains.
2148 * If the driver core informs the DMA layer if a driver grabs a device
2149 * we don't need to preallocate the protection domains anymore.
2150 * For now we have to.
2152 static void prealloc_protection_domains(void)
2154 struct pci_dev *dev = NULL;
2155 struct dma_ops_domain *dma_dom;
2158 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2160 /* Do we handle this device? */
2161 if (!check_device(&dev->dev))
2164 iommu_init_device(&dev->dev);
2166 /* Is there already any domain for it? */
2167 if (domain_for_device(&dev->dev))
2170 devid = get_device_id(&dev->dev);
2172 dma_dom = dma_ops_domain_alloc();
2175 init_unity_mappings_for_device(dma_dom, devid);
2176 dma_dom->target_dev = devid;
2178 attach_device(&dev->dev, &dma_dom->domain);
2180 list_add_tail(&dma_dom->list, &iommu_pd_list);
2184 static struct dma_map_ops amd_iommu_dma_ops = {
2185 .alloc_coherent = alloc_coherent,
2186 .free_coherent = free_coherent,
2187 .map_page = map_page,
2188 .unmap_page = unmap_page,
2190 .unmap_sg = unmap_sg,
2191 .dma_supported = amd_iommu_dma_supported,
2195 * The function which clues the AMD IOMMU driver into dma_ops.
2197 int __init amd_iommu_init_dma_ops(void)
2199 struct amd_iommu *iommu;
2203 * first allocate a default protection domain for every IOMMU we
2204 * found in the system. Devices not assigned to any other
2205 * protection domain will be assigned to the default one.
2207 for_each_iommu(iommu) {
2208 iommu->default_dom = dma_ops_domain_alloc();
2209 if (iommu->default_dom == NULL)
2211 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
2212 ret = iommu_init_unity_mappings(iommu);
2218 * Pre-allocate the protection domains for each device.
2220 prealloc_protection_domains();
2224 #ifdef CONFIG_GART_IOMMU
2225 gart_iommu_aperture_disabled = 1;
2226 gart_iommu_aperture = 0;
2229 /* Make the driver finally visible to the drivers */
2230 dma_ops = &amd_iommu_dma_ops;
2232 register_iommu(&amd_iommu_ops);
2234 bus_register_notifier(&pci_bus_type, &device_nb);
2236 amd_iommu_stats_init();
2242 for_each_iommu(iommu) {
2243 if (iommu->default_dom)
2244 dma_ops_domain_free(iommu->default_dom);
2250 /*****************************************************************************
2252 * The following functions belong to the exported interface of AMD IOMMU
2254 * This interface allows access to lower level functions of the IOMMU
2255 * like protection domain handling and assignement of devices to domains
2256 * which is not possible with the dma_ops interface.
2258 *****************************************************************************/
2260 static void cleanup_domain(struct protection_domain *domain)
2262 unsigned long flags;
2265 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2267 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
2268 if (amd_iommu_pd_table[devid] == domain)
2269 clear_dte_entry(devid);
2271 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2274 static void protection_domain_free(struct protection_domain *domain)
2279 del_domain_from_list(domain);
2282 domain_id_free(domain->id);
2287 static struct protection_domain *protection_domain_alloc(void)
2289 struct protection_domain *domain;
2291 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2295 spin_lock_init(&domain->lock);
2296 domain->id = domain_id_alloc();
2299 INIT_LIST_HEAD(&domain->dev_list);
2301 add_domain_to_list(domain);
2311 static int amd_iommu_domain_init(struct iommu_domain *dom)
2313 struct protection_domain *domain;
2315 domain = protection_domain_alloc();
2319 domain->mode = PAGE_MODE_3_LEVEL;
2320 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2321 if (!domain->pt_root)
2329 protection_domain_free(domain);
2334 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
2336 struct protection_domain *domain = dom->priv;
2341 if (domain->dev_cnt > 0)
2342 cleanup_domain(domain);
2344 BUG_ON(domain->dev_cnt != 0);
2346 free_pagetable(domain);
2348 domain_id_free(domain->id);
2355 static void amd_iommu_detach_device(struct iommu_domain *dom,
2358 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2359 struct amd_iommu *iommu;
2362 if (!check_device(dev))
2365 devid = get_device_id(dev);
2367 if (dev_data->domain != NULL)
2370 iommu = amd_iommu_rlookup_table[devid];
2374 iommu_flush_device(dev);
2375 iommu_completion_wait(iommu);
2378 static int amd_iommu_attach_device(struct iommu_domain *dom,
2381 struct protection_domain *domain = dom->priv;
2382 struct iommu_dev_data *dev_data;
2383 struct amd_iommu *iommu;
2387 if (!check_device(dev))
2390 dev_data = dev->archdata.iommu;
2392 devid = get_device_id(dev);
2394 iommu = amd_iommu_rlookup_table[devid];
2398 if (dev_data->domain)
2401 ret = attach_device(dev, domain);
2403 iommu_completion_wait(iommu);
2408 static int amd_iommu_map_range(struct iommu_domain *dom,
2409 unsigned long iova, phys_addr_t paddr,
2410 size_t size, int iommu_prot)
2412 struct protection_domain *domain = dom->priv;
2413 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
2417 if (iommu_prot & IOMMU_READ)
2418 prot |= IOMMU_PROT_IR;
2419 if (iommu_prot & IOMMU_WRITE)
2420 prot |= IOMMU_PROT_IW;
2425 for (i = 0; i < npages; ++i) {
2426 ret = iommu_map_page(domain, iova, paddr, prot, PM_MAP_4k);
2437 static void amd_iommu_unmap_range(struct iommu_domain *dom,
2438 unsigned long iova, size_t size)
2441 struct protection_domain *domain = dom->priv;
2442 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
2446 for (i = 0; i < npages; ++i) {
2447 iommu_unmap_page(domain, iova, PM_MAP_4k);
2451 iommu_flush_tlb_pde(domain);
2454 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2457 struct protection_domain *domain = dom->priv;
2458 unsigned long offset = iova & ~PAGE_MASK;
2462 pte = fetch_pte(domain, iova, PM_MAP_4k);
2464 if (!pte || !IOMMU_PTE_PRESENT(*pte))
2467 paddr = *pte & IOMMU_PAGE_MASK;
2473 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
2479 static struct iommu_ops amd_iommu_ops = {
2480 .domain_init = amd_iommu_domain_init,
2481 .domain_destroy = amd_iommu_domain_destroy,
2482 .attach_dev = amd_iommu_attach_device,
2483 .detach_dev = amd_iommu_detach_device,
2484 .map = amd_iommu_map_range,
2485 .unmap = amd_iommu_unmap_range,
2486 .iova_to_phys = amd_iommu_iova_to_phys,
2487 .domain_has_cap = amd_iommu_domain_has_cap,
2490 /*****************************************************************************
2492 * The next functions do a basic initialization of IOMMU for pass through
2495 * In passthrough mode the IOMMU is initialized and enabled but not used for
2496 * DMA-API translation.
2498 *****************************************************************************/
2500 int __init amd_iommu_init_passthrough(void)
2502 struct amd_iommu *iommu;
2503 struct pci_dev *dev = NULL;
2506 /* allocate passthroug domain */
2507 pt_domain = protection_domain_alloc();
2511 pt_domain->mode |= PAGE_MODE_NONE;
2513 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2515 if (!check_device(&dev->dev))
2518 devid = get_device_id(&dev->dev);
2520 iommu = amd_iommu_rlookup_table[devid];
2524 attach_device(&dev->dev, pt_domain);
2527 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");