2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/iommu-helper.h>
27 #include <linux/iommu.h>
28 #include <asm/proto.h>
29 #include <asm/iommu.h>
31 #include <asm/amd_iommu_types.h>
32 #include <asm/amd_iommu.h>
34 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
36 #define EXIT_LOOP_COUNT 10000000
38 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
40 /* A list of preallocated protection domains */
41 static LIST_HEAD(iommu_pd_list);
42 static DEFINE_SPINLOCK(iommu_pd_list_lock);
44 #ifdef CONFIG_IOMMU_API
45 static struct iommu_ops amd_iommu_ops;
49 * general struct to manage commands send to an IOMMU
55 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
56 struct unity_map_entry *e);
57 static struct dma_ops_domain *find_protection_domain(u16 devid);
60 #ifdef CONFIG_AMD_IOMMU_STATS
63 * Initialization code for statistics collection
66 DECLARE_STATS_COUNTER(compl_wait);
67 DECLARE_STATS_COUNTER(cnt_map_single);
68 DECLARE_STATS_COUNTER(cnt_unmap_single);
69 DECLARE_STATS_COUNTER(cnt_map_sg);
70 DECLARE_STATS_COUNTER(cnt_unmap_sg);
71 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
72 DECLARE_STATS_COUNTER(cnt_free_coherent);
73 DECLARE_STATS_COUNTER(cross_page);
74 DECLARE_STATS_COUNTER(domain_flush_single);
75 DECLARE_STATS_COUNTER(domain_flush_all);
76 DECLARE_STATS_COUNTER(alloced_io_mem);
77 DECLARE_STATS_COUNTER(total_map_requests);
79 static struct dentry *stats_dir;
80 static struct dentry *de_isolate;
81 static struct dentry *de_fflush;
83 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
85 if (stats_dir == NULL)
88 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
92 static void amd_iommu_stats_init(void)
94 stats_dir = debugfs_create_dir("amd-iommu", NULL);
95 if (stats_dir == NULL)
98 de_isolate = debugfs_create_bool("isolation", 0444, stats_dir,
99 (u32 *)&amd_iommu_isolate);
101 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
102 (u32 *)&amd_iommu_unmap_flush);
104 amd_iommu_stats_add(&compl_wait);
105 amd_iommu_stats_add(&cnt_map_single);
106 amd_iommu_stats_add(&cnt_unmap_single);
107 amd_iommu_stats_add(&cnt_map_sg);
108 amd_iommu_stats_add(&cnt_unmap_sg);
109 amd_iommu_stats_add(&cnt_alloc_coherent);
110 amd_iommu_stats_add(&cnt_free_coherent);
111 amd_iommu_stats_add(&cross_page);
112 amd_iommu_stats_add(&domain_flush_single);
113 amd_iommu_stats_add(&domain_flush_all);
114 amd_iommu_stats_add(&alloced_io_mem);
115 amd_iommu_stats_add(&total_map_requests);
120 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
121 static int iommu_has_npcache(struct amd_iommu *iommu)
123 return iommu->cap & (1UL << IOMMU_CAP_NPCACHE);
126 /****************************************************************************
128 * Interrupt handling functions
130 ****************************************************************************/
132 static void iommu_print_event(void *__evt)
135 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
136 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
137 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
138 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
139 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
141 printk(KERN_ERR "AMD IOMMU: Event logged [");
144 case EVENT_TYPE_ILL_DEV:
145 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
146 "address=0x%016llx flags=0x%04x]\n",
147 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
150 case EVENT_TYPE_IO_FAULT:
151 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
152 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
153 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
154 domid, address, flags);
156 case EVENT_TYPE_DEV_TAB_ERR:
157 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
158 "address=0x%016llx flags=0x%04x]\n",
159 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
162 case EVENT_TYPE_PAGE_TAB_ERR:
163 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
164 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
165 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
166 domid, address, flags);
168 case EVENT_TYPE_ILL_CMD:
169 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
171 case EVENT_TYPE_CMD_HARD_ERR:
172 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
173 "flags=0x%04x]\n", address, flags);
175 case EVENT_TYPE_IOTLB_INV_TO:
176 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
177 "address=0x%016llx]\n",
178 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
181 case EVENT_TYPE_INV_DEV_REQ:
182 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
183 "address=0x%016llx flags=0x%04x]\n",
184 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
188 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
192 static void iommu_poll_events(struct amd_iommu *iommu)
197 spin_lock_irqsave(&iommu->lock, flags);
199 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
200 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
202 while (head != tail) {
203 iommu_print_event(iommu->evt_buf + head);
204 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
207 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
209 spin_unlock_irqrestore(&iommu->lock, flags);
212 irqreturn_t amd_iommu_int_handler(int irq, void *data)
214 struct amd_iommu *iommu;
216 for_each_iommu(iommu)
217 iommu_poll_events(iommu);
222 /****************************************************************************
224 * IOMMU command queuing functions
226 ****************************************************************************/
229 * Writes the command to the IOMMUs command buffer and informs the
230 * hardware about the new command. Must be called with iommu->lock held.
232 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
237 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
238 target = iommu->cmd_buf + tail;
239 memcpy_toio(target, cmd, sizeof(*cmd));
240 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
241 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
244 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
250 * General queuing function for commands. Takes iommu->lock and calls
251 * __iommu_queue_command().
253 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
258 spin_lock_irqsave(&iommu->lock, flags);
259 ret = __iommu_queue_command(iommu, cmd);
261 iommu->need_sync = true;
262 spin_unlock_irqrestore(&iommu->lock, flags);
268 * This function waits until an IOMMU has completed a completion
271 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
277 INC_STATS_COUNTER(compl_wait);
279 while (!ready && (i < EXIT_LOOP_COUNT)) {
281 /* wait for the bit to become one */
282 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
283 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
286 /* set bit back to zero */
287 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
288 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
290 if (unlikely(i == EXIT_LOOP_COUNT))
291 panic("AMD IOMMU: Completion wait loop failed\n");
295 * This function queues a completion wait command into the command
298 static int __iommu_completion_wait(struct amd_iommu *iommu)
300 struct iommu_cmd cmd;
302 memset(&cmd, 0, sizeof(cmd));
303 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
304 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
306 return __iommu_queue_command(iommu, &cmd);
310 * This function is called whenever we need to ensure that the IOMMU has
311 * completed execution of all commands we sent. It sends a
312 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
313 * us about that by writing a value to a physical address we pass with
316 static int iommu_completion_wait(struct amd_iommu *iommu)
321 spin_lock_irqsave(&iommu->lock, flags);
323 if (!iommu->need_sync)
326 ret = __iommu_completion_wait(iommu);
328 iommu->need_sync = false;
333 __iommu_wait_for_completion(iommu);
336 spin_unlock_irqrestore(&iommu->lock, flags);
342 * Command send function for invalidating a device table entry
344 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
346 struct iommu_cmd cmd;
349 BUG_ON(iommu == NULL);
351 memset(&cmd, 0, sizeof(cmd));
352 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
355 ret = iommu_queue_command(iommu, &cmd);
360 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
361 u16 domid, int pde, int s)
363 memset(cmd, 0, sizeof(*cmd));
364 address &= PAGE_MASK;
365 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
366 cmd->data[1] |= domid;
367 cmd->data[2] = lower_32_bits(address);
368 cmd->data[3] = upper_32_bits(address);
369 if (s) /* size bit - we flush more than one 4kb page */
370 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
371 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
372 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
376 * Generic command send function for invalidaing TLB entries
378 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
379 u64 address, u16 domid, int pde, int s)
381 struct iommu_cmd cmd;
384 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
386 ret = iommu_queue_command(iommu, &cmd);
392 * TLB invalidation function which is called from the mapping functions.
393 * It invalidates a single PTE if the range to flush is within a single
394 * page. Otherwise it flushes the whole TLB of the IOMMU.
396 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
397 u64 address, size_t size)
400 unsigned pages = iommu_num_pages(address, size, PAGE_SIZE);
402 address &= PAGE_MASK;
406 * If we have to flush more than one page, flush all
407 * TLB entries for this domain
409 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
413 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
418 /* Flush the whole IO/TLB for a given protection domain */
419 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
421 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
423 INC_STATS_COUNTER(domain_flush_single);
425 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
429 * This function is used to flush the IO/TLB for a given protection domain
430 * on every IOMMU in the system
432 static void iommu_flush_domain(u16 domid)
435 struct amd_iommu *iommu;
436 struct iommu_cmd cmd;
438 INC_STATS_COUNTER(domain_flush_all);
440 __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
443 for_each_iommu(iommu) {
444 spin_lock_irqsave(&iommu->lock, flags);
445 __iommu_queue_command(iommu, &cmd);
446 __iommu_completion_wait(iommu);
447 __iommu_wait_for_completion(iommu);
448 spin_unlock_irqrestore(&iommu->lock, flags);
452 void amd_iommu_flush_all_domains(void)
456 for (i = 1; i < MAX_DOMAIN_ID; ++i) {
457 if (!test_bit(i, amd_iommu_pd_alloc_bitmap))
459 iommu_flush_domain(i);
463 /****************************************************************************
465 * The functions below are used the create the page table mappings for
466 * unity mapped regions.
468 ****************************************************************************/
471 * Generic mapping functions. It maps a physical address into a DMA
472 * address space. It allocates the page table pages if necessary.
473 * In the future it can be extended to a generic mapping function
474 * supporting all features of AMD IOMMU page tables like level skipping
475 * and full 64 bit address spaces.
477 static int iommu_map_page(struct protection_domain *dom,
478 unsigned long bus_addr,
479 unsigned long phys_addr,
482 u64 __pte, *pte, *page;
484 bus_addr = PAGE_ALIGN(bus_addr);
485 phys_addr = PAGE_ALIGN(phys_addr);
487 /* only support 512GB address spaces for now */
488 if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
491 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
493 if (!IOMMU_PTE_PRESENT(*pte)) {
494 page = (u64 *)get_zeroed_page(GFP_KERNEL);
497 *pte = IOMMU_L2_PDE(virt_to_phys(page));
500 pte = IOMMU_PTE_PAGE(*pte);
501 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
503 if (!IOMMU_PTE_PRESENT(*pte)) {
504 page = (u64 *)get_zeroed_page(GFP_KERNEL);
507 *pte = IOMMU_L1_PDE(virt_to_phys(page));
510 pte = IOMMU_PTE_PAGE(*pte);
511 pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)];
513 if (IOMMU_PTE_PRESENT(*pte))
516 __pte = phys_addr | IOMMU_PTE_P;
517 if (prot & IOMMU_PROT_IR)
518 __pte |= IOMMU_PTE_IR;
519 if (prot & IOMMU_PROT_IW)
520 __pte |= IOMMU_PTE_IW;
527 static void iommu_unmap_page(struct protection_domain *dom,
528 unsigned long bus_addr)
532 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
534 if (!IOMMU_PTE_PRESENT(*pte))
537 pte = IOMMU_PTE_PAGE(*pte);
538 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
540 if (!IOMMU_PTE_PRESENT(*pte))
543 pte = IOMMU_PTE_PAGE(*pte);
544 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
550 * This function checks if a specific unity mapping entry is needed for
551 * this specific IOMMU.
553 static int iommu_for_unity_map(struct amd_iommu *iommu,
554 struct unity_map_entry *entry)
558 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
559 bdf = amd_iommu_alias_table[i];
560 if (amd_iommu_rlookup_table[bdf] == iommu)
568 * Init the unity mappings for a specific IOMMU in the system
570 * Basically iterates over all unity mapping entries and applies them to
571 * the default domain DMA of that IOMMU if necessary.
573 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
575 struct unity_map_entry *entry;
578 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
579 if (!iommu_for_unity_map(iommu, entry))
581 ret = dma_ops_unity_map(iommu->default_dom, entry);
590 * This function actually applies the mapping to the page table of the
593 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
594 struct unity_map_entry *e)
599 for (addr = e->address_start; addr < e->address_end;
601 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot);
605 * if unity mapping is in aperture range mark the page
606 * as allocated in the aperture
608 if (addr < dma_dom->aperture_size)
609 __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap);
616 * Inits the unity mappings required for a specific device
618 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
621 struct unity_map_entry *e;
624 list_for_each_entry(e, &amd_iommu_unity_map, list) {
625 if (!(devid >= e->devid_start && devid <= e->devid_end))
627 ret = dma_ops_unity_map(dma_dom, e);
635 /****************************************************************************
637 * The next functions belong to the address allocator for the dma_ops
638 * interface functions. They work like the allocators in the other IOMMU
639 * drivers. Its basically a bitmap which marks the allocated pages in
640 * the aperture. Maybe it could be enhanced in the future to a more
641 * efficient allocator.
643 ****************************************************************************/
646 * The address allocator core function.
648 * called with domain->lock held
650 static unsigned long dma_ops_alloc_addresses(struct device *dev,
651 struct dma_ops_domain *dom,
653 unsigned long align_mask,
657 unsigned long address;
658 unsigned long boundary_size;
660 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
661 PAGE_SIZE) >> PAGE_SHIFT;
662 limit = iommu_device_max_index(dom->aperture_size >> PAGE_SHIFT, 0,
663 dma_mask >> PAGE_SHIFT);
665 if (dom->next_bit >= limit) {
667 dom->need_flush = true;
670 address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages,
671 0 , boundary_size, align_mask);
673 address = iommu_area_alloc(dom->bitmap, limit, 0, pages,
674 0, boundary_size, align_mask);
675 dom->need_flush = true;
678 if (likely(address != -1)) {
679 dom->next_bit = address + pages;
680 address <<= PAGE_SHIFT;
682 address = bad_dma_address;
684 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
690 * The address free function.
692 * called with domain->lock held
694 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
695 unsigned long address,
698 address >>= PAGE_SHIFT;
699 iommu_area_free(dom->bitmap, address, pages);
701 if (address >= dom->next_bit)
702 dom->need_flush = true;
705 /****************************************************************************
707 * The next functions belong to the domain allocation. A domain is
708 * allocated for every IOMMU as the default domain. If device isolation
709 * is enabled, every device get its own domain. The most important thing
710 * about domains is the page table mapping the DMA address space they
713 ****************************************************************************/
715 static u16 domain_id_alloc(void)
720 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
721 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
723 if (id > 0 && id < MAX_DOMAIN_ID)
724 __set_bit(id, amd_iommu_pd_alloc_bitmap);
727 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
732 static void domain_id_free(int id)
736 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
737 if (id > 0 && id < MAX_DOMAIN_ID)
738 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
739 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
743 * Used to reserve address ranges in the aperture (e.g. for exclusion
746 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
747 unsigned long start_page,
750 unsigned int last_page = dom->aperture_size >> PAGE_SHIFT;
752 if (start_page + pages > last_page)
753 pages = last_page - start_page;
755 iommu_area_reserve(dom->bitmap, start_page, pages);
758 static void free_pagetable(struct protection_domain *domain)
763 p1 = domain->pt_root;
768 for (i = 0; i < 512; ++i) {
769 if (!IOMMU_PTE_PRESENT(p1[i]))
772 p2 = IOMMU_PTE_PAGE(p1[i]);
773 for (j = 0; j < 512; ++j) {
774 if (!IOMMU_PTE_PRESENT(p2[j]))
776 p3 = IOMMU_PTE_PAGE(p2[j]);
777 free_page((unsigned long)p3);
780 free_page((unsigned long)p2);
783 free_page((unsigned long)p1);
785 domain->pt_root = NULL;
789 * Free a domain, only used if something went wrong in the
790 * allocation path and we need to free an already allocated page table
792 static void dma_ops_domain_free(struct dma_ops_domain *dom)
797 free_pagetable(&dom->domain);
799 kfree(dom->pte_pages);
807 * Allocates a new protection domain usable for the dma_ops functions.
808 * It also intializes the page table and the address allocator data
809 * structures required for the dma_ops interface
811 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu,
814 struct dma_ops_domain *dma_dom;
815 unsigned i, num_pte_pages;
820 * Currently the DMA aperture must be between 32 MB and 1GB in size
822 if ((order < 25) || (order > 30))
825 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
829 spin_lock_init(&dma_dom->domain.lock);
831 dma_dom->domain.id = domain_id_alloc();
832 if (dma_dom->domain.id == 0)
834 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
835 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
836 dma_dom->domain.flags = PD_DMA_OPS_MASK;
837 dma_dom->domain.priv = dma_dom;
838 if (!dma_dom->domain.pt_root)
840 dma_dom->aperture_size = (1ULL << order);
841 dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8),
843 if (!dma_dom->bitmap)
846 * mark the first page as allocated so we never return 0 as
847 * a valid dma-address. So we can use 0 as error value
849 dma_dom->bitmap[0] = 1;
850 dma_dom->next_bit = 0;
852 dma_dom->need_flush = false;
853 dma_dom->target_dev = 0xffff;
855 /* Intialize the exclusion range if necessary */
856 if (iommu->exclusion_start &&
857 iommu->exclusion_start < dma_dom->aperture_size) {
858 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
859 int pages = iommu_num_pages(iommu->exclusion_start,
860 iommu->exclusion_length,
862 dma_ops_reserve_addresses(dma_dom, startpage, pages);
866 * At the last step, build the page tables so we don't need to
867 * allocate page table pages in the dma_ops mapping/unmapping
870 num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512);
871 dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *),
873 if (!dma_dom->pte_pages)
876 l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL);
880 dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde));
882 for (i = 0; i < num_pte_pages; ++i) {
883 dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL);
884 if (!dma_dom->pte_pages[i])
886 address = virt_to_phys(dma_dom->pte_pages[i]);
887 l2_pde[i] = IOMMU_L1_PDE(address);
893 dma_ops_domain_free(dma_dom);
899 * little helper function to check whether a given protection domain is a
902 static bool dma_ops_domain(struct protection_domain *domain)
904 return domain->flags & PD_DMA_OPS_MASK;
908 * Find out the protection domain structure for a given PCI device. This
909 * will give us the pointer to the page table root for example.
911 static struct protection_domain *domain_for_device(u16 devid)
913 struct protection_domain *dom;
916 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
917 dom = amd_iommu_pd_table[devid];
918 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
924 * If a device is not yet associated with a domain, this function does
925 * assigns it visible for the hardware
927 static void attach_device(struct amd_iommu *iommu,
928 struct protection_domain *domain,
932 u64 pte_root = virt_to_phys(domain->pt_root);
934 domain->dev_cnt += 1;
936 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
937 << DEV_ENTRY_MODE_SHIFT;
938 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
940 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
941 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
942 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
943 amd_iommu_dev_table[devid].data[2] = domain->id;
945 amd_iommu_pd_table[devid] = domain;
946 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
948 iommu_queue_inv_dev_entry(iommu, devid);
952 * Removes a device from a protection domain (unlocked)
954 static void __detach_device(struct protection_domain *domain, u16 devid)
958 spin_lock(&domain->lock);
960 /* remove domain from the lookup table */
961 amd_iommu_pd_table[devid] = NULL;
963 /* remove entry from the device table seen by the hardware */
964 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
965 amd_iommu_dev_table[devid].data[1] = 0;
966 amd_iommu_dev_table[devid].data[2] = 0;
968 /* decrease reference counter */
969 domain->dev_cnt -= 1;
972 spin_unlock(&domain->lock);
976 * Removes a device from a protection domain (with devtable_lock held)
978 static void detach_device(struct protection_domain *domain, u16 devid)
982 /* lock device table */
983 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
984 __detach_device(domain, devid);
985 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
988 static int device_change_notifier(struct notifier_block *nb,
989 unsigned long action, void *data)
991 struct device *dev = data;
992 struct pci_dev *pdev = to_pci_dev(dev);
993 u16 devid = calc_devid(pdev->bus->number, pdev->devfn);
994 struct protection_domain *domain;
995 struct dma_ops_domain *dma_domain;
996 struct amd_iommu *iommu;
997 int order = amd_iommu_aperture_order;
1000 if (devid > amd_iommu_last_bdf)
1003 devid = amd_iommu_alias_table[devid];
1005 iommu = amd_iommu_rlookup_table[devid];
1009 domain = domain_for_device(devid);
1011 if (domain && !dma_ops_domain(domain))
1012 WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound "
1013 "to a non-dma-ops domain\n", dev_name(dev));
1016 case BUS_NOTIFY_BOUND_DRIVER:
1019 dma_domain = find_protection_domain(devid);
1021 dma_domain = iommu->default_dom;
1022 attach_device(iommu, &dma_domain->domain, devid);
1023 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
1024 "device %s\n", dma_domain->domain.id, dev_name(dev));
1026 case BUS_NOTIFY_UNBIND_DRIVER:
1029 detach_device(domain, devid);
1031 case BUS_NOTIFY_ADD_DEVICE:
1032 /* allocate a protection domain if a device is added */
1033 dma_domain = find_protection_domain(devid);
1036 dma_domain = dma_ops_domain_alloc(iommu, order);
1039 dma_domain->target_dev = devid;
1041 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1042 list_add_tail(&dma_domain->list, &iommu_pd_list);
1043 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1050 iommu_queue_inv_dev_entry(iommu, devid);
1051 iommu_completion_wait(iommu);
1057 struct notifier_block device_nb = {
1058 .notifier_call = device_change_notifier,
1061 /*****************************************************************************
1063 * The next functions belong to the dma_ops mapping/unmapping code.
1065 *****************************************************************************/
1068 * This function checks if the driver got a valid device from the caller to
1069 * avoid dereferencing invalid pointers.
1071 static bool check_device(struct device *dev)
1073 if (!dev || !dev->dma_mask)
1080 * In this function the list of preallocated protection domains is traversed to
1081 * find the domain for a specific device
1083 static struct dma_ops_domain *find_protection_domain(u16 devid)
1085 struct dma_ops_domain *entry, *ret = NULL;
1086 unsigned long flags;
1088 if (list_empty(&iommu_pd_list))
1091 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1093 list_for_each_entry(entry, &iommu_pd_list, list) {
1094 if (entry->target_dev == devid) {
1100 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1106 * In the dma_ops path we only have the struct device. This function
1107 * finds the corresponding IOMMU, the protection domain and the
1108 * requestor id for a given device.
1109 * If the device is not yet associated with a domain this is also done
1112 static int get_device_resources(struct device *dev,
1113 struct amd_iommu **iommu,
1114 struct protection_domain **domain,
1117 struct dma_ops_domain *dma_dom;
1118 struct pci_dev *pcidev;
1125 if (dev->bus != &pci_bus_type)
1128 pcidev = to_pci_dev(dev);
1129 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1131 /* device not translated by any IOMMU in the system? */
1132 if (_bdf > amd_iommu_last_bdf)
1135 *bdf = amd_iommu_alias_table[_bdf];
1137 *iommu = amd_iommu_rlookup_table[*bdf];
1140 *domain = domain_for_device(*bdf);
1141 if (*domain == NULL) {
1142 dma_dom = find_protection_domain(*bdf);
1144 dma_dom = (*iommu)->default_dom;
1145 *domain = &dma_dom->domain;
1146 attach_device(*iommu, *domain, *bdf);
1147 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
1148 "device %s\n", (*domain)->id, dev_name(dev));
1151 if (domain_for_device(_bdf) == NULL)
1152 attach_device(*iommu, *domain, _bdf);
1158 * This is the generic map function. It maps one 4kb page at paddr to
1159 * the given address in the DMA address space for the domain.
1161 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
1162 struct dma_ops_domain *dom,
1163 unsigned long address,
1169 WARN_ON(address > dom->aperture_size);
1173 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
1174 pte += IOMMU_PTE_L0_INDEX(address);
1176 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1178 if (direction == DMA_TO_DEVICE)
1179 __pte |= IOMMU_PTE_IR;
1180 else if (direction == DMA_FROM_DEVICE)
1181 __pte |= IOMMU_PTE_IW;
1182 else if (direction == DMA_BIDIRECTIONAL)
1183 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1189 return (dma_addr_t)address;
1193 * The generic unmapping function for on page in the DMA address space.
1195 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
1196 struct dma_ops_domain *dom,
1197 unsigned long address)
1201 if (address >= dom->aperture_size)
1204 WARN_ON(address & ~PAGE_MASK || address >= dom->aperture_size);
1206 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
1207 pte += IOMMU_PTE_L0_INDEX(address);
1215 * This function contains common code for mapping of a physically
1216 * contiguous memory region into DMA address space. It is used by all
1217 * mapping functions provided with this IOMMU driver.
1218 * Must be called with the domain lock held.
1220 static dma_addr_t __map_single(struct device *dev,
1221 struct amd_iommu *iommu,
1222 struct dma_ops_domain *dma_dom,
1229 dma_addr_t offset = paddr & ~PAGE_MASK;
1230 dma_addr_t address, start;
1232 unsigned long align_mask = 0;
1235 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1238 INC_STATS_COUNTER(total_map_requests);
1241 INC_STATS_COUNTER(cross_page);
1244 align_mask = (1UL << get_order(size)) - 1;
1246 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1248 if (unlikely(address == bad_dma_address))
1252 for (i = 0; i < pages; ++i) {
1253 dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
1259 ADD_STATS_COUNTER(alloced_io_mem, size);
1261 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1262 iommu_flush_tlb(iommu, dma_dom->domain.id);
1263 dma_dom->need_flush = false;
1264 } else if (unlikely(iommu_has_npcache(iommu)))
1265 iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
1272 * Does the reverse of the __map_single function. Must be called with
1273 * the domain lock held too
1275 static void __unmap_single(struct amd_iommu *iommu,
1276 struct dma_ops_domain *dma_dom,
1277 dma_addr_t dma_addr,
1281 dma_addr_t i, start;
1284 if ((dma_addr == bad_dma_address) ||
1285 (dma_addr + size > dma_dom->aperture_size))
1288 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1289 dma_addr &= PAGE_MASK;
1292 for (i = 0; i < pages; ++i) {
1293 dma_ops_domain_unmap(iommu, dma_dom, start);
1297 SUB_STATS_COUNTER(alloced_io_mem, size);
1299 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1301 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1302 iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
1303 dma_dom->need_flush = false;
1308 * The exported map_single function for dma_ops.
1310 static dma_addr_t map_page(struct device *dev, struct page *page,
1311 unsigned long offset, size_t size,
1312 enum dma_data_direction dir,
1313 struct dma_attrs *attrs)
1315 unsigned long flags;
1316 struct amd_iommu *iommu;
1317 struct protection_domain *domain;
1321 phys_addr_t paddr = page_to_phys(page) + offset;
1323 INC_STATS_COUNTER(cnt_map_single);
1325 if (!check_device(dev))
1326 return bad_dma_address;
1328 dma_mask = *dev->dma_mask;
1330 get_device_resources(dev, &iommu, &domain, &devid);
1332 if (iommu == NULL || domain == NULL)
1333 /* device not handled by any AMD IOMMU */
1334 return (dma_addr_t)paddr;
1336 if (!dma_ops_domain(domain))
1337 return bad_dma_address;
1339 spin_lock_irqsave(&domain->lock, flags);
1340 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false,
1342 if (addr == bad_dma_address)
1345 iommu_completion_wait(iommu);
1348 spin_unlock_irqrestore(&domain->lock, flags);
1354 * The exported unmap_single function for dma_ops.
1356 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
1357 enum dma_data_direction dir, struct dma_attrs *attrs)
1359 unsigned long flags;
1360 struct amd_iommu *iommu;
1361 struct protection_domain *domain;
1364 INC_STATS_COUNTER(cnt_unmap_single);
1366 if (!check_device(dev) ||
1367 !get_device_resources(dev, &iommu, &domain, &devid))
1368 /* device not handled by any AMD IOMMU */
1371 if (!dma_ops_domain(domain))
1374 spin_lock_irqsave(&domain->lock, flags);
1376 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
1378 iommu_completion_wait(iommu);
1380 spin_unlock_irqrestore(&domain->lock, flags);
1384 * This is a special map_sg function which is used if we should map a
1385 * device which is not handled by an AMD IOMMU in the system.
1387 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1388 int nelems, int dir)
1390 struct scatterlist *s;
1393 for_each_sg(sglist, s, nelems, i) {
1394 s->dma_address = (dma_addr_t)sg_phys(s);
1395 s->dma_length = s->length;
1402 * The exported map_sg function for dma_ops (handles scatter-gather
1405 static int map_sg(struct device *dev, struct scatterlist *sglist,
1406 int nelems, enum dma_data_direction dir,
1407 struct dma_attrs *attrs)
1409 unsigned long flags;
1410 struct amd_iommu *iommu;
1411 struct protection_domain *domain;
1414 struct scatterlist *s;
1416 int mapped_elems = 0;
1419 INC_STATS_COUNTER(cnt_map_sg);
1421 if (!check_device(dev))
1424 dma_mask = *dev->dma_mask;
1426 get_device_resources(dev, &iommu, &domain, &devid);
1428 if (!iommu || !domain)
1429 return map_sg_no_iommu(dev, sglist, nelems, dir);
1431 if (!dma_ops_domain(domain))
1434 spin_lock_irqsave(&domain->lock, flags);
1436 for_each_sg(sglist, s, nelems, i) {
1439 s->dma_address = __map_single(dev, iommu, domain->priv,
1440 paddr, s->length, dir, false,
1443 if (s->dma_address) {
1444 s->dma_length = s->length;
1450 iommu_completion_wait(iommu);
1453 spin_unlock_irqrestore(&domain->lock, flags);
1455 return mapped_elems;
1457 for_each_sg(sglist, s, mapped_elems, i) {
1459 __unmap_single(iommu, domain->priv, s->dma_address,
1460 s->dma_length, dir);
1461 s->dma_address = s->dma_length = 0;
1470 * The exported map_sg function for dma_ops (handles scatter-gather
1473 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1474 int nelems, enum dma_data_direction dir,
1475 struct dma_attrs *attrs)
1477 unsigned long flags;
1478 struct amd_iommu *iommu;
1479 struct protection_domain *domain;
1480 struct scatterlist *s;
1484 INC_STATS_COUNTER(cnt_unmap_sg);
1486 if (!check_device(dev) ||
1487 !get_device_resources(dev, &iommu, &domain, &devid))
1490 if (!dma_ops_domain(domain))
1493 spin_lock_irqsave(&domain->lock, flags);
1495 for_each_sg(sglist, s, nelems, i) {
1496 __unmap_single(iommu, domain->priv, s->dma_address,
1497 s->dma_length, dir);
1498 s->dma_address = s->dma_length = 0;
1501 iommu_completion_wait(iommu);
1503 spin_unlock_irqrestore(&domain->lock, flags);
1507 * The exported alloc_coherent function for dma_ops.
1509 static void *alloc_coherent(struct device *dev, size_t size,
1510 dma_addr_t *dma_addr, gfp_t flag)
1512 unsigned long flags;
1514 struct amd_iommu *iommu;
1515 struct protection_domain *domain;
1518 u64 dma_mask = dev->coherent_dma_mask;
1520 INC_STATS_COUNTER(cnt_alloc_coherent);
1522 if (!check_device(dev))
1525 if (!get_device_resources(dev, &iommu, &domain, &devid))
1526 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
1529 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1533 paddr = virt_to_phys(virt_addr);
1535 if (!iommu || !domain) {
1536 *dma_addr = (dma_addr_t)paddr;
1540 if (!dma_ops_domain(domain))
1544 dma_mask = *dev->dma_mask;
1546 spin_lock_irqsave(&domain->lock, flags);
1548 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1549 size, DMA_BIDIRECTIONAL, true, dma_mask);
1551 if (*dma_addr == bad_dma_address)
1554 iommu_completion_wait(iommu);
1556 spin_unlock_irqrestore(&domain->lock, flags);
1562 free_pages((unsigned long)virt_addr, get_order(size));
1568 * The exported free_coherent function for dma_ops.
1570 static void free_coherent(struct device *dev, size_t size,
1571 void *virt_addr, dma_addr_t dma_addr)
1573 unsigned long flags;
1574 struct amd_iommu *iommu;
1575 struct protection_domain *domain;
1578 INC_STATS_COUNTER(cnt_free_coherent);
1580 if (!check_device(dev))
1583 get_device_resources(dev, &iommu, &domain, &devid);
1585 if (!iommu || !domain)
1588 if (!dma_ops_domain(domain))
1591 spin_lock_irqsave(&domain->lock, flags);
1593 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
1595 iommu_completion_wait(iommu);
1597 spin_unlock_irqrestore(&domain->lock, flags);
1600 free_pages((unsigned long)virt_addr, get_order(size));
1604 * This function is called by the DMA layer to find out if we can handle a
1605 * particular device. It is part of the dma_ops.
1607 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
1610 struct pci_dev *pcidev;
1612 /* No device or no PCI device */
1613 if (!dev || dev->bus != &pci_bus_type)
1616 pcidev = to_pci_dev(dev);
1618 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1620 /* Out of our scope? */
1621 if (bdf > amd_iommu_last_bdf)
1628 * The function for pre-allocating protection domains.
1630 * If the driver core informs the DMA layer if a driver grabs a device
1631 * we don't need to preallocate the protection domains anymore.
1632 * For now we have to.
1634 static void prealloc_protection_domains(void)
1636 struct pci_dev *dev = NULL;
1637 struct dma_ops_domain *dma_dom;
1638 struct amd_iommu *iommu;
1639 int order = amd_iommu_aperture_order;
1642 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1643 devid = calc_devid(dev->bus->number, dev->devfn);
1644 if (devid > amd_iommu_last_bdf)
1646 devid = amd_iommu_alias_table[devid];
1647 if (domain_for_device(devid))
1649 iommu = amd_iommu_rlookup_table[devid];
1652 dma_dom = dma_ops_domain_alloc(iommu, order);
1655 init_unity_mappings_for_device(dma_dom, devid);
1656 dma_dom->target_dev = devid;
1658 list_add_tail(&dma_dom->list, &iommu_pd_list);
1662 static struct dma_map_ops amd_iommu_dma_ops = {
1663 .alloc_coherent = alloc_coherent,
1664 .free_coherent = free_coherent,
1665 .map_page = map_page,
1666 .unmap_page = unmap_page,
1668 .unmap_sg = unmap_sg,
1669 .dma_supported = amd_iommu_dma_supported,
1673 * The function which clues the AMD IOMMU driver into dma_ops.
1675 int __init amd_iommu_init_dma_ops(void)
1677 struct amd_iommu *iommu;
1678 int order = amd_iommu_aperture_order;
1682 * first allocate a default protection domain for every IOMMU we
1683 * found in the system. Devices not assigned to any other
1684 * protection domain will be assigned to the default one.
1686 for_each_iommu(iommu) {
1687 iommu->default_dom = dma_ops_domain_alloc(iommu, order);
1688 if (iommu->default_dom == NULL)
1690 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
1691 ret = iommu_init_unity_mappings(iommu);
1697 * If device isolation is enabled, pre-allocate the protection
1698 * domains for each device.
1700 if (amd_iommu_isolate)
1701 prealloc_protection_domains();
1705 bad_dma_address = 0;
1706 #ifdef CONFIG_GART_IOMMU
1707 gart_iommu_aperture_disabled = 1;
1708 gart_iommu_aperture = 0;
1711 /* Make the driver finally visible to the drivers */
1712 dma_ops = &amd_iommu_dma_ops;
1714 register_iommu(&amd_iommu_ops);
1716 bus_register_notifier(&pci_bus_type, &device_nb);
1718 amd_iommu_stats_init();
1724 for_each_iommu(iommu) {
1725 if (iommu->default_dom)
1726 dma_ops_domain_free(iommu->default_dom);
1732 /*****************************************************************************
1734 * The following functions belong to the exported interface of AMD IOMMU
1736 * This interface allows access to lower level functions of the IOMMU
1737 * like protection domain handling and assignement of devices to domains
1738 * which is not possible with the dma_ops interface.
1740 *****************************************************************************/
1742 static void cleanup_domain(struct protection_domain *domain)
1744 unsigned long flags;
1747 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1749 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1750 if (amd_iommu_pd_table[devid] == domain)
1751 __detach_device(domain, devid);
1753 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1756 static int amd_iommu_domain_init(struct iommu_domain *dom)
1758 struct protection_domain *domain;
1760 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
1764 spin_lock_init(&domain->lock);
1765 domain->mode = PAGE_MODE_3_LEVEL;
1766 domain->id = domain_id_alloc();
1769 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1770 if (!domain->pt_root)
1783 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
1785 struct protection_domain *domain = dom->priv;
1790 if (domain->dev_cnt > 0)
1791 cleanup_domain(domain);
1793 BUG_ON(domain->dev_cnt != 0);
1795 free_pagetable(domain);
1797 domain_id_free(domain->id);
1804 static void amd_iommu_detach_device(struct iommu_domain *dom,
1807 struct protection_domain *domain = dom->priv;
1808 struct amd_iommu *iommu;
1809 struct pci_dev *pdev;
1812 if (dev->bus != &pci_bus_type)
1815 pdev = to_pci_dev(dev);
1817 devid = calc_devid(pdev->bus->number, pdev->devfn);
1820 detach_device(domain, devid);
1822 iommu = amd_iommu_rlookup_table[devid];
1826 iommu_queue_inv_dev_entry(iommu, devid);
1827 iommu_completion_wait(iommu);
1830 static int amd_iommu_attach_device(struct iommu_domain *dom,
1833 struct protection_domain *domain = dom->priv;
1834 struct protection_domain *old_domain;
1835 struct amd_iommu *iommu;
1836 struct pci_dev *pdev;
1839 if (dev->bus != &pci_bus_type)
1842 pdev = to_pci_dev(dev);
1844 devid = calc_devid(pdev->bus->number, pdev->devfn);
1846 if (devid >= amd_iommu_last_bdf ||
1847 devid != amd_iommu_alias_table[devid])
1850 iommu = amd_iommu_rlookup_table[devid];
1854 old_domain = domain_for_device(devid);
1858 attach_device(iommu, domain, devid);
1860 iommu_completion_wait(iommu);
1865 static int amd_iommu_map_range(struct iommu_domain *dom,
1866 unsigned long iova, phys_addr_t paddr,
1867 size_t size, int iommu_prot)
1869 struct protection_domain *domain = dom->priv;
1870 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
1874 if (iommu_prot & IOMMU_READ)
1875 prot |= IOMMU_PROT_IR;
1876 if (iommu_prot & IOMMU_WRITE)
1877 prot |= IOMMU_PROT_IW;
1882 for (i = 0; i < npages; ++i) {
1883 ret = iommu_map_page(domain, iova, paddr, prot);
1894 static void amd_iommu_unmap_range(struct iommu_domain *dom,
1895 unsigned long iova, size_t size)
1898 struct protection_domain *domain = dom->priv;
1899 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
1903 for (i = 0; i < npages; ++i) {
1904 iommu_unmap_page(domain, iova);
1908 iommu_flush_domain(domain->id);
1911 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
1914 struct protection_domain *domain = dom->priv;
1915 unsigned long offset = iova & ~PAGE_MASK;
1919 pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)];
1921 if (!IOMMU_PTE_PRESENT(*pte))
1924 pte = IOMMU_PTE_PAGE(*pte);
1925 pte = &pte[IOMMU_PTE_L1_INDEX(iova)];
1927 if (!IOMMU_PTE_PRESENT(*pte))
1930 pte = IOMMU_PTE_PAGE(*pte);
1931 pte = &pte[IOMMU_PTE_L0_INDEX(iova)];
1933 if (!IOMMU_PTE_PRESENT(*pte))
1936 paddr = *pte & IOMMU_PAGE_MASK;
1942 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
1948 static struct iommu_ops amd_iommu_ops = {
1949 .domain_init = amd_iommu_domain_init,
1950 .domain_destroy = amd_iommu_domain_destroy,
1951 .attach_dev = amd_iommu_attach_device,
1952 .detach_dev = amd_iommu_detach_device,
1953 .map = amd_iommu_map_range,
1954 .unmap = amd_iommu_unmap_range,
1955 .iova_to_phys = amd_iommu_iova_to_phys,
1956 .domain_has_cap = amd_iommu_domain_has_cap,