2 * Copyright (C) 2007-2009 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/iommu-helper.h>
27 #include <linux/iommu.h>
28 #include <asm/proto.h>
29 #include <asm/iommu.h>
31 #include <asm/amd_iommu_proto.h>
32 #include <asm/amd_iommu_types.h>
33 #include <asm/amd_iommu.h>
35 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
37 #define EXIT_LOOP_COUNT 10000000
39 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
41 /* A list of preallocated protection domains */
42 static LIST_HEAD(iommu_pd_list);
43 static DEFINE_SPINLOCK(iommu_pd_list_lock);
46 * Domain for untranslated devices - only allocated
47 * if iommu=pt passed on kernel cmd line.
49 static struct protection_domain *pt_domain;
51 static struct iommu_ops amd_iommu_ops;
54 * general struct to manage commands send to an IOMMU
60 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
61 struct unity_map_entry *e);
62 static struct dma_ops_domain *find_protection_domain(u16 devid);
63 static u64 *alloc_pte(struct protection_domain *domain,
64 unsigned long address, int end_lvl,
65 u64 **pte_page, gfp_t gfp);
66 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
67 unsigned long start_page,
69 static void reset_iommu_command_buffer(struct amd_iommu *iommu);
70 static u64 *fetch_pte(struct protection_domain *domain,
71 unsigned long address, int map_size);
72 static void update_domain(struct protection_domain *domain);
74 #ifdef CONFIG_AMD_IOMMU_STATS
77 * Initialization code for statistics collection
80 DECLARE_STATS_COUNTER(compl_wait);
81 DECLARE_STATS_COUNTER(cnt_map_single);
82 DECLARE_STATS_COUNTER(cnt_unmap_single);
83 DECLARE_STATS_COUNTER(cnt_map_sg);
84 DECLARE_STATS_COUNTER(cnt_unmap_sg);
85 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
86 DECLARE_STATS_COUNTER(cnt_free_coherent);
87 DECLARE_STATS_COUNTER(cross_page);
88 DECLARE_STATS_COUNTER(domain_flush_single);
89 DECLARE_STATS_COUNTER(domain_flush_all);
90 DECLARE_STATS_COUNTER(alloced_io_mem);
91 DECLARE_STATS_COUNTER(total_map_requests);
93 static struct dentry *stats_dir;
94 static struct dentry *de_isolate;
95 static struct dentry *de_fflush;
97 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
99 if (stats_dir == NULL)
102 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
106 static void amd_iommu_stats_init(void)
108 stats_dir = debugfs_create_dir("amd-iommu", NULL);
109 if (stats_dir == NULL)
112 de_isolate = debugfs_create_bool("isolation", 0444, stats_dir,
113 (u32 *)&amd_iommu_isolate);
115 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
116 (u32 *)&amd_iommu_unmap_flush);
118 amd_iommu_stats_add(&compl_wait);
119 amd_iommu_stats_add(&cnt_map_single);
120 amd_iommu_stats_add(&cnt_unmap_single);
121 amd_iommu_stats_add(&cnt_map_sg);
122 amd_iommu_stats_add(&cnt_unmap_sg);
123 amd_iommu_stats_add(&cnt_alloc_coherent);
124 amd_iommu_stats_add(&cnt_free_coherent);
125 amd_iommu_stats_add(&cross_page);
126 amd_iommu_stats_add(&domain_flush_single);
127 amd_iommu_stats_add(&domain_flush_all);
128 amd_iommu_stats_add(&alloced_io_mem);
129 amd_iommu_stats_add(&total_map_requests);
134 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
135 static int iommu_has_npcache(struct amd_iommu *iommu)
137 return iommu->cap & (1UL << IOMMU_CAP_NPCACHE);
140 /****************************************************************************
142 * Interrupt handling functions
144 ****************************************************************************/
146 static void dump_dte_entry(u16 devid)
150 for (i = 0; i < 8; ++i)
151 pr_err("AMD-Vi: DTE[%d]: %08x\n", i,
152 amd_iommu_dev_table[devid].data[i]);
155 static void dump_command(unsigned long phys_addr)
157 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
160 for (i = 0; i < 4; ++i)
161 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
164 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
167 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
168 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
169 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
170 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
171 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
173 printk(KERN_ERR "AMD-Vi: Event logged [");
176 case EVENT_TYPE_ILL_DEV:
177 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
178 "address=0x%016llx flags=0x%04x]\n",
179 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
181 dump_dte_entry(devid);
183 case EVENT_TYPE_IO_FAULT:
184 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
185 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
186 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
187 domid, address, flags);
189 case EVENT_TYPE_DEV_TAB_ERR:
190 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
191 "address=0x%016llx flags=0x%04x]\n",
192 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
195 case EVENT_TYPE_PAGE_TAB_ERR:
196 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
197 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
198 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
199 domid, address, flags);
201 case EVENT_TYPE_ILL_CMD:
202 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
203 reset_iommu_command_buffer(iommu);
204 dump_command(address);
206 case EVENT_TYPE_CMD_HARD_ERR:
207 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
208 "flags=0x%04x]\n", address, flags);
210 case EVENT_TYPE_IOTLB_INV_TO:
211 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
212 "address=0x%016llx]\n",
213 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
216 case EVENT_TYPE_INV_DEV_REQ:
217 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
218 "address=0x%016llx flags=0x%04x]\n",
219 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
223 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
227 static void iommu_poll_events(struct amd_iommu *iommu)
232 spin_lock_irqsave(&iommu->lock, flags);
234 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
235 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
237 while (head != tail) {
238 iommu_print_event(iommu, iommu->evt_buf + head);
239 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
242 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
244 spin_unlock_irqrestore(&iommu->lock, flags);
247 irqreturn_t amd_iommu_int_handler(int irq, void *data)
249 struct amd_iommu *iommu;
251 for_each_iommu(iommu)
252 iommu_poll_events(iommu);
257 /****************************************************************************
259 * IOMMU command queuing functions
261 ****************************************************************************/
264 * Writes the command to the IOMMUs command buffer and informs the
265 * hardware about the new command. Must be called with iommu->lock held.
267 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
272 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
273 target = iommu->cmd_buf + tail;
274 memcpy_toio(target, cmd, sizeof(*cmd));
275 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
276 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
279 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
285 * General queuing function for commands. Takes iommu->lock and calls
286 * __iommu_queue_command().
288 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
293 spin_lock_irqsave(&iommu->lock, flags);
294 ret = __iommu_queue_command(iommu, cmd);
296 iommu->need_sync = true;
297 spin_unlock_irqrestore(&iommu->lock, flags);
303 * This function waits until an IOMMU has completed a completion
306 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
312 INC_STATS_COUNTER(compl_wait);
314 while (!ready && (i < EXIT_LOOP_COUNT)) {
316 /* wait for the bit to become one */
317 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
318 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
321 /* set bit back to zero */
322 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
323 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
325 if (unlikely(i == EXIT_LOOP_COUNT)) {
326 spin_unlock(&iommu->lock);
327 reset_iommu_command_buffer(iommu);
328 spin_lock(&iommu->lock);
333 * This function queues a completion wait command into the command
336 static int __iommu_completion_wait(struct amd_iommu *iommu)
338 struct iommu_cmd cmd;
340 memset(&cmd, 0, sizeof(cmd));
341 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
342 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
344 return __iommu_queue_command(iommu, &cmd);
348 * This function is called whenever we need to ensure that the IOMMU has
349 * completed execution of all commands we sent. It sends a
350 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
351 * us about that by writing a value to a physical address we pass with
354 static int iommu_completion_wait(struct amd_iommu *iommu)
359 spin_lock_irqsave(&iommu->lock, flags);
361 if (!iommu->need_sync)
364 ret = __iommu_completion_wait(iommu);
366 iommu->need_sync = false;
371 __iommu_wait_for_completion(iommu);
374 spin_unlock_irqrestore(&iommu->lock, flags);
379 static void iommu_flush_complete(struct protection_domain *domain)
383 for (i = 0; i < amd_iommus_present; ++i) {
384 if (!domain->dev_iommu[i])
388 * Devices of this domain are behind this IOMMU
389 * We need to wait for completion of all commands.
391 iommu_completion_wait(amd_iommus[i]);
396 * Command send function for invalidating a device table entry
398 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
400 struct iommu_cmd cmd;
403 BUG_ON(iommu == NULL);
405 memset(&cmd, 0, sizeof(cmd));
406 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
409 ret = iommu_queue_command(iommu, &cmd);
414 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
415 u16 domid, int pde, int s)
417 memset(cmd, 0, sizeof(*cmd));
418 address &= PAGE_MASK;
419 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
420 cmd->data[1] |= domid;
421 cmd->data[2] = lower_32_bits(address);
422 cmd->data[3] = upper_32_bits(address);
423 if (s) /* size bit - we flush more than one 4kb page */
424 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
425 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
426 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
430 * Generic command send function for invalidaing TLB entries
432 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
433 u64 address, u16 domid, int pde, int s)
435 struct iommu_cmd cmd;
438 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
440 ret = iommu_queue_command(iommu, &cmd);
446 * TLB invalidation function which is called from the mapping functions.
447 * It invalidates a single PTE if the range to flush is within a single
448 * page. Otherwise it flushes the whole TLB of the IOMMU.
450 static void __iommu_flush_pages(struct protection_domain *domain,
451 u64 address, size_t size, int pde)
454 unsigned pages = iommu_num_pages(address, size, PAGE_SIZE);
456 address &= PAGE_MASK;
460 * If we have to flush more than one page, flush all
461 * TLB entries for this domain
463 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
468 for (i = 0; i < amd_iommus_present; ++i) {
469 if (!domain->dev_iommu[i])
473 * Devices of this domain are behind this IOMMU
474 * We need a TLB flush
476 iommu_queue_inv_iommu_pages(amd_iommus[i], address,
483 static void iommu_flush_pages(struct protection_domain *domain,
484 u64 address, size_t size)
486 __iommu_flush_pages(domain, address, size, 0);
489 /* Flush the whole IO/TLB for a given protection domain */
490 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
492 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
494 INC_STATS_COUNTER(domain_flush_single);
496 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
499 /* Flush the whole IO/TLB for a given protection domain - including PDE */
500 static void iommu_flush_tlb_pde(struct amd_iommu *iommu, u16 domid)
502 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
504 INC_STATS_COUNTER(domain_flush_single);
506 iommu_queue_inv_iommu_pages(iommu, address, domid, 1, 1);
510 * This function flushes one domain on one IOMMU
512 static void flush_domain_on_iommu(struct amd_iommu *iommu, u16 domid)
514 struct iommu_cmd cmd;
517 __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
520 spin_lock_irqsave(&iommu->lock, flags);
521 __iommu_queue_command(iommu, &cmd);
522 __iommu_completion_wait(iommu);
523 __iommu_wait_for_completion(iommu);
524 spin_unlock_irqrestore(&iommu->lock, flags);
527 static void flush_all_domains_on_iommu(struct amd_iommu *iommu)
531 for (i = 1; i < MAX_DOMAIN_ID; ++i) {
532 if (!test_bit(i, amd_iommu_pd_alloc_bitmap))
534 flush_domain_on_iommu(iommu, i);
540 * This function is used to flush the IO/TLB for a given protection domain
541 * on every IOMMU in the system
543 static void iommu_flush_domain(u16 domid)
545 struct amd_iommu *iommu;
547 INC_STATS_COUNTER(domain_flush_all);
549 for_each_iommu(iommu)
550 flush_domain_on_iommu(iommu, domid);
553 void amd_iommu_flush_all_domains(void)
555 struct amd_iommu *iommu;
557 for_each_iommu(iommu)
558 flush_all_domains_on_iommu(iommu);
561 static void flush_all_devices_for_iommu(struct amd_iommu *iommu)
565 for (i = 0; i <= amd_iommu_last_bdf; ++i) {
566 if (iommu != amd_iommu_rlookup_table[i])
569 iommu_queue_inv_dev_entry(iommu, i);
570 iommu_completion_wait(iommu);
574 static void flush_devices_by_domain(struct protection_domain *domain)
576 struct amd_iommu *iommu;
579 for (i = 0; i <= amd_iommu_last_bdf; ++i) {
580 if ((domain == NULL && amd_iommu_pd_table[i] == NULL) ||
581 (amd_iommu_pd_table[i] != domain))
584 iommu = amd_iommu_rlookup_table[i];
588 iommu_queue_inv_dev_entry(iommu, i);
589 iommu_completion_wait(iommu);
593 static void reset_iommu_command_buffer(struct amd_iommu *iommu)
595 pr_err("AMD-Vi: Resetting IOMMU command buffer\n");
597 if (iommu->reset_in_progress)
598 panic("AMD-Vi: ILLEGAL_COMMAND_ERROR while resetting command buffer\n");
600 iommu->reset_in_progress = true;
602 amd_iommu_reset_cmd_buffer(iommu);
603 flush_all_devices_for_iommu(iommu);
604 flush_all_domains_on_iommu(iommu);
606 iommu->reset_in_progress = false;
609 void amd_iommu_flush_all_devices(void)
611 flush_devices_by_domain(NULL);
614 /****************************************************************************
616 * The functions below are used the create the page table mappings for
617 * unity mapped regions.
619 ****************************************************************************/
622 * Generic mapping functions. It maps a physical address into a DMA
623 * address space. It allocates the page table pages if necessary.
624 * In the future it can be extended to a generic mapping function
625 * supporting all features of AMD IOMMU page tables like level skipping
626 * and full 64 bit address spaces.
628 static int iommu_map_page(struct protection_domain *dom,
629 unsigned long bus_addr,
630 unsigned long phys_addr,
636 bus_addr = PAGE_ALIGN(bus_addr);
637 phys_addr = PAGE_ALIGN(phys_addr);
639 BUG_ON(!PM_ALIGNED(map_size, bus_addr));
640 BUG_ON(!PM_ALIGNED(map_size, phys_addr));
642 if (!(prot & IOMMU_PROT_MASK))
645 pte = alloc_pte(dom, bus_addr, map_size, NULL, GFP_KERNEL);
647 if (IOMMU_PTE_PRESENT(*pte))
650 __pte = phys_addr | IOMMU_PTE_P;
651 if (prot & IOMMU_PROT_IR)
652 __pte |= IOMMU_PTE_IR;
653 if (prot & IOMMU_PROT_IW)
654 __pte |= IOMMU_PTE_IW;
663 static void iommu_unmap_page(struct protection_domain *dom,
664 unsigned long bus_addr, int map_size)
666 u64 *pte = fetch_pte(dom, bus_addr, map_size);
673 * This function checks if a specific unity mapping entry is needed for
674 * this specific IOMMU.
676 static int iommu_for_unity_map(struct amd_iommu *iommu,
677 struct unity_map_entry *entry)
681 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
682 bdf = amd_iommu_alias_table[i];
683 if (amd_iommu_rlookup_table[bdf] == iommu)
691 * Init the unity mappings for a specific IOMMU in the system
693 * Basically iterates over all unity mapping entries and applies them to
694 * the default domain DMA of that IOMMU if necessary.
696 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
698 struct unity_map_entry *entry;
701 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
702 if (!iommu_for_unity_map(iommu, entry))
704 ret = dma_ops_unity_map(iommu->default_dom, entry);
713 * This function actually applies the mapping to the page table of the
716 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
717 struct unity_map_entry *e)
722 for (addr = e->address_start; addr < e->address_end;
724 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
729 * if unity mapping is in aperture range mark the page
730 * as allocated in the aperture
732 if (addr < dma_dom->aperture_size)
733 __set_bit(addr >> PAGE_SHIFT,
734 dma_dom->aperture[0]->bitmap);
741 * Inits the unity mappings required for a specific device
743 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
746 struct unity_map_entry *e;
749 list_for_each_entry(e, &amd_iommu_unity_map, list) {
750 if (!(devid >= e->devid_start && devid <= e->devid_end))
752 ret = dma_ops_unity_map(dma_dom, e);
760 /****************************************************************************
762 * The next functions belong to the address allocator for the dma_ops
763 * interface functions. They work like the allocators in the other IOMMU
764 * drivers. Its basically a bitmap which marks the allocated pages in
765 * the aperture. Maybe it could be enhanced in the future to a more
766 * efficient allocator.
768 ****************************************************************************/
771 * The address allocator core functions.
773 * called with domain->lock held
777 * This function checks if there is a PTE for a given dma address. If
778 * there is one, it returns the pointer to it.
780 static u64 *fetch_pte(struct protection_domain *domain,
781 unsigned long address, int map_size)
786 level = domain->mode - 1;
787 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
789 while (level > map_size) {
790 if (!IOMMU_PTE_PRESENT(*pte))
795 pte = IOMMU_PTE_PAGE(*pte);
796 pte = &pte[PM_LEVEL_INDEX(level, address)];
798 if ((PM_PTE_LEVEL(*pte) == 0) && level != map_size) {
808 * This function is used to add a new aperture range to an existing
809 * aperture in case of dma_ops domain allocation or address allocation
812 static int alloc_new_range(struct amd_iommu *iommu,
813 struct dma_ops_domain *dma_dom,
814 bool populate, gfp_t gfp)
816 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
819 #ifdef CONFIG_IOMMU_STRESS
823 if (index >= APERTURE_MAX_RANGES)
826 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
827 if (!dma_dom->aperture[index])
830 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
831 if (!dma_dom->aperture[index]->bitmap)
834 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
837 unsigned long address = dma_dom->aperture_size;
838 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
841 for (i = 0; i < num_ptes; ++i) {
842 pte = alloc_pte(&dma_dom->domain, address, PM_MAP_4k,
847 dma_dom->aperture[index]->pte_pages[i] = pte_page;
849 address += APERTURE_RANGE_SIZE / 64;
853 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
855 /* Intialize the exclusion range if necessary */
856 if (iommu->exclusion_start &&
857 iommu->exclusion_start >= dma_dom->aperture[index]->offset &&
858 iommu->exclusion_start < dma_dom->aperture_size) {
859 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
860 int pages = iommu_num_pages(iommu->exclusion_start,
861 iommu->exclusion_length,
863 dma_ops_reserve_addresses(dma_dom, startpage, pages);
867 * Check for areas already mapped as present in the new aperture
868 * range and mark those pages as reserved in the allocator. Such
869 * mappings may already exist as a result of requested unity
870 * mappings for devices.
872 for (i = dma_dom->aperture[index]->offset;
873 i < dma_dom->aperture_size;
875 u64 *pte = fetch_pte(&dma_dom->domain, i, PM_MAP_4k);
876 if (!pte || !IOMMU_PTE_PRESENT(*pte))
879 dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1);
882 update_domain(&dma_dom->domain);
887 update_domain(&dma_dom->domain);
889 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
891 kfree(dma_dom->aperture[index]);
892 dma_dom->aperture[index] = NULL;
897 static unsigned long dma_ops_area_alloc(struct device *dev,
898 struct dma_ops_domain *dom,
900 unsigned long align_mask,
904 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
905 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
906 int i = start >> APERTURE_RANGE_SHIFT;
907 unsigned long boundary_size;
908 unsigned long address = -1;
911 next_bit >>= PAGE_SHIFT;
913 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
914 PAGE_SIZE) >> PAGE_SHIFT;
916 for (;i < max_index; ++i) {
917 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
919 if (dom->aperture[i]->offset >= dma_mask)
922 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
923 dma_mask >> PAGE_SHIFT);
925 address = iommu_area_alloc(dom->aperture[i]->bitmap,
926 limit, next_bit, pages, 0,
927 boundary_size, align_mask);
929 address = dom->aperture[i]->offset +
930 (address << PAGE_SHIFT);
931 dom->next_address = address + (pages << PAGE_SHIFT);
941 static unsigned long dma_ops_alloc_addresses(struct device *dev,
942 struct dma_ops_domain *dom,
944 unsigned long align_mask,
947 unsigned long address;
949 #ifdef CONFIG_IOMMU_STRESS
950 dom->next_address = 0;
951 dom->need_flush = true;
954 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
955 dma_mask, dom->next_address);
958 dom->next_address = 0;
959 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
961 dom->need_flush = true;
964 if (unlikely(address == -1))
965 address = DMA_ERROR_CODE;
967 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
973 * The address free function.
975 * called with domain->lock held
977 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
978 unsigned long address,
981 unsigned i = address >> APERTURE_RANGE_SHIFT;
982 struct aperture_range *range = dom->aperture[i];
984 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
986 #ifdef CONFIG_IOMMU_STRESS
991 if (address >= dom->next_address)
992 dom->need_flush = true;
994 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
996 iommu_area_free(range->bitmap, address, pages);
1000 /****************************************************************************
1002 * The next functions belong to the domain allocation. A domain is
1003 * allocated for every IOMMU as the default domain. If device isolation
1004 * is enabled, every device get its own domain. The most important thing
1005 * about domains is the page table mapping the DMA address space they
1008 ****************************************************************************/
1010 static u16 domain_id_alloc(void)
1012 unsigned long flags;
1015 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1016 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1018 if (id > 0 && id < MAX_DOMAIN_ID)
1019 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1022 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1027 static void domain_id_free(int id)
1029 unsigned long flags;
1031 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1032 if (id > 0 && id < MAX_DOMAIN_ID)
1033 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1034 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1038 * Used to reserve address ranges in the aperture (e.g. for exclusion
1041 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1042 unsigned long start_page,
1045 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1047 if (start_page + pages > last_page)
1048 pages = last_page - start_page;
1050 for (i = start_page; i < start_page + pages; ++i) {
1051 int index = i / APERTURE_RANGE_PAGES;
1052 int page = i % APERTURE_RANGE_PAGES;
1053 __set_bit(page, dom->aperture[index]->bitmap);
1057 static void free_pagetable(struct protection_domain *domain)
1062 p1 = domain->pt_root;
1067 for (i = 0; i < 512; ++i) {
1068 if (!IOMMU_PTE_PRESENT(p1[i]))
1071 p2 = IOMMU_PTE_PAGE(p1[i]);
1072 for (j = 0; j < 512; ++j) {
1073 if (!IOMMU_PTE_PRESENT(p2[j]))
1075 p3 = IOMMU_PTE_PAGE(p2[j]);
1076 free_page((unsigned long)p3);
1079 free_page((unsigned long)p2);
1082 free_page((unsigned long)p1);
1084 domain->pt_root = NULL;
1088 * Free a domain, only used if something went wrong in the
1089 * allocation path and we need to free an already allocated page table
1091 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1098 free_pagetable(&dom->domain);
1100 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1101 if (!dom->aperture[i])
1103 free_page((unsigned long)dom->aperture[i]->bitmap);
1104 kfree(dom->aperture[i]);
1111 * Allocates a new protection domain usable for the dma_ops functions.
1112 * It also intializes the page table and the address allocator data
1113 * structures required for the dma_ops interface
1115 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu)
1117 struct dma_ops_domain *dma_dom;
1119 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1123 spin_lock_init(&dma_dom->domain.lock);
1125 dma_dom->domain.id = domain_id_alloc();
1126 if (dma_dom->domain.id == 0)
1128 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
1129 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1130 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1131 dma_dom->domain.priv = dma_dom;
1132 if (!dma_dom->domain.pt_root)
1135 dma_dom->need_flush = false;
1136 dma_dom->target_dev = 0xffff;
1138 if (alloc_new_range(iommu, dma_dom, true, GFP_KERNEL))
1142 * mark the first page as allocated so we never return 0 as
1143 * a valid dma-address. So we can use 0 as error value
1145 dma_dom->aperture[0]->bitmap[0] = 1;
1146 dma_dom->next_address = 0;
1152 dma_ops_domain_free(dma_dom);
1158 * little helper function to check whether a given protection domain is a
1161 static bool dma_ops_domain(struct protection_domain *domain)
1163 return domain->flags & PD_DMA_OPS_MASK;
1167 * Find out the protection domain structure for a given PCI device. This
1168 * will give us the pointer to the page table root for example.
1170 static struct protection_domain *domain_for_device(u16 devid)
1172 struct protection_domain *dom;
1173 unsigned long flags;
1175 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
1176 dom = amd_iommu_pd_table[devid];
1177 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1182 static void set_dte_entry(u16 devid, struct protection_domain *domain)
1184 u64 pte_root = virt_to_phys(domain->pt_root);
1186 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1187 << DEV_ENTRY_MODE_SHIFT;
1188 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1190 amd_iommu_dev_table[devid].data[2] = domain->id;
1191 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
1192 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
1194 amd_iommu_pd_table[devid] = domain;
1198 * If a device is not yet associated with a domain, this function does
1199 * assigns it visible for the hardware
1201 static void __attach_device(struct amd_iommu *iommu,
1202 struct protection_domain *domain,
1206 spin_lock(&domain->lock);
1208 /* update DTE entry */
1209 set_dte_entry(devid, domain);
1211 /* Do reference counting */
1212 domain->dev_iommu[iommu->index] += 1;
1213 domain->dev_cnt += 1;
1216 spin_unlock(&domain->lock);
1220 * If a device is not yet associated with a domain, this function does
1221 * assigns it visible for the hardware
1223 static void attach_device(struct amd_iommu *iommu,
1224 struct protection_domain *domain,
1227 unsigned long flags;
1229 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1230 __attach_device(iommu, domain, devid);
1231 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1234 * We might boot into a crash-kernel here. The crashed kernel
1235 * left the caches in the IOMMU dirty. So we have to flush
1236 * here to evict all dirty stuff.
1238 iommu_queue_inv_dev_entry(iommu, devid);
1239 iommu_flush_tlb_pde(iommu, domain->id);
1243 * Removes a device from a protection domain (unlocked)
1245 static void __detach_device(struct protection_domain *domain, u16 devid)
1247 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1252 spin_lock(&domain->lock);
1254 /* remove domain from the lookup table */
1255 amd_iommu_pd_table[devid] = NULL;
1257 /* remove entry from the device table seen by the hardware */
1258 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1259 amd_iommu_dev_table[devid].data[1] = 0;
1260 amd_iommu_dev_table[devid].data[2] = 0;
1262 amd_iommu_apply_erratum_63(devid);
1264 /* decrease reference counters */
1265 domain->dev_iommu[iommu->index] -= 1;
1266 domain->dev_cnt -= 1;
1269 spin_unlock(&domain->lock);
1272 * If we run in passthrough mode the device must be assigned to the
1273 * passthrough domain if it is detached from any other domain
1275 if (iommu_pass_through) {
1276 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1277 __attach_device(iommu, pt_domain, devid);
1282 * Removes a device from a protection domain (with devtable_lock held)
1284 static void detach_device(struct protection_domain *domain, u16 devid)
1286 unsigned long flags;
1288 /* lock device table */
1289 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1290 __detach_device(domain, devid);
1291 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1294 static int device_change_notifier(struct notifier_block *nb,
1295 unsigned long action, void *data)
1297 struct device *dev = data;
1298 struct pci_dev *pdev = to_pci_dev(dev);
1299 u16 devid = calc_devid(pdev->bus->number, pdev->devfn);
1300 struct protection_domain *domain;
1301 struct dma_ops_domain *dma_domain;
1302 struct amd_iommu *iommu;
1303 unsigned long flags;
1305 if (devid > amd_iommu_last_bdf)
1308 devid = amd_iommu_alias_table[devid];
1310 iommu = amd_iommu_rlookup_table[devid];
1314 domain = domain_for_device(devid);
1316 if (domain && !dma_ops_domain(domain))
1317 WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound "
1318 "to a non-dma-ops domain\n", dev_name(dev));
1321 case BUS_NOTIFY_UNBOUND_DRIVER:
1324 if (iommu_pass_through)
1326 detach_device(domain, devid);
1328 case BUS_NOTIFY_ADD_DEVICE:
1329 /* allocate a protection domain if a device is added */
1330 dma_domain = find_protection_domain(devid);
1333 dma_domain = dma_ops_domain_alloc(iommu);
1336 dma_domain->target_dev = devid;
1338 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1339 list_add_tail(&dma_domain->list, &iommu_pd_list);
1340 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1347 iommu_queue_inv_dev_entry(iommu, devid);
1348 iommu_completion_wait(iommu);
1354 static struct notifier_block device_nb = {
1355 .notifier_call = device_change_notifier,
1358 /*****************************************************************************
1360 * The next functions belong to the dma_ops mapping/unmapping code.
1362 *****************************************************************************/
1365 * This function checks if the driver got a valid device from the caller to
1366 * avoid dereferencing invalid pointers.
1368 static bool check_device(struct device *dev)
1370 if (!dev || !dev->dma_mask)
1377 * In this function the list of preallocated protection domains is traversed to
1378 * find the domain for a specific device
1380 static struct dma_ops_domain *find_protection_domain(u16 devid)
1382 struct dma_ops_domain *entry, *ret = NULL;
1383 unsigned long flags;
1385 if (list_empty(&iommu_pd_list))
1388 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1390 list_for_each_entry(entry, &iommu_pd_list, list) {
1391 if (entry->target_dev == devid) {
1397 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1403 * In the dma_ops path we only have the struct device. This function
1404 * finds the corresponding IOMMU, the protection domain and the
1405 * requestor id for a given device.
1406 * If the device is not yet associated with a domain this is also done
1409 static int get_device_resources(struct device *dev,
1410 struct amd_iommu **iommu,
1411 struct protection_domain **domain,
1414 struct dma_ops_domain *dma_dom;
1415 struct pci_dev *pcidev;
1422 if (dev->bus != &pci_bus_type)
1425 pcidev = to_pci_dev(dev);
1426 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1428 /* device not translated by any IOMMU in the system? */
1429 if (_bdf > amd_iommu_last_bdf)
1432 *bdf = amd_iommu_alias_table[_bdf];
1434 *iommu = amd_iommu_rlookup_table[*bdf];
1437 *domain = domain_for_device(*bdf);
1438 if (*domain == NULL) {
1439 dma_dom = find_protection_domain(*bdf);
1441 dma_dom = (*iommu)->default_dom;
1442 *domain = &dma_dom->domain;
1443 attach_device(*iommu, *domain, *bdf);
1444 DUMP_printk("Using protection domain %d for device %s\n",
1445 (*domain)->id, dev_name(dev));
1448 if (domain_for_device(_bdf) == NULL)
1449 attach_device(*iommu, *domain, _bdf);
1454 static void update_device_table(struct protection_domain *domain)
1456 unsigned long flags;
1459 for (i = 0; i <= amd_iommu_last_bdf; ++i) {
1460 if (amd_iommu_pd_table[i] != domain)
1462 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1463 set_dte_entry(i, domain);
1464 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1468 static void update_domain(struct protection_domain *domain)
1470 if (!domain->updated)
1473 update_device_table(domain);
1474 flush_devices_by_domain(domain);
1475 iommu_flush_domain(domain->id);
1477 domain->updated = false;
1481 * This function is used to add another level to an IO page table. Adding
1482 * another level increases the size of the address space by 9 bits to a size up
1485 static bool increase_address_space(struct protection_domain *domain,
1490 if (domain->mode == PAGE_MODE_6_LEVEL)
1491 /* address space already 64 bit large */
1494 pte = (void *)get_zeroed_page(gfp);
1498 *pte = PM_LEVEL_PDE(domain->mode,
1499 virt_to_phys(domain->pt_root));
1500 domain->pt_root = pte;
1502 domain->updated = true;
1507 static u64 *alloc_pte(struct protection_domain *domain,
1508 unsigned long address,
1516 while (address > PM_LEVEL_SIZE(domain->mode))
1517 increase_address_space(domain, gfp);
1519 level = domain->mode - 1;
1520 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1522 while (level > end_lvl) {
1523 if (!IOMMU_PTE_PRESENT(*pte)) {
1524 page = (u64 *)get_zeroed_page(gfp);
1527 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
1532 pte = IOMMU_PTE_PAGE(*pte);
1534 if (pte_page && level == end_lvl)
1537 pte = &pte[PM_LEVEL_INDEX(level, address)];
1544 * This function fetches the PTE for a given address in the aperture
1546 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
1547 unsigned long address)
1549 struct aperture_range *aperture;
1550 u64 *pte, *pte_page;
1552 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1556 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1558 pte = alloc_pte(&dom->domain, address, PM_MAP_4k, &pte_page,
1560 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
1562 pte += PM_LEVEL_INDEX(0, address);
1564 update_domain(&dom->domain);
1570 * This is the generic map function. It maps one 4kb page at paddr to
1571 * the given address in the DMA address space for the domain.
1573 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
1574 struct dma_ops_domain *dom,
1575 unsigned long address,
1581 WARN_ON(address > dom->aperture_size);
1585 pte = dma_ops_get_pte(dom, address);
1587 return DMA_ERROR_CODE;
1589 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1591 if (direction == DMA_TO_DEVICE)
1592 __pte |= IOMMU_PTE_IR;
1593 else if (direction == DMA_FROM_DEVICE)
1594 __pte |= IOMMU_PTE_IW;
1595 else if (direction == DMA_BIDIRECTIONAL)
1596 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1602 return (dma_addr_t)address;
1606 * The generic unmapping function for on page in the DMA address space.
1608 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
1609 struct dma_ops_domain *dom,
1610 unsigned long address)
1612 struct aperture_range *aperture;
1615 if (address >= dom->aperture_size)
1618 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1622 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1626 pte += PM_LEVEL_INDEX(0, address);
1634 * This function contains common code for mapping of a physically
1635 * contiguous memory region into DMA address space. It is used by all
1636 * mapping functions provided with this IOMMU driver.
1637 * Must be called with the domain lock held.
1639 static dma_addr_t __map_single(struct device *dev,
1640 struct amd_iommu *iommu,
1641 struct dma_ops_domain *dma_dom,
1648 dma_addr_t offset = paddr & ~PAGE_MASK;
1649 dma_addr_t address, start, ret;
1651 unsigned long align_mask = 0;
1654 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1657 INC_STATS_COUNTER(total_map_requests);
1660 INC_STATS_COUNTER(cross_page);
1663 align_mask = (1UL << get_order(size)) - 1;
1666 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1668 if (unlikely(address == DMA_ERROR_CODE)) {
1670 * setting next_address here will let the address
1671 * allocator only scan the new allocated range in the
1672 * first run. This is a small optimization.
1674 dma_dom->next_address = dma_dom->aperture_size;
1676 if (alloc_new_range(iommu, dma_dom, false, GFP_ATOMIC))
1680 * aperture was sucessfully enlarged by 128 MB, try
1687 for (i = 0; i < pages; ++i) {
1688 ret = dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
1689 if (ret == DMA_ERROR_CODE)
1697 ADD_STATS_COUNTER(alloced_io_mem, size);
1699 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1700 iommu_flush_tlb(iommu, dma_dom->domain.id);
1701 dma_dom->need_flush = false;
1702 } else if (unlikely(iommu_has_npcache(iommu)))
1703 iommu_flush_pages(&dma_dom->domain, address, size);
1710 for (--i; i >= 0; --i) {
1712 dma_ops_domain_unmap(iommu, dma_dom, start);
1715 dma_ops_free_addresses(dma_dom, address, pages);
1717 return DMA_ERROR_CODE;
1721 * Does the reverse of the __map_single function. Must be called with
1722 * the domain lock held too
1724 static void __unmap_single(struct amd_iommu *iommu,
1725 struct dma_ops_domain *dma_dom,
1726 dma_addr_t dma_addr,
1730 dma_addr_t i, start;
1733 if ((dma_addr == DMA_ERROR_CODE) ||
1734 (dma_addr + size > dma_dom->aperture_size))
1737 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1738 dma_addr &= PAGE_MASK;
1741 for (i = 0; i < pages; ++i) {
1742 dma_ops_domain_unmap(iommu, dma_dom, start);
1746 SUB_STATS_COUNTER(alloced_io_mem, size);
1748 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1750 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1751 iommu_flush_pages(&dma_dom->domain, dma_addr, size);
1752 dma_dom->need_flush = false;
1757 * The exported map_single function for dma_ops.
1759 static dma_addr_t map_page(struct device *dev, struct page *page,
1760 unsigned long offset, size_t size,
1761 enum dma_data_direction dir,
1762 struct dma_attrs *attrs)
1764 unsigned long flags;
1765 struct amd_iommu *iommu;
1766 struct protection_domain *domain;
1770 phys_addr_t paddr = page_to_phys(page) + offset;
1772 INC_STATS_COUNTER(cnt_map_single);
1774 if (!check_device(dev))
1775 return DMA_ERROR_CODE;
1777 dma_mask = *dev->dma_mask;
1779 get_device_resources(dev, &iommu, &domain, &devid);
1781 if (iommu == NULL || domain == NULL)
1782 /* device not handled by any AMD IOMMU */
1783 return (dma_addr_t)paddr;
1785 if (!dma_ops_domain(domain))
1786 return DMA_ERROR_CODE;
1788 spin_lock_irqsave(&domain->lock, flags);
1789 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false,
1791 if (addr == DMA_ERROR_CODE)
1794 iommu_flush_complete(domain);
1797 spin_unlock_irqrestore(&domain->lock, flags);
1803 * The exported unmap_single function for dma_ops.
1805 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
1806 enum dma_data_direction dir, struct dma_attrs *attrs)
1808 unsigned long flags;
1809 struct amd_iommu *iommu;
1810 struct protection_domain *domain;
1813 INC_STATS_COUNTER(cnt_unmap_single);
1815 if (!check_device(dev) ||
1816 !get_device_resources(dev, &iommu, &domain, &devid))
1817 /* device not handled by any AMD IOMMU */
1820 if (!dma_ops_domain(domain))
1823 spin_lock_irqsave(&domain->lock, flags);
1825 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
1827 iommu_flush_complete(domain);
1829 spin_unlock_irqrestore(&domain->lock, flags);
1833 * This is a special map_sg function which is used if we should map a
1834 * device which is not handled by an AMD IOMMU in the system.
1836 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1837 int nelems, int dir)
1839 struct scatterlist *s;
1842 for_each_sg(sglist, s, nelems, i) {
1843 s->dma_address = (dma_addr_t)sg_phys(s);
1844 s->dma_length = s->length;
1851 * The exported map_sg function for dma_ops (handles scatter-gather
1854 static int map_sg(struct device *dev, struct scatterlist *sglist,
1855 int nelems, enum dma_data_direction dir,
1856 struct dma_attrs *attrs)
1858 unsigned long flags;
1859 struct amd_iommu *iommu;
1860 struct protection_domain *domain;
1863 struct scatterlist *s;
1865 int mapped_elems = 0;
1868 INC_STATS_COUNTER(cnt_map_sg);
1870 if (!check_device(dev))
1873 dma_mask = *dev->dma_mask;
1875 get_device_resources(dev, &iommu, &domain, &devid);
1877 if (!iommu || !domain)
1878 return map_sg_no_iommu(dev, sglist, nelems, dir);
1880 if (!dma_ops_domain(domain))
1883 spin_lock_irqsave(&domain->lock, flags);
1885 for_each_sg(sglist, s, nelems, i) {
1888 s->dma_address = __map_single(dev, iommu, domain->priv,
1889 paddr, s->length, dir, false,
1892 if (s->dma_address) {
1893 s->dma_length = s->length;
1899 iommu_flush_complete(domain);
1902 spin_unlock_irqrestore(&domain->lock, flags);
1904 return mapped_elems;
1906 for_each_sg(sglist, s, mapped_elems, i) {
1908 __unmap_single(iommu, domain->priv, s->dma_address,
1909 s->dma_length, dir);
1910 s->dma_address = s->dma_length = 0;
1919 * The exported map_sg function for dma_ops (handles scatter-gather
1922 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1923 int nelems, enum dma_data_direction dir,
1924 struct dma_attrs *attrs)
1926 unsigned long flags;
1927 struct amd_iommu *iommu;
1928 struct protection_domain *domain;
1929 struct scatterlist *s;
1933 INC_STATS_COUNTER(cnt_unmap_sg);
1935 if (!check_device(dev) ||
1936 !get_device_resources(dev, &iommu, &domain, &devid))
1939 if (!dma_ops_domain(domain))
1942 spin_lock_irqsave(&domain->lock, flags);
1944 for_each_sg(sglist, s, nelems, i) {
1945 __unmap_single(iommu, domain->priv, s->dma_address,
1946 s->dma_length, dir);
1947 s->dma_address = s->dma_length = 0;
1950 iommu_flush_complete(domain);
1952 spin_unlock_irqrestore(&domain->lock, flags);
1956 * The exported alloc_coherent function for dma_ops.
1958 static void *alloc_coherent(struct device *dev, size_t size,
1959 dma_addr_t *dma_addr, gfp_t flag)
1961 unsigned long flags;
1963 struct amd_iommu *iommu;
1964 struct protection_domain *domain;
1967 u64 dma_mask = dev->coherent_dma_mask;
1969 INC_STATS_COUNTER(cnt_alloc_coherent);
1971 if (!check_device(dev))
1974 if (!get_device_resources(dev, &iommu, &domain, &devid))
1975 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
1978 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1982 paddr = virt_to_phys(virt_addr);
1984 if (!iommu || !domain) {
1985 *dma_addr = (dma_addr_t)paddr;
1989 if (!dma_ops_domain(domain))
1993 dma_mask = *dev->dma_mask;
1995 spin_lock_irqsave(&domain->lock, flags);
1997 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1998 size, DMA_BIDIRECTIONAL, true, dma_mask);
2000 if (*dma_addr == DMA_ERROR_CODE) {
2001 spin_unlock_irqrestore(&domain->lock, flags);
2005 iommu_flush_complete(domain);
2007 spin_unlock_irqrestore(&domain->lock, flags);
2013 free_pages((unsigned long)virt_addr, get_order(size));
2019 * The exported free_coherent function for dma_ops.
2021 static void free_coherent(struct device *dev, size_t size,
2022 void *virt_addr, dma_addr_t dma_addr)
2024 unsigned long flags;
2025 struct amd_iommu *iommu;
2026 struct protection_domain *domain;
2029 INC_STATS_COUNTER(cnt_free_coherent);
2031 if (!check_device(dev))
2034 get_device_resources(dev, &iommu, &domain, &devid);
2036 if (!iommu || !domain)
2039 if (!dma_ops_domain(domain))
2042 spin_lock_irqsave(&domain->lock, flags);
2044 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2046 iommu_flush_complete(domain);
2048 spin_unlock_irqrestore(&domain->lock, flags);
2051 free_pages((unsigned long)virt_addr, get_order(size));
2055 * This function is called by the DMA layer to find out if we can handle a
2056 * particular device. It is part of the dma_ops.
2058 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2061 struct pci_dev *pcidev;
2063 /* No device or no PCI device */
2064 if (!dev || dev->bus != &pci_bus_type)
2067 pcidev = to_pci_dev(dev);
2069 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
2071 /* Out of our scope? */
2072 if (bdf > amd_iommu_last_bdf)
2079 * The function for pre-allocating protection domains.
2081 * If the driver core informs the DMA layer if a driver grabs a device
2082 * we don't need to preallocate the protection domains anymore.
2083 * For now we have to.
2085 static void prealloc_protection_domains(void)
2087 struct pci_dev *dev = NULL;
2088 struct dma_ops_domain *dma_dom;
2089 struct amd_iommu *iommu;
2092 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2093 __devid = devid = calc_devid(dev->bus->number, dev->devfn);
2094 if (devid > amd_iommu_last_bdf)
2096 devid = amd_iommu_alias_table[devid];
2097 if (domain_for_device(devid))
2099 iommu = amd_iommu_rlookup_table[devid];
2102 dma_dom = dma_ops_domain_alloc(iommu);
2105 init_unity_mappings_for_device(dma_dom, devid);
2106 dma_dom->target_dev = devid;
2108 attach_device(iommu, &dma_dom->domain, devid);
2109 if (__devid != devid)
2110 attach_device(iommu, &dma_dom->domain, __devid);
2112 list_add_tail(&dma_dom->list, &iommu_pd_list);
2116 static struct dma_map_ops amd_iommu_dma_ops = {
2117 .alloc_coherent = alloc_coherent,
2118 .free_coherent = free_coherent,
2119 .map_page = map_page,
2120 .unmap_page = unmap_page,
2122 .unmap_sg = unmap_sg,
2123 .dma_supported = amd_iommu_dma_supported,
2127 * The function which clues the AMD IOMMU driver into dma_ops.
2129 int __init amd_iommu_init_dma_ops(void)
2131 struct amd_iommu *iommu;
2135 * first allocate a default protection domain for every IOMMU we
2136 * found in the system. Devices not assigned to any other
2137 * protection domain will be assigned to the default one.
2139 for_each_iommu(iommu) {
2140 iommu->default_dom = dma_ops_domain_alloc(iommu);
2141 if (iommu->default_dom == NULL)
2143 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
2144 ret = iommu_init_unity_mappings(iommu);
2150 * If device isolation is enabled, pre-allocate the protection
2151 * domains for each device.
2153 if (amd_iommu_isolate)
2154 prealloc_protection_domains();
2158 #ifdef CONFIG_GART_IOMMU
2159 gart_iommu_aperture_disabled = 1;
2160 gart_iommu_aperture = 0;
2163 /* Make the driver finally visible to the drivers */
2164 dma_ops = &amd_iommu_dma_ops;
2166 register_iommu(&amd_iommu_ops);
2168 bus_register_notifier(&pci_bus_type, &device_nb);
2170 amd_iommu_stats_init();
2176 for_each_iommu(iommu) {
2177 if (iommu->default_dom)
2178 dma_ops_domain_free(iommu->default_dom);
2184 /*****************************************************************************
2186 * The following functions belong to the exported interface of AMD IOMMU
2188 * This interface allows access to lower level functions of the IOMMU
2189 * like protection domain handling and assignement of devices to domains
2190 * which is not possible with the dma_ops interface.
2192 *****************************************************************************/
2194 static void cleanup_domain(struct protection_domain *domain)
2196 unsigned long flags;
2199 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2201 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
2202 if (amd_iommu_pd_table[devid] == domain)
2203 __detach_device(domain, devid);
2205 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2208 static void protection_domain_free(struct protection_domain *domain)
2214 domain_id_free(domain->id);
2219 static struct protection_domain *protection_domain_alloc(void)
2221 struct protection_domain *domain;
2223 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2227 spin_lock_init(&domain->lock);
2228 domain->id = domain_id_alloc();
2240 static int amd_iommu_domain_init(struct iommu_domain *dom)
2242 struct protection_domain *domain;
2244 domain = protection_domain_alloc();
2248 domain->mode = PAGE_MODE_3_LEVEL;
2249 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2250 if (!domain->pt_root)
2258 protection_domain_free(domain);
2263 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
2265 struct protection_domain *domain = dom->priv;
2270 if (domain->dev_cnt > 0)
2271 cleanup_domain(domain);
2273 BUG_ON(domain->dev_cnt != 0);
2275 free_pagetable(domain);
2277 domain_id_free(domain->id);
2284 static void amd_iommu_detach_device(struct iommu_domain *dom,
2287 struct protection_domain *domain = dom->priv;
2288 struct amd_iommu *iommu;
2289 struct pci_dev *pdev;
2292 if (dev->bus != &pci_bus_type)
2295 pdev = to_pci_dev(dev);
2297 devid = calc_devid(pdev->bus->number, pdev->devfn);
2300 detach_device(domain, devid);
2302 iommu = amd_iommu_rlookup_table[devid];
2306 iommu_queue_inv_dev_entry(iommu, devid);
2307 iommu_completion_wait(iommu);
2310 static int amd_iommu_attach_device(struct iommu_domain *dom,
2313 struct protection_domain *domain = dom->priv;
2314 struct protection_domain *old_domain;
2315 struct amd_iommu *iommu;
2316 struct pci_dev *pdev;
2319 if (dev->bus != &pci_bus_type)
2322 pdev = to_pci_dev(dev);
2324 devid = calc_devid(pdev->bus->number, pdev->devfn);
2326 if (devid >= amd_iommu_last_bdf ||
2327 devid != amd_iommu_alias_table[devid])
2330 iommu = amd_iommu_rlookup_table[devid];
2334 old_domain = domain_for_device(devid);
2336 detach_device(old_domain, devid);
2338 attach_device(iommu, domain, devid);
2340 iommu_completion_wait(iommu);
2345 static int amd_iommu_map_range(struct iommu_domain *dom,
2346 unsigned long iova, phys_addr_t paddr,
2347 size_t size, int iommu_prot)
2349 struct protection_domain *domain = dom->priv;
2350 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
2354 if (iommu_prot & IOMMU_READ)
2355 prot |= IOMMU_PROT_IR;
2356 if (iommu_prot & IOMMU_WRITE)
2357 prot |= IOMMU_PROT_IW;
2362 for (i = 0; i < npages; ++i) {
2363 ret = iommu_map_page(domain, iova, paddr, prot, PM_MAP_4k);
2374 static void amd_iommu_unmap_range(struct iommu_domain *dom,
2375 unsigned long iova, size_t size)
2378 struct protection_domain *domain = dom->priv;
2379 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
2383 for (i = 0; i < npages; ++i) {
2384 iommu_unmap_page(domain, iova, PM_MAP_4k);
2388 iommu_flush_domain(domain->id);
2391 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2394 struct protection_domain *domain = dom->priv;
2395 unsigned long offset = iova & ~PAGE_MASK;
2399 pte = fetch_pte(domain, iova, PM_MAP_4k);
2401 if (!pte || !IOMMU_PTE_PRESENT(*pte))
2404 paddr = *pte & IOMMU_PAGE_MASK;
2410 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
2416 static struct iommu_ops amd_iommu_ops = {
2417 .domain_init = amd_iommu_domain_init,
2418 .domain_destroy = amd_iommu_domain_destroy,
2419 .attach_dev = amd_iommu_attach_device,
2420 .detach_dev = amd_iommu_detach_device,
2421 .map = amd_iommu_map_range,
2422 .unmap = amd_iommu_unmap_range,
2423 .iova_to_phys = amd_iommu_iova_to_phys,
2424 .domain_has_cap = amd_iommu_domain_has_cap,
2427 /*****************************************************************************
2429 * The next functions do a basic initialization of IOMMU for pass through
2432 * In passthrough mode the IOMMU is initialized and enabled but not used for
2433 * DMA-API translation.
2435 *****************************************************************************/
2437 int __init amd_iommu_init_passthrough(void)
2439 struct pci_dev *dev = NULL;
2442 /* allocate passthroug domain */
2443 pt_domain = protection_domain_alloc();
2447 pt_domain->mode |= PAGE_MODE_NONE;
2449 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2450 struct amd_iommu *iommu;
2452 devid = calc_devid(dev->bus->number, dev->devfn);
2453 if (devid > amd_iommu_last_bdf)
2456 devid2 = amd_iommu_alias_table[devid];
2458 iommu = amd_iommu_rlookup_table[devid2];
2462 __attach_device(iommu, pt_domain, devid);
2463 __attach_device(iommu, pt_domain, devid2);
2466 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");