SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/x86/include/asm/system.h

   1 #ifndef _ASM_X86_SYSTEM_H
   2 #define _ASM_X86_SYSTEM_H
   3
   4 #include <asm/asm.h>
   5 #include <asm/segment.h>
   6 #include <asm/cpufeature.h>
   7 #include <asm/cmpxchg.h>
   8 #include <asm/nops.h>
   9
  10 #include <linux/kernel.h>
  11 #include <linux/irqflags.h>
  12
  13 /* entries in ARCH_DLINFO: */
  14 #ifdef CONFIG_IA32_EMULATION
  15 # define AT_VECTOR_SIZE_ARCH 2
  16 #else
  17 # define AT_VECTOR_SIZE_ARCH 1
  18 #endif
  19
  20 struct task_struct; /* one of the stranger aspects of C forward declarations */
  21 struct task_struct *__switch_to(struct task_struct *prev,
  22                                 struct task_struct *next);
  23
  24 #ifdef CONFIG_X86_32
  25
  26 /*
  27  * Saving eflags is important. It switches not only IOPL between tasks,
  28  * it also protects other tasks from NT leaking through sysenter etc.
  29  */
  30 #define switch_to(prev, next, last)                                     \
  31 do {                                                                    \
  32         /*                                                              \
  33          * Context-switching clobbers all registers, so we clobber      \
  34          * them explicitly, via unused output variables.                \
  35          * (EAX and EBP is not listed because EBP is saved/restored     \
  36          * explicitly for wchan access and EAX is the return value of   \
  37          * __switch_to())                                               \
  38          */                                                             \
  39         unsigned long ebx, ecx, edx, esi, edi;                          \
  40                                                                         \
  41         asm volatile("pushfl\n\t"               /* save    flags */     \
  42                      "pushl %%ebp\n\t"          /* save    EBP   */     \
  43                      "movl %%esp,%[prev_sp]\n\t"        /* save    ESP   */ \
  44                      "movl %[next_sp],%%esp\n\t"        /* restore ESP   */ \
  45                      "movl $1f,%[prev_ip]\n\t"  /* save    EIP   */     \
  46                      "pushl %[next_ip]\n\t"     /* restore EIP   */     \
  47                      "jmp __switch_to\n"        /* regparm call  */     \
  48                      "1:\t"                                             \
  49                      "popl %%ebp\n\t"           /* restore EBP   */     \
  50                      "popfl\n"                  /* restore flags */     \
  51                                                                         \
  52                      /* output parameters */                            \
  53                      : [prev_sp] "=m" (prev->thread.sp),                \
  54                        [prev_ip] "=m" (prev->thread.ip),                \
  55                        "=a" (last),                                     \
  56                                                                         \
  57                        /* clobbered output registers: */                \
  58                        "=b" (ebx), "=c" (ecx), "=d" (edx),              \
  59                        "=S" (esi), "=D" (edi)                           \
  60                                                                         \
  61                        /* input parameters: */                          \
  62                      : [next_sp]  "m" (next->thread.sp),                \
  63                        [next_ip]  "m" (next->thread.ip),                \
  64                                                                         \
  65                        /* regparm parameters for __switch_to(): */      \
  66                        [prev]     "a" (prev),                           \
  67                        [next]     "d" (next)                            \
  68                                                                         \
  69                      : /* reloaded segment registers */                 \
  70                         "memory");                                      \
  71 } while (0)
  72
  73 /*
  74  * disable hlt during certain critical i/o operations
  75  */
  76 #define HAVE_DISABLE_HLT
  77 #else
  78 #define __SAVE(reg, offset) "movq %%" #reg ",(14-" #offset ")*8(%%rsp)\n\t"
  79 #define __RESTORE(reg, offset) "movq (14-" #offset ")*8(%%rsp),%%" #reg "\n\t"
  80
  81 /* frame pointer must be last for get_wchan */
  82 #define SAVE_CONTEXT    "pushf ; pushq %%rbp ; movq %%rsi,%%rbp\n\t"
  83 #define RESTORE_CONTEXT "movq %%rbp,%%rsi ; popq %%rbp ; popf\t"
  84
  85 #define __EXTRA_CLOBBER  \
  86         , "rcx", "rbx", "rdx", "r8", "r9", "r10", "r11", \
  87           "r12", "r13", "r14", "r15"
  88
  89 /* Save restore flags to clear handle leaking NT */
  90 #define switch_to(prev, next, last) \
  91         asm volatile(SAVE_CONTEXT                                                   \
  92              "movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */       \
  93              "movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */    \
  94              "call __switch_to\n\t"                                       \
  95              ".globl thread_return\n"                                     \
  96              "thread_return:\n\t"                                         \
  97              "movq %%gs:%P[pda_pcurrent],%%rsi\n\t"                       \
  98              "movq %P[task_canary](%%rsi),%%r8\n\t"                       \
  99              "movq %%r8,%%gs:%P[pda_canary]\n\t"                          \
 100              "movq %P[thread_info](%%rsi),%%r8\n\t"                       \
 101              LOCK_PREFIX "btr  %[tif_fork],%P[ti_flags](%%r8)\n\t"        \
 102              "movq %%rax,%%rdi\n\t"                                       \
 103              "jc   ret_from_fork\n\t"                                     \
 104              RESTORE_CONTEXT                                              \
 105              : "=a" (last)                                                \
 106              : [next] "S" (next), [prev] "D" (prev),                      \
 107                [threadrsp] "i" (offsetof(struct task_struct, thread.sp)), \
 108                [ti_flags] "i" (offsetof(struct thread_info, flags)),      \
 109                [tif_fork] "i" (TIF_FORK),                                 \
 110                [thread_info] "i" (offsetof(struct task_struct, stack)),   \
 111                [task_canary] "i" (offsetof(struct task_struct, stack_canary)),\
 112                [pda_pcurrent] "i" (offsetof(struct x8664_pda, pcurrent)), \
 113                [pda_canary] "i" (offsetof(struct x8664_pda, stack_canary))\
 114              : "memory", "cc" __EXTRA_CLOBBER)
 115 #endif
 116
 117 #ifdef __KERNEL__
 118 #define _set_base(addr, base) do { unsigned long __pr; \
 119 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
 120         "rorl $16,%%edx\n\t" \
 121         "movb %%dl,%2\n\t" \
 122         "movb %%dh,%3" \
 123         :"=&d" (__pr) \
 124         :"m" (*((addr)+2)), \
 125          "m" (*((addr)+4)), \
 126          "m" (*((addr)+7)), \
 127          "0" (base) \
 128         ); } while (0)
 129
 130 #define _set_limit(addr, limit) do { unsigned long __lr; \
 131 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
 132         "rorl $16,%%edx\n\t" \
 133         "movb %2,%%dh\n\t" \
 134         "andb $0xf0,%%dh\n\t" \
 135         "orb %%dh,%%dl\n\t" \
 136         "movb %%dl,%2" \
 137         :"=&d" (__lr) \
 138         :"m" (*(addr)), \
 139          "m" (*((addr)+6)), \
 140          "0" (limit) \
 141         ); } while (0)
 142
 143 #define set_base(ldt, base) _set_base(((char *)&(ldt)) , (base))
 144 #define set_limit(ldt, limit) _set_limit(((char *)&(ldt)) , ((limit)-1))
 145
 146 extern void native_load_gs_index(unsigned);
 147
 148 /*
 149  * Load a segment. Fall back on loading the zero
 150  * segment if something goes wrong..
 151  */
 152 #define loadsegment(seg, value)                 \
 153         asm volatile("\n"                       \
 154                      "1:\t"                     \
 155                      "movl %k0,%%" #seg "\n"    \
 156                      "2:\n"                     \
 157                      ".section .fixup,\"ax\"\n" \
 158                      "3:\t"                     \
 159                      "movl %k1, %%" #seg "\n\t" \
 160                      "jmp 2b\n"                 \
 161                      ".previous\n"              \
 162                      _ASM_EXTABLE(1b,3b)        \
 163                      : :"r" (value), "r" (0) : "memory")
 164
 165
 166 /*
 167  * Save a segment register away
 168  */
 169 #define savesegment(seg, value)                         \
 170         asm("mov %%" #seg ",%0":"=r" (value) : : "memory")
 171
 172 static inline unsigned long get_limit(unsigned long segment)
 173 {
 174         unsigned long __limit;
 175         asm("lsll %1,%0" : "=r" (__limit) : "r" (segment));
 176         return __limit + 1;
 177 }
 178
 179 static inline void native_clts(void)
 180 {
 181         asm volatile("clts");
 182 }
 183
 184 /*
 185  * Volatile isn't enough to prevent the compiler from reordering the
 186  * read/write functions for the control registers and messing everything up.
 187  * A memory clobber would solve the problem, but would prevent reordering of
 188  * all loads stores around it, which can hurt performance. Solution is to
 189  * use a variable and mimic reads and writes to it to enforce serialization
 190  */
 191 static unsigned long __force_order;
 192
 193 static inline unsigned long native_read_cr0(void)
 194 {
 195         unsigned long val;
 196         asm volatile("mov %%cr0,%0\n\t" : "=r" (val), "=m" (__force_order));
 197         return val;
 198 }
 199
 200 static inline void native_write_cr0(unsigned long val)
 201 {
 202         asm volatile("mov %0,%%cr0": : "r" (val), "m" (__force_order));
 203 }
 204
 205 static inline unsigned long native_read_cr2(void)
 206 {
 207         unsigned long val;
 208         asm volatile("mov %%cr2,%0\n\t" : "=r" (val), "=m" (__force_order));
 209         return val;
 210 }
 211
 212 static inline void native_write_cr2(unsigned long val)
 213 {
 214         asm volatile("mov %0,%%cr2": : "r" (val), "m" (__force_order));
 215 }
 216
 217 static inline unsigned long native_read_cr3(void)
 218 {
 219         unsigned long val;
 220         asm volatile("mov %%cr3,%0\n\t" : "=r" (val), "=m" (__force_order));
 221         return val;
 222 }
 223
 224 static inline void native_write_cr3(unsigned long val)
 225 {
 226         asm volatile("mov %0,%%cr3": : "r" (val), "m" (__force_order));
 227 }
 228
 229 static inline unsigned long native_read_cr4(void)
 230 {
 231         unsigned long val;
 232         asm volatile("mov %%cr4,%0\n\t" : "=r" (val), "=m" (__force_order));
 233         return val;
 234 }
 235
 236 static inline unsigned long native_read_cr4_safe(void)
 237 {
 238         unsigned long val;
 239         /* This could fault if %cr4 does not exist. In x86_64, a cr4 always
 240          * exists, so it will never fail. */
 241 #ifdef CONFIG_X86_32
 242         asm volatile("1: mov %%cr4, %0\n"
 243                      "2:\n"
 244                      _ASM_EXTABLE(1b, 2b)
 245                      : "=r" (val), "=m" (__force_order) : "0" (0));
 246 #else
 247         val = native_read_cr4();
 248 #endif
 249         return val;
 250 }
 251
 252 static inline void native_write_cr4(unsigned long val)
 253 {
 254         asm volatile("mov %0,%%cr4": : "r" (val), "m" (__force_order));
 255 }
 256
 257 #ifdef CONFIG_X86_64
 258 static inline unsigned long native_read_cr8(void)
 259 {
 260         unsigned long cr8;
 261         asm volatile("movq %%cr8,%0" : "=r" (cr8));
 262         return cr8;
 263 }
 264
 265 static inline void native_write_cr8(unsigned long val)
 266 {
 267         asm volatile("movq %0,%%cr8" :: "r" (val) : "memory");
 268 }
 269 #endif
 270
 271 static inline void native_wbinvd(void)
 272 {
 273         asm volatile("wbinvd": : :"memory");
 274 }
 275
 276 #ifdef CONFIG_PARAVIRT
 277 #include <asm/paravirt.h>
 278 #else
 279 #define read_cr0()      (native_read_cr0())
 280 #define write_cr0(x)    (native_write_cr0(x))
 281 #define read_cr2()      (native_read_cr2())
 282 #define write_cr2(x)    (native_write_cr2(x))
 283 #define read_cr3()      (native_read_cr3())
 284 #define write_cr3(x)    (native_write_cr3(x))
 285 #define read_cr4()      (native_read_cr4())
 286 #define read_cr4_safe() (native_read_cr4_safe())
 287 #define write_cr4(x)    (native_write_cr4(x))
 288 #define wbinvd()        (native_wbinvd())
 289 #ifdef CONFIG_X86_64
 290 #define read_cr8()      (native_read_cr8())
 291 #define write_cr8(x)    (native_write_cr8(x))
 292 #define load_gs_index   native_load_gs_index
 293 #endif
 294
 295 /* Clear the 'TS' bit */
 296 #define clts()          (native_clts())
 297
 298 #endif/* CONFIG_PARAVIRT */
 299
 300 #define stts() write_cr0(read_cr0() | X86_CR0_TS)
 301
 302 #endif /* __KERNEL__ */
 303
 304 static inline void clflush(volatile void *__p)
 305 {
 306         asm volatile("clflush %0" : "+m" (*(volatile char __force *)__p));
 307 }
 308
 309 #define nop() asm volatile ("nop")
 310
 311 void disable_hlt(void);
 312 void enable_hlt(void);
 313
 314 void cpu_idle_wait(void);
 315
 316 extern unsigned long arch_align_stack(unsigned long sp);
 317 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
 318
 319 void default_idle(void);
 320
 321 void stop_this_cpu(void *dummy);
 322
 323 /*
 324  * Force strict CPU ordering.
 325  * And yes, this is required on UP too when we're talking
 326  * to devices.
 327  */
 328 #ifdef CONFIG_X86_32
 329 /*
 330  * Some non-Intel clones support out of order store. wmb() ceases to be a
 331  * nop for these.
 332  */
 333 #define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
 334 #define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
 335 #define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
 336 #else
 337 #define mb()    asm volatile("mfence":::"memory")
 338 #define rmb()   asm volatile("lfence":::"memory")
 339 #define wmb()   asm volatile("sfence" ::: "memory")
 340 #endif
 341
 342 /**
 343  * read_barrier_depends - Flush all pending reads that subsequents reads
 344  * depend on.
 345  *
 346  * No data-dependent reads from memory-like regions are ever reordered
 347  * over this barrier.  All reads preceding this primitive are guaranteed
 348  * to access memory (but not necessarily other CPUs' caches) before any
 349  * reads following this primitive that depend on the data return by
 350  * any of the preceding reads.  This primitive is much lighter weight than
 351  * rmb() on most CPUs, and is never heavier weight than is
 352  * rmb().
 353  *
 354  * These ordering constraints are respected by both the local CPU
 355  * and the compiler.
 356  *
 357  * Ordering is not guaranteed by anything other than these primitives,
 358  * not even by data dependencies.  See the documentation for
 359  * memory_barrier() for examples and URLs to more information.
 360  *
 361  * For example, the following code would force ordering (the initial
 362  * value of "a" is zero, "b" is one, and "p" is "&a"):
 363  *
 364  * <programlisting>
 365  *      CPU 0                           CPU 1
 366  *
 367  *      b = 2;
 368  *      memory_barrier();
 369  *      p = &b;                         q = p;
 370  *                                      read_barrier_depends();
 371  *                                      d = *q;
 372  * </programlisting>
 373  *
 374  * because the read of "*q" depends on the read of "p" and these
 375  * two reads are separated by a read_barrier_depends().  However,
 376  * the following code, with the same initial values for "a" and "b":
 377  *
 378  * <programlisting>
 379  *      CPU 0                           CPU 1
 380  *
 381  *      a = 2;
 382  *      memory_barrier();
 383  *      b = 3;                          y = b;
 384  *                                      read_barrier_depends();
 385  *                                      x = a;
 386  * </programlisting>
 387  *
 388  * does not enforce ordering, since there is no data dependency between
 389  * the read of "a" and the read of "b".  Therefore, on some CPUs, such
 390  * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
 391  * in cases like this where there are no data dependencies.
 392  **/
 393
 394 #define read_barrier_depends()  do { } while (0)
 395
 396 #ifdef CONFIG_SMP
 397 #define smp_mb()        mb()
 398 #ifdef CONFIG_X86_PPRO_FENCE
 399 # define smp_rmb()      rmb()
 400 #else
 401 # define smp_rmb()      barrier()
 402 #endif
 403 #ifdef CONFIG_X86_OOSTORE
 404 # define smp_wmb()      wmb()
 405 #else
 406 # define smp_wmb()      barrier()
 407 #endif
 408 #define smp_read_barrier_depends()      read_barrier_depends()
 409 #define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
 410 #else
 411 #define smp_mb()        barrier()
 412 #define smp_rmb()       barrier()
 413 #define smp_wmb()       barrier()
 414 #define smp_read_barrier_depends()      do { } while (0)
 415 #define set_mb(var, value) do { var = value; barrier(); } while (0)
 416 #endif
 417
 418 /*
 419  * Stop RDTSC speculation. This is needed when you need to use RDTSC
 420  * (or get_cycles or vread that possibly accesses the TSC) in a defined
 421  * code region.
 422  *
 423  * (Could use an alternative three way for this if there was one.)
 424  */
 425 static inline void rdtsc_barrier(void)
 426 {
 427         alternative(ASM_NOP3, "mfence", X86_FEATURE_MFENCE_RDTSC);
 428         alternative(ASM_NOP3, "lfence", X86_FEATURE_LFENCE_RDTSC);
 429 }
 430
 431 #endif /* _ASM_X86_SYSTEM_H */