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   1 #ifndef _ASM_X86_SYSTEM_H
   2 #define _ASM_X86_SYSTEM_H
   3
   4 #include <asm/asm.h>
   5 #include <asm/segment.h>
   6 #include <asm/cpufeature.h>
   7 #include <asm/cmpxchg.h>
   8 #include <asm/nops.h>
   9
  10 #include <linux/kernel.h>
  11 #include <linux/irqflags.h>
  12
  13 /* entries in ARCH_DLINFO: */
  14 #ifdef CONFIG_IA32_EMULATION
  15 # define AT_VECTOR_SIZE_ARCH 2
  16 #else
  17 # define AT_VECTOR_SIZE_ARCH 1
  18 #endif
  19
  20 struct task_struct; /* one of the stranger aspects of C forward declarations */
  21 struct task_struct *__switch_to(struct task_struct *prev,
  22                                 struct task_struct *next);
  23
  24 #ifdef CONFIG_X86_32
  25
  26 /*
  27  * Saving eflags is important. It switches not only IOPL between tasks,
  28  * it also protects other tasks from NT leaking through sysenter etc.
  29  */
  30 #define switch_to(prev, next, last)                                     \
  31 do {                                                                    \
  32         /*                                                              \
  33          * Context-switching clobbers all registers, so we clobber      \
  34          * them explicitly, via unused output variables.                \
  35          * (EAX and EBP is not listed because EBP is saved/restored     \
  36          * explicitly for wchan access and EAX is the return value of   \
  37          * __switch_to())                                               \
  38          */                                                             \
  39         unsigned long ebx, ecx, edx, esi, edi;                          \
  40                                                                         \
  41         asm volatile("pushfl\n\t"               /* save    flags */     \
  42                      "pushl %%ebp\n\t"          /* save    EBP   */     \
  43                      "movl %%esp,%[prev_sp]\n\t"        /* save    ESP   */ \
  44                      "movl %[next_sp],%%esp\n\t"        /* restore ESP   */ \
  45                      "movl $1f,%[prev_ip]\n\t"  /* save    EIP   */     \
  46                      "pushl %[next_ip]\n\t"     /* restore EIP   */     \
  47                      "jmp __switch_to\n"        /* regparm call  */     \
  48                      "1:\t"                                             \
  49                      "popl %%ebp\n\t"           /* restore EBP   */     \
  50                      "popfl\n"                  /* restore flags */     \
  51                                                                         \
  52                      /* output parameters */                            \
  53                      : [prev_sp] "=m" (prev->thread.sp),                \
  54                        [prev_ip] "=m" (prev->thread.ip),                \
  55                        "=a" (last),                                     \
  56                                                                         \
  57                        /* clobbered output registers: */                \
  58                        "=b" (ebx), "=c" (ecx), "=d" (edx),              \
  59                        "=S" (esi), "=D" (edi)                           \
  60                                                                         \
  61                        /* input parameters: */                          \
  62                      : [next_sp]  "m" (next->thread.sp),                \
  63                        [next_ip]  "m" (next->thread.ip),                \
  64                                                                         \
  65                        /* regparm parameters for __switch_to(): */      \
  66                        [prev]     "a" (prev),                           \
  67                        [next]     "d" (next)                            \
  68                                                                         \
  69                      : /* reloaded segment registers */                 \
  70                         "memory");                                      \
  71 } while (0)
  72
  73 /*
  74  * disable hlt during certain critical i/o operations
  75  */
  76 #define HAVE_DISABLE_HLT
  77 #else
  78 #define __SAVE(reg, offset) "movq %%" #reg ",(14-" #offset ")*8(%%rsp)\n\t"
  79 #define __RESTORE(reg, offset) "movq (14-" #offset ")*8(%%rsp),%%" #reg "\n\t"
  80
  81 /* frame pointer must be last for get_wchan */
  82 #define SAVE_CONTEXT    "pushf ; pushq %%rbp ; movq %%rsi,%%rbp\n\t"
  83 #define RESTORE_CONTEXT "movq %%rbp,%%rsi ; popq %%rbp ; popf\t"
  84
  85 #define __EXTRA_CLOBBER  \
  86         , "rcx", "rbx", "rdx", "r8", "r9", "r10", "r11", \
  87           "r12", "r13", "r14", "r15"
  88
  89 #ifdef CONFIG_CC_STACKPROTECTOR
  90 #define __switch_canary                                                   \
  91         "movq %P[task_canary](%%rsi),%%r8\n\t"                            \
  92         "movq %%r8,%%gs:%P[gs_canary]\n\t"
  93 #define __switch_canary_param                                             \
  94         , [task_canary] "i" (offsetof(struct task_struct, stack_canary))  \
  95         , [gs_canary] "i" (offsetof(union irq_stack_union, stack_canary))
  96 #else   /* CC_STACKPROTECTOR */
  97 #define __switch_canary
  98 #define __switch_canary_param
  99 #endif  /* CC_STACKPROTECTOR */
 100
 101 /* Save restore flags to clear handle leaking NT */
 102 #define switch_to(prev, next, last) \
 103         asm volatile(SAVE_CONTEXT                                         \
 104              "movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */       \
 105              "movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */    \
 106              "call __switch_to\n\t"                                       \
 107              ".globl thread_return\n"                                     \
 108              "thread_return:\n\t"                                         \
 109              "movq "__percpu_arg([current_task])",%%rsi\n\t"              \
 110              __switch_canary                                              \
 111              "movq %P[thread_info](%%rsi),%%r8\n\t"                       \
 112              LOCK_PREFIX "btr  %[tif_fork],%P[ti_flags](%%r8)\n\t"        \
 113              "movq %%rax,%%rdi\n\t"                                       \
 114              "jc   ret_from_fork\n\t"                                     \
 115              RESTORE_CONTEXT                                              \
 116              : "=a" (last)                                                \
 117              : [next] "S" (next), [prev] "D" (prev),                      \
 118                [threadrsp] "i" (offsetof(struct task_struct, thread.sp)), \
 119                [ti_flags] "i" (offsetof(struct thread_info, flags)),      \
 120                [tif_fork] "i" (TIF_FORK),                                 \
 121                [thread_info] "i" (offsetof(struct task_struct, stack)),   \
 122                [current_task] "m" (per_cpu_var(current_task))             \
 123                __switch_canary_param                                      \
 124              : "memory", "cc" __EXTRA_CLOBBER)
 125 #endif
 126
 127 #ifdef __KERNEL__
 128 #define _set_base(addr, base) do { unsigned long __pr; \
 129 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
 130         "rorl $16,%%edx\n\t" \
 131         "movb %%dl,%2\n\t" \
 132         "movb %%dh,%3" \
 133         :"=&d" (__pr) \
 134         :"m" (*((addr)+2)), \
 135          "m" (*((addr)+4)), \
 136          "m" (*((addr)+7)), \
 137          "0" (base) \
 138         ); } while (0)
 139
 140 #define _set_limit(addr, limit) do { unsigned long __lr; \
 141 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
 142         "rorl $16,%%edx\n\t" \
 143         "movb %2,%%dh\n\t" \
 144         "andb $0xf0,%%dh\n\t" \
 145         "orb %%dh,%%dl\n\t" \
 146         "movb %%dl,%2" \
 147         :"=&d" (__lr) \
 148         :"m" (*(addr)), \
 149          "m" (*((addr)+6)), \
 150          "0" (limit) \
 151         ); } while (0)
 152
 153 #define set_base(ldt, base) _set_base(((char *)&(ldt)) , (base))
 154 #define set_limit(ldt, limit) _set_limit(((char *)&(ldt)) , ((limit)-1))
 155
 156 extern void native_load_gs_index(unsigned);
 157
 158 /*
 159  * Load a segment. Fall back on loading the zero
 160  * segment if something goes wrong..
 161  */
 162 #define loadsegment(seg, value)                 \
 163         asm volatile("\n"                       \
 164                      "1:\t"                     \
 165                      "movl %k0,%%" #seg "\n"    \
 166                      "2:\n"                     \
 167                      ".section .fixup,\"ax\"\n" \
 168                      "3:\t"                     \
 169                      "movl %k1, %%" #seg "\n\t" \
 170                      "jmp 2b\n"                 \
 171                      ".previous\n"              \
 172                      _ASM_EXTABLE(1b,3b)        \
 173                      : :"r" (value), "r" (0) : "memory")
 174
 175
 176 /*
 177  * Save a segment register away
 178  */
 179 #define savesegment(seg, value)                         \
 180         asm("mov %%" #seg ",%0":"=r" (value) : : "memory")
 181
 182 static inline unsigned long get_limit(unsigned long segment)
 183 {
 184         unsigned long __limit;
 185         asm("lsll %1,%0" : "=r" (__limit) : "r" (segment));
 186         return __limit + 1;
 187 }
 188
 189 static inline void native_clts(void)
 190 {
 191         asm volatile("clts");
 192 }
 193
 194 /*
 195  * Volatile isn't enough to prevent the compiler from reordering the
 196  * read/write functions for the control registers and messing everything up.
 197  * A memory clobber would solve the problem, but would prevent reordering of
 198  * all loads stores around it, which can hurt performance. Solution is to
 199  * use a variable and mimic reads and writes to it to enforce serialization
 200  */
 201 static unsigned long __force_order;
 202
 203 static inline unsigned long native_read_cr0(void)
 204 {
 205         unsigned long val;
 206         asm volatile("mov %%cr0,%0\n\t" : "=r" (val), "=m" (__force_order));
 207         return val;
 208 }
 209
 210 static inline void native_write_cr0(unsigned long val)
 211 {
 212         asm volatile("mov %0,%%cr0": : "r" (val), "m" (__force_order));
 213 }
 214
 215 static inline unsigned long native_read_cr2(void)
 216 {
 217         unsigned long val;
 218         asm volatile("mov %%cr2,%0\n\t" : "=r" (val), "=m" (__force_order));
 219         return val;
 220 }
 221
 222 static inline void native_write_cr2(unsigned long val)
 223 {
 224         asm volatile("mov %0,%%cr2": : "r" (val), "m" (__force_order));
 225 }
 226
 227 static inline unsigned long native_read_cr3(void)
 228 {
 229         unsigned long val;
 230         asm volatile("mov %%cr3,%0\n\t" : "=r" (val), "=m" (__force_order));
 231         return val;
 232 }
 233
 234 static inline void native_write_cr3(unsigned long val)
 235 {
 236         asm volatile("mov %0,%%cr3": : "r" (val), "m" (__force_order));
 237 }
 238
 239 static inline unsigned long native_read_cr4(void)
 240 {
 241         unsigned long val;
 242         asm volatile("mov %%cr4,%0\n\t" : "=r" (val), "=m" (__force_order));
 243         return val;
 244 }
 245
 246 static inline unsigned long native_read_cr4_safe(void)
 247 {
 248         unsigned long val;
 249         /* This could fault if %cr4 does not exist. In x86_64, a cr4 always
 250          * exists, so it will never fail. */
 251 #ifdef CONFIG_X86_32
 252         asm volatile("1: mov %%cr4, %0\n"
 253                      "2:\n"
 254                      _ASM_EXTABLE(1b, 2b)
 255                      : "=r" (val), "=m" (__force_order) : "0" (0));
 256 #else
 257         val = native_read_cr4();
 258 #endif
 259         return val;
 260 }
 261
 262 static inline void native_write_cr4(unsigned long val)
 263 {
 264         asm volatile("mov %0,%%cr4": : "r" (val), "m" (__force_order));
 265 }
 266
 267 #ifdef CONFIG_X86_64
 268 static inline unsigned long native_read_cr8(void)
 269 {
 270         unsigned long cr8;
 271         asm volatile("movq %%cr8,%0" : "=r" (cr8));
 272         return cr8;
 273 }
 274
 275 static inline void native_write_cr8(unsigned long val)
 276 {
 277         asm volatile("movq %0,%%cr8" :: "r" (val) : "memory");
 278 }
 279 #endif
 280
 281 static inline void native_wbinvd(void)
 282 {
 283         asm volatile("wbinvd": : :"memory");
 284 }
 285
 286 #ifdef CONFIG_PARAVIRT
 287 #include <asm/paravirt.h>
 288 #else
 289 #define read_cr0()      (native_read_cr0())
 290 #define write_cr0(x)    (native_write_cr0(x))
 291 #define read_cr2()      (native_read_cr2())
 292 #define write_cr2(x)    (native_write_cr2(x))
 293 #define read_cr3()      (native_read_cr3())
 294 #define write_cr3(x)    (native_write_cr3(x))
 295 #define read_cr4()      (native_read_cr4())
 296 #define read_cr4_safe() (native_read_cr4_safe())
 297 #define write_cr4(x)    (native_write_cr4(x))
 298 #define wbinvd()        (native_wbinvd())
 299 #ifdef CONFIG_X86_64
 300 #define read_cr8()      (native_read_cr8())
 301 #define write_cr8(x)    (native_write_cr8(x))
 302 #define load_gs_index   native_load_gs_index
 303 #endif
 304
 305 /* Clear the 'TS' bit */
 306 #define clts()          (native_clts())
 307
 308 #endif/* CONFIG_PARAVIRT */
 309
 310 #define stts() write_cr0(read_cr0() | X86_CR0_TS)
 311
 312 #endif /* __KERNEL__ */
 313
 314 static inline void clflush(volatile void *__p)
 315 {
 316         asm volatile("clflush %0" : "+m" (*(volatile char __force *)__p));
 317 }
 318
 319 #define nop() asm volatile ("nop")
 320
 321 void disable_hlt(void);
 322 void enable_hlt(void);
 323
 324 void cpu_idle_wait(void);
 325
 326 extern unsigned long arch_align_stack(unsigned long sp);
 327 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
 328
 329 void default_idle(void);
 330
 331 void stop_this_cpu(void *dummy);
 332
 333 /*
 334  * Force strict CPU ordering.
 335  * And yes, this is required on UP too when we're talking
 336  * to devices.
 337  */
 338 #ifdef CONFIG_X86_32
 339 /*
 340  * Some non-Intel clones support out of order store. wmb() ceases to be a
 341  * nop for these.
 342  */
 343 #define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
 344 #define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
 345 #define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
 346 #else
 347 #define mb()    asm volatile("mfence":::"memory")
 348 #define rmb()   asm volatile("lfence":::"memory")
 349 #define wmb()   asm volatile("sfence" ::: "memory")
 350 #endif
 351
 352 /**
 353  * read_barrier_depends - Flush all pending reads that subsequents reads
 354  * depend on.
 355  *
 356  * No data-dependent reads from memory-like regions are ever reordered
 357  * over this barrier.  All reads preceding this primitive are guaranteed
 358  * to access memory (but not necessarily other CPUs' caches) before any
 359  * reads following this primitive that depend on the data return by
 360  * any of the preceding reads.  This primitive is much lighter weight than
 361  * rmb() on most CPUs, and is never heavier weight than is
 362  * rmb().
 363  *
 364  * These ordering constraints are respected by both the local CPU
 365  * and the compiler.
 366  *
 367  * Ordering is not guaranteed by anything other than these primitives,
 368  * not even by data dependencies.  See the documentation for
 369  * memory_barrier() for examples and URLs to more information.
 370  *
 371  * For example, the following code would force ordering (the initial
 372  * value of "a" is zero, "b" is one, and "p" is "&a"):
 373  *
 374  * <programlisting>
 375  *      CPU 0                           CPU 1
 376  *
 377  *      b = 2;
 378  *      memory_barrier();
 379  *      p = &b;                         q = p;
 380  *                                      read_barrier_depends();
 381  *                                      d = *q;
 382  * </programlisting>
 383  *
 384  * because the read of "*q" depends on the read of "p" and these
 385  * two reads are separated by a read_barrier_depends().  However,
 386  * the following code, with the same initial values for "a" and "b":
 387  *
 388  * <programlisting>
 389  *      CPU 0                           CPU 1
 390  *
 391  *      a = 2;
 392  *      memory_barrier();
 393  *      b = 3;                          y = b;
 394  *                                      read_barrier_depends();
 395  *                                      x = a;
 396  * </programlisting>
 397  *
 398  * does not enforce ordering, since there is no data dependency between
 399  * the read of "a" and the read of "b".  Therefore, on some CPUs, such
 400  * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
 401  * in cases like this where there are no data dependencies.
 402  **/
 403
 404 #define read_barrier_depends()  do { } while (0)
 405
 406 #ifdef CONFIG_SMP
 407 #define smp_mb()        mb()
 408 #ifdef CONFIG_X86_PPRO_FENCE
 409 # define smp_rmb()      rmb()
 410 #else
 411 # define smp_rmb()      barrier()
 412 #endif
 413 #ifdef CONFIG_X86_OOSTORE
 414 # define smp_wmb()      wmb()
 415 #else
 416 # define smp_wmb()      barrier()
 417 #endif
 418 #define smp_read_barrier_depends()      read_barrier_depends()
 419 #define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
 420 #else
 421 #define smp_mb()        barrier()
 422 #define smp_rmb()       barrier()
 423 #define smp_wmb()       barrier()
 424 #define smp_read_barrier_depends()      do { } while (0)
 425 #define set_mb(var, value) do { var = value; barrier(); } while (0)
 426 #endif
 427
 428 /*
 429  * Stop RDTSC speculation. This is needed when you need to use RDTSC
 430  * (or get_cycles or vread that possibly accesses the TSC) in a defined
 431  * code region.
 432  *
 433  * (Could use an alternative three way for this if there was one.)
 434  */
 435 static inline void rdtsc_barrier(void)
 436 {
 437         alternative(ASM_NOP3, "mfence", X86_FEATURE_MFENCE_RDTSC);
 438         alternative(ASM_NOP3, "lfence", X86_FEATURE_LFENCE_RDTSC);
 439 }
 440
 441 #endif /* _ASM_X86_SYSTEM_H */