1 #ifndef _ASM_X86_MACH_DEFAULT_MACH_APIC_H
2 #define _ASM_X86_MACH_DEFAULT_MACH_APIC_H
4 #ifdef CONFIG_X86_LOCAL_APIC
6 #include <mach_apicdef.h>
9 #define APIC_DFR_VALUE (APIC_DFR_FLAT)
11 static inline const struct cpumask *default_target_cpus(void)
14 return cpu_online_mask;
21 #include <asm/genapic.h>
22 #define init_apic_ldr (apic->init_apic_ldr)
23 #define cpu_mask_to_apicid (apic->cpu_mask_to_apicid)
24 #define cpu_mask_to_apicid_and (apic->cpu_mask_to_apicid_and)
25 #define phys_pkg_id (apic->phys_pkg_id)
26 #define vector_allocation_domain (apic->vector_allocation_domain)
27 #define read_apic_id() (GET_APIC_ID(apic_read(APIC_ID)))
28 #define send_IPI_self (apic->send_IPI_self)
29 #define wakeup_secondary_cpu (apic->wakeup_cpu)
30 extern void setup_apic_routing(void);
32 #define wakeup_secondary_cpu wakeup_secondary_cpu_via_init
34 * Set up the logical destination ID.
36 * Intel recommends to set DFR, LDR and TPR before enabling
37 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
38 * document number 292116). So here it goes...
40 static inline void init_apic_ldr(void)
44 apic_write(APIC_DFR, APIC_DFR_VALUE);
45 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
46 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
47 apic_write(APIC_LDR, val);
50 static inline int default_apic_id_registered(void)
52 return physid_isset(read_apic_id(), phys_cpu_present_map);
55 static inline unsigned int cpu_mask_to_apicid(const struct cpumask *cpumask)
57 return cpumask_bits(cpumask)[0];
60 static inline unsigned int cpu_mask_to_apicid_and(const struct cpumask *cpumask,
61 const struct cpumask *andmask)
63 unsigned long mask1 = cpumask_bits(cpumask)[0];
64 unsigned long mask2 = cpumask_bits(andmask)[0];
65 unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];
67 return (unsigned int)(mask1 & mask2 & mask3);
70 static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
72 return cpuid_apic >> index_msb;
75 static inline void setup_apic_routing(void)
77 #ifdef CONFIG_X86_IO_APIC
78 printk("Enabling APIC mode: %s. Using %d I/O APICs\n",
83 static inline int apicid_to_node(int logical_apicid)
86 return apicid_2_node[hard_smp_processor_id()];
92 static inline void vector_allocation_domain(int cpu, struct cpumask *retmask)
94 /* Careful. Some cpus do not strictly honor the set of cpus
95 * specified in the interrupt destination when using lowest
96 * priority interrupt delivery mode.
98 * In particular there was a hyperthreading cpu observed to
99 * deliver interrupts to the wrong hyperthread when only one
100 * hyperthread was specified in the interrupt desitination.
102 *retmask = (cpumask_t) { { [0] = APIC_ALL_CPUS } };
106 static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid)
108 return physid_isset(apicid, bitmap);
111 static inline unsigned long default_check_apicid_present(int bit)
113 return physid_isset(bit, phys_cpu_present_map);
116 static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
121 static inline int multi_timer_check(int apic, int irq)
126 /* Mapping from cpu number to logical apicid */
127 static inline int cpu_to_logical_apicid(int cpu)
132 static inline int cpu_present_to_apicid(int mps_cpu)
134 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
135 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
140 static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
142 return physid_mask_of_physid(phys_apicid);
145 static inline void setup_portio_remap(void)
149 static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
151 return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map);
154 static inline void enable_apic_mode(void)
157 #endif /* CONFIG_X86_LOCAL_APIC */
158 #endif /* _ASM_X86_MACH_DEFAULT_MACH_APIC_H */