2 * Copyright (C) 2007-2009 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #ifndef _ASM_X86_AMD_IOMMU_TYPES_H
21 #define _ASM_X86_AMD_IOMMU_TYPES_H
23 #include <linux/types.h>
24 #include <linux/mutex.h>
25 #include <linux/list.h>
26 #include <linux/spinlock.h>
29 * Maximum number of IOMMUs supported
34 * some size calculation constants
36 #define DEV_TABLE_ENTRY_SIZE 32
37 #define ALIAS_TABLE_ENTRY_SIZE 2
38 #define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *))
40 /* Length of the MMIO region for the AMD IOMMU */
41 #define MMIO_REGION_LENGTH 0x4000
43 /* Capability offsets used by the driver */
44 #define MMIO_CAP_HDR_OFFSET 0x00
45 #define MMIO_RANGE_OFFSET 0x0c
46 #define MMIO_MISC_OFFSET 0x10
48 /* Masks, shifts and macros to parse the device range capability */
49 #define MMIO_RANGE_LD_MASK 0xff000000
50 #define MMIO_RANGE_FD_MASK 0x00ff0000
51 #define MMIO_RANGE_BUS_MASK 0x0000ff00
52 #define MMIO_RANGE_LD_SHIFT 24
53 #define MMIO_RANGE_FD_SHIFT 16
54 #define MMIO_RANGE_BUS_SHIFT 8
55 #define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
56 #define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
57 #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
58 #define MMIO_MSI_NUM(x) ((x) & 0x1f)
60 /* Flag masks for the AMD IOMMU exclusion range */
61 #define MMIO_EXCL_ENABLE_MASK 0x01ULL
62 #define MMIO_EXCL_ALLOW_MASK 0x02ULL
64 /* Used offsets into the MMIO space */
65 #define MMIO_DEV_TABLE_OFFSET 0x0000
66 #define MMIO_CMD_BUF_OFFSET 0x0008
67 #define MMIO_EVT_BUF_OFFSET 0x0010
68 #define MMIO_CONTROL_OFFSET 0x0018
69 #define MMIO_EXCL_BASE_OFFSET 0x0020
70 #define MMIO_EXCL_LIMIT_OFFSET 0x0028
71 #define MMIO_CMD_HEAD_OFFSET 0x2000
72 #define MMIO_CMD_TAIL_OFFSET 0x2008
73 #define MMIO_EVT_HEAD_OFFSET 0x2010
74 #define MMIO_EVT_TAIL_OFFSET 0x2018
75 #define MMIO_STATUS_OFFSET 0x2020
77 /* MMIO status bits */
78 #define MMIO_STATUS_COM_WAIT_INT_MASK 0x04
80 /* event logging constants */
81 #define EVENT_ENTRY_SIZE 0x10
82 #define EVENT_TYPE_SHIFT 28
83 #define EVENT_TYPE_MASK 0xf
84 #define EVENT_TYPE_ILL_DEV 0x1
85 #define EVENT_TYPE_IO_FAULT 0x2
86 #define EVENT_TYPE_DEV_TAB_ERR 0x3
87 #define EVENT_TYPE_PAGE_TAB_ERR 0x4
88 #define EVENT_TYPE_ILL_CMD 0x5
89 #define EVENT_TYPE_CMD_HARD_ERR 0x6
90 #define EVENT_TYPE_IOTLB_INV_TO 0x7
91 #define EVENT_TYPE_INV_DEV_REQ 0x8
92 #define EVENT_DEVID_MASK 0xffff
93 #define EVENT_DEVID_SHIFT 0
94 #define EVENT_DOMID_MASK 0xffff
95 #define EVENT_DOMID_SHIFT 0
96 #define EVENT_FLAGS_MASK 0xfff
97 #define EVENT_FLAGS_SHIFT 0x10
99 /* feature control bits */
100 #define CONTROL_IOMMU_EN 0x00ULL
101 #define CONTROL_HT_TUN_EN 0x01ULL
102 #define CONTROL_EVT_LOG_EN 0x02ULL
103 #define CONTROL_EVT_INT_EN 0x03ULL
104 #define CONTROL_COMWAIT_EN 0x04ULL
105 #define CONTROL_PASSPW_EN 0x08ULL
106 #define CONTROL_RESPASSPW_EN 0x09ULL
107 #define CONTROL_COHERENT_EN 0x0aULL
108 #define CONTROL_ISOC_EN 0x0bULL
109 #define CONTROL_CMDBUF_EN 0x0cULL
110 #define CONTROL_PPFLOG_EN 0x0dULL
111 #define CONTROL_PPFINT_EN 0x0eULL
113 /* command specific defines */
114 #define CMD_COMPL_WAIT 0x01
115 #define CMD_INV_DEV_ENTRY 0x02
116 #define CMD_INV_IOMMU_PAGES 0x03
118 #define CMD_COMPL_WAIT_STORE_MASK 0x01
119 #define CMD_COMPL_WAIT_INT_MASK 0x02
120 #define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01
121 #define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02
123 #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL
125 /* macros and definitions for device table entries */
126 #define DEV_ENTRY_VALID 0x00
127 #define DEV_ENTRY_TRANSLATION 0x01
128 #define DEV_ENTRY_IR 0x3d
129 #define DEV_ENTRY_IW 0x3e
130 #define DEV_ENTRY_NO_PAGE_FAULT 0x62
131 #define DEV_ENTRY_EX 0x67
132 #define DEV_ENTRY_SYSMGT1 0x68
133 #define DEV_ENTRY_SYSMGT2 0x69
134 #define DEV_ENTRY_INIT_PASS 0xb8
135 #define DEV_ENTRY_EINT_PASS 0xb9
136 #define DEV_ENTRY_NMI_PASS 0xba
137 #define DEV_ENTRY_LINT0_PASS 0xbe
138 #define DEV_ENTRY_LINT1_PASS 0xbf
139 #define DEV_ENTRY_MODE_MASK 0x07
140 #define DEV_ENTRY_MODE_SHIFT 0x09
142 /* constants to configure the command buffer */
143 #define CMD_BUFFER_SIZE 8192
144 #define CMD_BUFFER_ENTRIES 512
145 #define MMIO_CMD_SIZE_SHIFT 56
146 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
148 /* constants for event buffer handling */
149 #define EVT_BUFFER_SIZE 8192 /* 512 entries */
150 #define EVT_LEN_MASK (0x9ULL << 56)
152 #define PAGE_MODE_NONE 0x00
153 #define PAGE_MODE_1_LEVEL 0x01
154 #define PAGE_MODE_2_LEVEL 0x02
155 #define PAGE_MODE_3_LEVEL 0x03
156 #define PAGE_MODE_4_LEVEL 0x04
157 #define PAGE_MODE_5_LEVEL 0x05
158 #define PAGE_MODE_6_LEVEL 0x06
160 #define PM_LEVEL_SHIFT(x) (12 + ((x) * 9))
161 #define PM_LEVEL_SIZE(x) (((x) < 6) ? \
162 ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \
163 (0xffffffffffffffffULL))
164 #define PM_LEVEL_INDEX(x, a) (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL)
165 #define PM_LEVEL_ENC(x) (((x) << 9) & 0xe00ULL)
166 #define PM_LEVEL_PDE(x, a) ((a) | PM_LEVEL_ENC((x)) | \
167 IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
168 #define PM_PTE_LEVEL(pte) (((pte) >> 9) & 0x7ULL)
171 #define PM_ADDR_MASK 0x000ffffffffff000ULL
172 #define PM_MAP_MASK(lvl) (PM_ADDR_MASK & \
173 (~((1ULL << (12 + ((lvl) * 9))) - 1)))
174 #define PM_ALIGNED(lvl, addr) ((PM_MAP_MASK(lvl) & (addr)) == (addr))
176 #define IOMMU_PTE_P (1ULL << 0)
177 #define IOMMU_PTE_TV (1ULL << 1)
178 #define IOMMU_PTE_U (1ULL << 59)
179 #define IOMMU_PTE_FC (1ULL << 60)
180 #define IOMMU_PTE_IR (1ULL << 61)
181 #define IOMMU_PTE_IW (1ULL << 62)
183 #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
184 #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P)
185 #define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK))
186 #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)
188 #define IOMMU_PROT_MASK 0x03
189 #define IOMMU_PROT_IR 0x01
190 #define IOMMU_PROT_IW 0x02
192 /* IOMMU capabilities */
193 #define IOMMU_CAP_IOTLB 24
194 #define IOMMU_CAP_NPCACHE 26
196 #define MAX_DOMAIN_ID 65536
198 /* FIXME: move this macro to <linux/pci.h> */
199 #define PCI_BUS(x) (((x) >> 8) & 0xff)
201 /* Protection domain flags */
202 #define PD_DMA_OPS_MASK (1UL << 0) /* domain used for dma_ops */
203 #define PD_DEFAULT_MASK (1UL << 1) /* domain is a default dma_ops
204 domain for an IOMMU */
205 #define PD_PASSTHROUGH_MASK (1UL << 2) /* domain has no page
208 extern bool amd_iommu_dump;
209 #define DUMP_printk(format, arg...) \
211 if (amd_iommu_dump) \
212 printk(KERN_INFO "AMD-Vi: " format, ## arg); \
215 /* global flag if IOMMUs cache non-present entries */
216 extern bool amd_iommu_np_cache;
219 * Make iterating over all IOMMUs easier
221 #define for_each_iommu(iommu) \
222 list_for_each_entry((iommu), &amd_iommu_list, list)
223 #define for_each_iommu_safe(iommu, next) \
224 list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list)
226 #define APERTURE_RANGE_SHIFT 27 /* 128 MB */
227 #define APERTURE_RANGE_SIZE (1ULL << APERTURE_RANGE_SHIFT)
228 #define APERTURE_RANGE_PAGES (APERTURE_RANGE_SIZE >> PAGE_SHIFT)
229 #define APERTURE_MAX_RANGES 32 /* allows 4GB of DMA address space */
230 #define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT)
231 #define APERTURE_PAGE_INDEX(a) (((a) >> 21) & 0x3fULL)
234 * This structure contains generic data for IOMMU protection domains
235 * independent of their use.
237 struct protection_domain {
238 struct list_head list; /* for list of all protection domains */
239 struct list_head dev_list; /* List of all devices in this domain */
240 spinlock_t lock; /* mostly used to lock the page table*/
241 struct mutex api_lock; /* protect page tables in the iommu-api path */
242 u16 id; /* the domain id written to the device table */
243 int mode; /* paging mode (0-6 levels) */
244 u64 *pt_root; /* page table root pointer */
245 unsigned long flags; /* flags to find out type of domain */
246 bool updated; /* complete domain flush required */
247 unsigned dev_cnt; /* devices assigned to this domain */
248 unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */
249 void *priv; /* private data */
254 * This struct contains device specific data for the IOMMU
256 struct iommu_dev_data {
257 struct list_head list; /* For domain->dev_list */
258 struct device *dev; /* Device this data belong to */
259 struct device *alias; /* The Alias Device */
260 struct protection_domain *domain; /* Domain the device is bound to */
261 atomic_t bind; /* Domain attach reverent count */
265 * For dynamic growth the aperture size is split into ranges of 128MB of
266 * DMA address space each. This struct represents one such range.
268 struct aperture_range {
270 /* address allocation bitmap */
271 unsigned long *bitmap;
274 * Array of PTE pages for the aperture. In this array we save all the
275 * leaf pages of the domain page table used for the aperture. This way
276 * we don't need to walk the page table to find a specific PTE. We can
277 * just calculate its address in constant time.
281 unsigned long offset;
285 * Data container for a dma_ops specific protection domain
287 struct dma_ops_domain {
288 struct list_head list;
290 /* generic protection domain information */
291 struct protection_domain domain;
293 /* size of the aperture for the mappings */
294 unsigned long aperture_size;
296 /* address we start to search for free addresses */
297 unsigned long next_address;
299 /* address space relevant data */
300 struct aperture_range *aperture[APERTURE_MAX_RANGES];
302 /* This will be set to true when TLB needs to be flushed */
306 * if this is a preallocated domain, keep the device for which it was
307 * preallocated in this variable
313 * Structure where we save information about one hardware AMD IOMMU in the
317 struct list_head list;
319 /* Index within the IOMMU array */
322 /* locks the accesses to the hardware */
325 /* Pointer to PCI device of this IOMMU */
328 /* physical address of MMIO space */
330 /* virtual address of MMIO space */
333 /* capabilities of that IOMMU read from ACPI */
337 * Capability pointer. There could be more than one IOMMU per PCI
338 * device function if there are more than one AMD IOMMU capability
343 /* pci domain of this IOMMU */
346 /* first device this IOMMU handles. read from PCI */
348 /* last device this IOMMU handles. read from PCI */
351 /* start of exclusion range of that IOMMU */
353 /* length of exclusion range of that IOMMU */
354 u64 exclusion_length;
356 /* command buffer virtual address */
358 /* size of command buffer */
361 /* size of event buffer */
363 /* event buffer virtual address */
365 /* MSI number for event interrupt */
368 /* true if interrupts for this IOMMU are already enabled */
371 /* if one, we need to send a completion wait command */
374 /* becomes true if a command buffer reset is running */
375 bool reset_in_progress;
377 /* default dma_ops domain for that IOMMU */
378 struct dma_ops_domain *default_dom;
382 * List with all IOMMUs in the system. This list is not locked because it is
383 * only written and read at driver initialization or suspend time
385 extern struct list_head amd_iommu_list;
388 * Array with pointers to each IOMMU struct
389 * The indices are referenced in the protection domains
391 extern struct amd_iommu *amd_iommus[MAX_IOMMUS];
393 /* Number of IOMMUs present in the system */
394 extern int amd_iommus_present;
397 * Declarations for the global list of all protection domains
399 extern spinlock_t amd_iommu_pd_lock;
400 extern struct list_head amd_iommu_pd_list;
403 * Structure defining one entry in the device table
405 struct dev_table_entry {
410 * One entry for unity mappings parsed out of the ACPI table.
412 struct unity_map_entry {
413 struct list_head list;
415 /* starting device id this entry is used for (including) */
417 /* end device id this entry is used for (including) */
420 /* start address to unity map (including) */
422 /* end address to unity map (including) */
425 /* required protection */
430 * List of all unity mappings. It is not locked because as runtime it is only
431 * read. It is created at ACPI table parsing time.
433 extern struct list_head amd_iommu_unity_map;
436 * Data structures for device handling
440 * Device table used by hardware. Read and write accesses by software are
441 * locked with the amd_iommu_pd_table lock.
443 extern struct dev_table_entry *amd_iommu_dev_table;
446 * Alias table to find requestor ids to device ids. Not locked because only
449 extern u16 *amd_iommu_alias_table;
452 * Reverse lookup table to find the IOMMU which translates a specific device.
454 extern struct amd_iommu **amd_iommu_rlookup_table;
456 /* size of the dma_ops aperture as power of 2 */
457 extern unsigned amd_iommu_aperture_order;
459 /* largest PCI device id we expect translation requests for */
460 extern u16 amd_iommu_last_bdf;
462 /* allocation bitmap for domain ids */
463 extern unsigned long *amd_iommu_pd_alloc_bitmap;
466 * If true, the addresses will be flushed on unmap time, not when
469 extern bool amd_iommu_unmap_flush;
471 /* takes bus and device/function and returns the device id
472 * FIXME: should that be in generic PCI code? */
473 static inline u16 calc_devid(u8 bus, u8 devfn)
475 return (((u16)bus) << 8) | devfn;
478 #ifdef CONFIG_AMD_IOMMU_STATS
480 struct __iommu_counter {
486 #define DECLARE_STATS_COUNTER(nm) \
487 static struct __iommu_counter nm = { \
491 #define INC_STATS_COUNTER(name) name.value += 1
492 #define ADD_STATS_COUNTER(name, x) name.value += (x)
493 #define SUB_STATS_COUNTER(name, x) name.value -= (x)
495 #else /* CONFIG_AMD_IOMMU_STATS */
497 #define DECLARE_STATS_COUNTER(name)
498 #define INC_STATS_COUNTER(name)
499 #define ADD_STATS_COUNTER(name, x)
500 #define SUB_STATS_COUNTER(name, x)
502 #endif /* CONFIG_AMD_IOMMU_STATS */
504 #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */