1 /* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 #include <linux/config.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
15 #include <linux/hugetlb.h>
16 #include <linux/slab.h>
17 #include <linux/initrd.h>
18 #include <linux/swap.h>
19 #include <linux/pagemap.h>
21 #include <linux/seq_file.h>
22 #include <linux/kprobes.h>
23 #include <linux/cache.h>
24 #include <linux/sort.h>
27 #include <asm/system.h>
29 #include <asm/pgalloc.h>
30 #include <asm/pgtable.h>
31 #include <asm/oplib.h>
32 #include <asm/iommu.h>
34 #include <asm/uaccess.h>
35 #include <asm/mmu_context.h>
36 #include <asm/tlbflush.h>
38 #include <asm/starfire.h>
40 #include <asm/spitfire.h>
41 #include <asm/sections.h>
43 #include <asm/hypervisor.h>
45 extern void device_scan(void);
49 static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
50 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
51 static int pavail_ents __initdata;
52 static int pavail_rescan_ents __initdata;
54 static int cmp_p64(const void *a, const void *b)
56 const struct linux_prom64_registers *x = a, *y = b;
58 if (x->phys_addr > y->phys_addr)
60 if (x->phys_addr < y->phys_addr)
65 static void __init read_obp_memory(const char *property,
66 struct linux_prom64_registers *regs,
69 int node = prom_finddevice("/memory");
70 int prop_size = prom_getproplen(node, property);
73 ents = prop_size / sizeof(struct linux_prom64_registers);
74 if (ents > MAX_BANKS) {
75 prom_printf("The machine has more %s property entries than "
76 "this kernel can support (%d).\n",
81 ret = prom_getproperty(node, property, (char *) regs, prop_size);
83 prom_printf("Couldn't get %s property from /memory.\n");
89 /* Sanitize what we got from the firmware, by page aligning
92 for (i = 0; i < ents; i++) {
93 unsigned long base, size;
95 base = regs[i].phys_addr;
96 size = regs[i].reg_size;
99 if (base & ~PAGE_MASK) {
100 unsigned long new_base = PAGE_ALIGN(base);
102 size -= new_base - base;
103 if ((long) size < 0L)
107 regs[i].phys_addr = base;
108 regs[i].reg_size = size;
110 sort(regs, ents, sizeof(struct linux_prom64_registers),
114 unsigned long *sparc64_valid_addr_bitmap __read_mostly;
116 /* Ugly, but necessary... -DaveM */
117 unsigned long phys_base __read_mostly;
118 unsigned long kern_base __read_mostly;
119 unsigned long kern_size __read_mostly;
120 unsigned long pfn_base __read_mostly;
122 /* get_new_mmu_context() uses "cache + 1". */
123 DEFINE_SPINLOCK(ctx_alloc_lock);
124 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
125 #define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
126 unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
128 /* References to special section boundaries */
129 extern char _start[], _end[];
131 /* Initial ramdisk setup */
132 extern unsigned long sparc_ramdisk_image64;
133 extern unsigned int sparc_ramdisk_image;
134 extern unsigned int sparc_ramdisk_size;
136 struct page *mem_map_zero __read_mostly;
138 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
140 unsigned long sparc64_kern_pri_context __read_mostly;
141 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
142 unsigned long sparc64_kern_sec_context __read_mostly;
146 kmem_cache_t *pgtable_cache __read_mostly;
148 static void zero_ctor(void *addr, kmem_cache_t *cache, unsigned long flags)
153 void pgtable_cache_init(void)
155 pgtable_cache = kmem_cache_create("pgtable_cache",
156 PAGE_SIZE, PAGE_SIZE,
158 SLAB_MUST_HWCACHE_ALIGN,
161 if (!pgtable_cache) {
162 prom_printf("pgtable_cache_init(): Could not create!\n");
167 #ifdef CONFIG_DEBUG_DCFLUSH
168 atomic_t dcpage_flushes = ATOMIC_INIT(0);
170 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
174 __inline__ void flush_dcache_page_impl(struct page *page)
176 #ifdef CONFIG_DEBUG_DCFLUSH
177 atomic_inc(&dcpage_flushes);
180 #ifdef DCACHE_ALIASING_POSSIBLE
181 __flush_dcache_page(page_address(page),
182 ((tlb_type == spitfire) &&
183 page_mapping(page) != NULL));
185 if (page_mapping(page) != NULL &&
186 tlb_type == spitfire)
187 __flush_icache_page(__pa(page_address(page)));
191 #define PG_dcache_dirty PG_arch_1
192 #define PG_dcache_cpu_shift 24
193 #define PG_dcache_cpu_mask (256 - 1)
196 #error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
199 #define dcache_dirty_cpu(page) \
200 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
202 static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
204 unsigned long mask = this_cpu;
205 unsigned long non_cpu_bits;
207 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
208 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
210 __asm__ __volatile__("1:\n\t"
212 "and %%g7, %1, %%g1\n\t"
213 "or %%g1, %0, %%g1\n\t"
214 "casx [%2], %%g7, %%g1\n\t"
216 "membar #StoreLoad | #StoreStore\n\t"
217 "bne,pn %%xcc, 1b\n\t"
220 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
224 static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
226 unsigned long mask = (1UL << PG_dcache_dirty);
228 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
231 "srlx %%g7, %4, %%g1\n\t"
232 "and %%g1, %3, %%g1\n\t"
234 "bne,pn %%icc, 2f\n\t"
235 " andn %%g7, %1, %%g1\n\t"
236 "casx [%2], %%g7, %%g1\n\t"
238 "membar #StoreLoad | #StoreStore\n\t"
239 "bne,pn %%xcc, 1b\n\t"
243 : "r" (cpu), "r" (mask), "r" (&page->flags),
244 "i" (PG_dcache_cpu_mask),
245 "i" (PG_dcache_cpu_shift)
249 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
251 unsigned long tsb_addr = (unsigned long) ent;
253 if (tlb_type == cheetah_plus)
254 tsb_addr = __pa(tsb_addr);
256 __tsb_insert(tsb_addr, tag, pte);
259 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
261 struct mm_struct *mm;
264 unsigned long pg_flags;
267 if (pfn_valid(pfn) &&
268 (page = pfn_to_page(pfn), page_mapping(page)) &&
269 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
270 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
272 int this_cpu = get_cpu();
274 /* This is just to optimize away some function calls
278 flush_dcache_page_impl(page);
280 smp_flush_dcache_page_impl(page, cpu);
282 clear_dcache_dirty_cpu(page, cpu);
288 if ((pte_val(pte) & _PAGE_ALL_SZ_BITS) == _PAGE_SZBITS) {
292 tsb = &mm->context.tsb[(address >> PAGE_SHIFT) &
293 (mm->context.tsb_nentries - 1UL)];
294 tag = (address >> 22UL) | CTX_HWBITS(mm->context) << 48UL;
295 tsb_insert(tsb, tag, pte_val(pte));
299 void flush_dcache_page(struct page *page)
301 struct address_space *mapping;
304 /* Do not bother with the expensive D-cache flush if it
305 * is merely the zero page. The 'bigcore' testcase in GDB
306 * causes this case to run millions of times.
308 if (page == ZERO_PAGE(0))
311 this_cpu = get_cpu();
313 mapping = page_mapping(page);
314 if (mapping && !mapping_mapped(mapping)) {
315 int dirty = test_bit(PG_dcache_dirty, &page->flags);
317 int dirty_cpu = dcache_dirty_cpu(page);
319 if (dirty_cpu == this_cpu)
321 smp_flush_dcache_page_impl(page, dirty_cpu);
323 set_dcache_dirty(page, this_cpu);
325 /* We could delay the flush for the !page_mapping
326 * case too. But that case is for exec env/arg
327 * pages and those are %99 certainly going to get
328 * faulted into the tlb (and thus flushed) anyways.
330 flush_dcache_page_impl(page);
337 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
339 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
340 if (tlb_type == spitfire) {
343 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
344 __flush_icache_page(__get_phys(kaddr));
348 unsigned long page_to_pfn(struct page *page)
350 return (unsigned long) ((page - mem_map) + pfn_base);
353 struct page *pfn_to_page(unsigned long pfn)
355 return (mem_map + (pfn - pfn_base));
360 printk("Mem-info:\n");
362 printk("Free swap: %6ldkB\n",
363 nr_swap_pages << (PAGE_SHIFT-10));
364 printk("%ld pages of RAM\n", num_physpages);
365 printk("%d free pages\n", nr_free_pages());
368 void mmu_info(struct seq_file *m)
370 if (tlb_type == cheetah)
371 seq_printf(m, "MMU Type\t: Cheetah\n");
372 else if (tlb_type == cheetah_plus)
373 seq_printf(m, "MMU Type\t: Cheetah+\n");
374 else if (tlb_type == spitfire)
375 seq_printf(m, "MMU Type\t: Spitfire\n");
376 else if (tlb_type == hypervisor)
377 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
379 seq_printf(m, "MMU Type\t: ???\n");
381 #ifdef CONFIG_DEBUG_DCFLUSH
382 seq_printf(m, "DCPageFlushes\t: %d\n",
383 atomic_read(&dcpage_flushes));
385 seq_printf(m, "DCPageFlushesXC\t: %d\n",
386 atomic_read(&dcpage_flushes_xcall));
387 #endif /* CONFIG_SMP */
388 #endif /* CONFIG_DEBUG_DCFLUSH */
391 struct linux_prom_translation {
397 /* Exported for kernel TLB miss handling in ktlb.S */
398 struct linux_prom_translation prom_trans[512] __read_mostly;
399 unsigned int prom_trans_ents __read_mostly;
401 extern unsigned long prom_boot_page;
402 extern void prom_remap(unsigned long physpage, unsigned long virtpage, int mmu_ihandle);
403 extern int prom_get_mmu_ihandle(void);
404 extern void register_prom_callbacks(void);
406 /* Exported for SMP bootup purposes. */
407 unsigned long kern_locked_tte_data;
410 * Translate PROM's mapping we capture at boot time into physical address.
411 * The second parameter is only set from prom_callback() invocations.
413 unsigned long prom_virt_to_phys(unsigned long promva, int *error)
417 for (i = 0; i < prom_trans_ents; i++) {
418 struct linux_prom_translation *p = &prom_trans[i];
420 if (promva >= p->virt &&
421 promva < (p->virt + p->size)) {
422 unsigned long base = p->data & _PAGE_PADDR;
426 return base + (promva & (8192 - 1));
434 /* The obp translations are saved based on 8k pagesize, since obp can
435 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
436 * HI_OBP_ADDRESS range are handled in ktlb.S.
438 static inline int in_obp_range(unsigned long vaddr)
440 return (vaddr >= LOW_OBP_ADDRESS &&
441 vaddr < HI_OBP_ADDRESS);
444 static int cmp_ptrans(const void *a, const void *b)
446 const struct linux_prom_translation *x = a, *y = b;
448 if (x->virt > y->virt)
450 if (x->virt < y->virt)
455 /* Read OBP translations property into 'prom_trans[]'. */
456 static void __init read_obp_translations(void)
458 int n, node, ents, first, last, i;
460 node = prom_finddevice("/virtual-memory");
461 n = prom_getproplen(node, "translations");
462 if (unlikely(n == 0 || n == -1)) {
463 prom_printf("prom_mappings: Couldn't get size.\n");
466 if (unlikely(n > sizeof(prom_trans))) {
467 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
471 if ((n = prom_getproperty(node, "translations",
472 (char *)&prom_trans[0],
473 sizeof(prom_trans))) == -1) {
474 prom_printf("prom_mappings: Couldn't get property.\n");
478 n = n / sizeof(struct linux_prom_translation);
482 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
485 /* Now kick out all the non-OBP entries. */
486 for (i = 0; i < ents; i++) {
487 if (in_obp_range(prom_trans[i].virt))
491 for (; i < ents; i++) {
492 if (!in_obp_range(prom_trans[i].virt))
497 for (i = 0; i < (last - first); i++) {
498 struct linux_prom_translation *src = &prom_trans[i + first];
499 struct linux_prom_translation *dest = &prom_trans[i];
503 for (; i < ents; i++) {
504 struct linux_prom_translation *dest = &prom_trans[i];
505 dest->virt = dest->size = dest->data = 0x0UL;
508 prom_trans_ents = last - first;
510 if (tlb_type == spitfire) {
511 /* Clear diag TTE bits. */
512 for (i = 0; i < prom_trans_ents; i++)
513 prom_trans[i].data &= ~0x0003fe0000000000UL;
517 static void __init remap_kernel(void)
519 unsigned long phys_page, tte_vaddr, tte_data;
520 int tlb_ent = sparc64_highest_locked_tlbent();
522 tte_vaddr = (unsigned long) KERNBASE;
523 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
524 tte_data = (phys_page | (_PAGE_VALID | _PAGE_SZ4MB |
525 _PAGE_CP | _PAGE_CV | _PAGE_P |
528 kern_locked_tte_data = tte_data;
530 /* Now lock us into the TLBs via OBP. */
531 prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
532 prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
535 prom_dtlb_load(tlb_ent,
537 tte_vaddr + 0x400000);
538 prom_itlb_load(tlb_ent,
540 tte_vaddr + 0x400000);
542 sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
543 if (tlb_type == cheetah_plus) {
544 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
545 CTX_CHEETAH_PLUS_NUC);
546 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
547 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
552 static void __init inherit_prom_mappings(void)
554 read_obp_translations();
556 /* Now fixup OBP's idea about where we really are mapped. */
557 prom_printf("Remapping the kernel... ");
559 prom_printf("done.\n");
561 prom_printf("Registering callbacks... ");
562 register_prom_callbacks();
563 prom_printf("done.\n");
566 void prom_world(int enter)
569 set_fs((mm_segment_t) { get_thread_current_ds() });
571 __asm__ __volatile__("flushw");
574 #ifdef DCACHE_ALIASING_POSSIBLE
575 void __flush_dcache_range(unsigned long start, unsigned long end)
579 if (tlb_type == spitfire) {
582 for (va = start; va < end; va += 32) {
583 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
587 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
590 for (va = start; va < end; va += 32)
591 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
595 "i" (ASI_DCACHE_INVALIDATE));
598 #endif /* DCACHE_ALIASING_POSSIBLE */
600 /* If not locked, zap it. */
601 void __flush_tlb_all(void)
603 unsigned long pstate;
606 __asm__ __volatile__("flushw\n\t"
607 "rdpr %%pstate, %0\n\t"
608 "wrpr %0, %1, %%pstate"
611 if (tlb_type == spitfire) {
612 for (i = 0; i < 64; i++) {
613 /* Spitfire Errata #32 workaround */
614 /* NOTE: Always runs on spitfire, so no
615 * cheetah+ page size encodings.
617 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
621 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
623 if (!(spitfire_get_dtlb_data(i) & _PAGE_L)) {
624 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
627 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
628 spitfire_put_dtlb_data(i, 0x0UL);
631 /* Spitfire Errata #32 workaround */
632 /* NOTE: Always runs on spitfire, so no
633 * cheetah+ page size encodings.
635 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
639 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
641 if (!(spitfire_get_itlb_data(i) & _PAGE_L)) {
642 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
645 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
646 spitfire_put_itlb_data(i, 0x0UL);
649 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
650 cheetah_flush_dtlb_all();
651 cheetah_flush_itlb_all();
653 __asm__ __volatile__("wrpr %0, 0, %%pstate"
657 /* Caller does TLB context flushing on local CPU if necessary.
658 * The caller also ensures that CTX_VALID(mm->context) is false.
660 * We must be careful about boundary cases so that we never
661 * let the user have CTX 0 (nucleus) or we ever use a CTX
662 * version of zero (and thus NO_CONTEXT would not be caught
663 * by version mis-match tests in mmu_context.h).
665 void get_new_mmu_context(struct mm_struct *mm)
667 unsigned long ctx, new_ctx;
668 unsigned long orig_pgsz_bits;
671 spin_lock(&ctx_alloc_lock);
672 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
673 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
674 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
675 if (new_ctx >= (1 << CTX_NR_BITS)) {
676 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
677 if (new_ctx >= ctx) {
679 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
682 new_ctx = CTX_FIRST_VERSION;
684 /* Don't call memset, for 16 entries that's just
687 mmu_context_bmap[0] = 3;
688 mmu_context_bmap[1] = 0;
689 mmu_context_bmap[2] = 0;
690 mmu_context_bmap[3] = 0;
691 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
692 mmu_context_bmap[i + 0] = 0;
693 mmu_context_bmap[i + 1] = 0;
694 mmu_context_bmap[i + 2] = 0;
695 mmu_context_bmap[i + 3] = 0;
700 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
701 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
703 tlb_context_cache = new_ctx;
704 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
705 spin_unlock(&ctx_alloc_lock);
708 void sparc_ultra_dump_itlb(void)
712 if (tlb_type == spitfire) {
713 printk ("Contents of itlb: ");
714 for (slot = 0; slot < 14; slot++) printk (" ");
715 printk ("%2x:%016lx,%016lx\n",
717 spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
718 for (slot = 1; slot < 64; slot+=3) {
719 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
721 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
723 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
725 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
727 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
728 printk ("Contents of itlb0:\n");
729 for (slot = 0; slot < 16; slot+=2) {
730 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
732 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
734 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
736 printk ("Contents of itlb2:\n");
737 for (slot = 0; slot < 128; slot+=2) {
738 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
740 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
742 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
747 void sparc_ultra_dump_dtlb(void)
751 if (tlb_type == spitfire) {
752 printk ("Contents of dtlb: ");
753 for (slot = 0; slot < 14; slot++) printk (" ");
754 printk ("%2x:%016lx,%016lx\n", 0,
755 spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
756 for (slot = 1; slot < 64; slot+=3) {
757 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
759 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
761 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
763 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
765 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
766 printk ("Contents of dtlb0:\n");
767 for (slot = 0; slot < 16; slot+=2) {
768 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
770 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
772 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
774 printk ("Contents of dtlb2:\n");
775 for (slot = 0; slot < 512; slot+=2) {
776 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
778 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
780 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
782 if (tlb_type == cheetah_plus) {
783 printk ("Contents of dtlb3:\n");
784 for (slot = 0; slot < 512; slot+=2) {
785 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
787 cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
789 cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
795 extern unsigned long cmdline_memory_size;
797 unsigned long __init bootmem_init(unsigned long *pages_avail)
799 unsigned long bootmap_size, start_pfn, end_pfn;
800 unsigned long end_of_phys_memory = 0UL;
801 unsigned long bootmap_pfn, bytes_avail, size;
804 #ifdef CONFIG_DEBUG_BOOTMEM
805 prom_printf("bootmem_init: Scan pavail, ");
809 for (i = 0; i < pavail_ents; i++) {
810 end_of_phys_memory = pavail[i].phys_addr +
812 bytes_avail += pavail[i].reg_size;
813 if (cmdline_memory_size) {
814 if (bytes_avail > cmdline_memory_size) {
815 unsigned long slack = bytes_avail - cmdline_memory_size;
817 bytes_avail -= slack;
818 end_of_phys_memory -= slack;
820 pavail[i].reg_size -= slack;
821 if ((long)pavail[i].reg_size <= 0L) {
822 pavail[i].phys_addr = 0xdeadbeefUL;
823 pavail[i].reg_size = 0UL;
826 pavail[i+1].reg_size = 0Ul;
827 pavail[i+1].phys_addr = 0xdeadbeefUL;
835 *pages_avail = bytes_avail >> PAGE_SHIFT;
837 /* Start with page aligned address of last symbol in kernel
838 * image. The kernel is hard mapped below PAGE_OFFSET in a
839 * 4MB locked TLB translation.
841 start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT;
843 bootmap_pfn = start_pfn;
845 end_pfn = end_of_phys_memory >> PAGE_SHIFT;
847 #ifdef CONFIG_BLK_DEV_INITRD
848 /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
849 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
850 unsigned long ramdisk_image = sparc_ramdisk_image ?
851 sparc_ramdisk_image : sparc_ramdisk_image64;
852 if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
853 ramdisk_image -= KERNBASE;
854 initrd_start = ramdisk_image + phys_base;
855 initrd_end = initrd_start + sparc_ramdisk_size;
856 if (initrd_end > end_of_phys_memory) {
857 printk(KERN_CRIT "initrd extends beyond end of memory "
858 "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
859 initrd_end, end_of_phys_memory);
863 if (initrd_start >= (start_pfn << PAGE_SHIFT) &&
864 initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE)
865 bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT;
869 /* Initialize the boot-time allocator. */
870 max_pfn = max_low_pfn = end_pfn;
871 min_low_pfn = pfn_base;
873 #ifdef CONFIG_DEBUG_BOOTMEM
874 prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
875 min_low_pfn, bootmap_pfn, max_low_pfn);
877 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn);
879 /* Now register the available physical memory with the
882 for (i = 0; i < pavail_ents; i++) {
883 #ifdef CONFIG_DEBUG_BOOTMEM
884 prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
885 i, pavail[i].phys_addr, pavail[i].reg_size);
887 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
890 #ifdef CONFIG_BLK_DEV_INITRD
892 size = initrd_end - initrd_start;
894 /* Resert the initrd image area. */
895 #ifdef CONFIG_DEBUG_BOOTMEM
896 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
897 initrd_start, initrd_end);
899 reserve_bootmem(initrd_start, size);
900 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
902 initrd_start += PAGE_OFFSET;
903 initrd_end += PAGE_OFFSET;
906 /* Reserve the kernel text/data/bss. */
907 #ifdef CONFIG_DEBUG_BOOTMEM
908 prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
910 reserve_bootmem(kern_base, kern_size);
911 *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
913 /* Reserve the bootmem map. We do not account for it
914 * in pages_avail because we will release that memory
915 * in free_all_bootmem.
918 #ifdef CONFIG_DEBUG_BOOTMEM
919 prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
920 (bootmap_pfn << PAGE_SHIFT), size);
922 reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
923 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
928 #ifdef CONFIG_DEBUG_PAGEALLOC
929 static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
931 unsigned long vstart = PAGE_OFFSET + pstart;
932 unsigned long vend = PAGE_OFFSET + pend;
933 unsigned long alloc_bytes = 0UL;
935 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
936 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
941 while (vstart < vend) {
942 unsigned long this_end, paddr = __pa(vstart);
943 pgd_t *pgd = pgd_offset_k(vstart);
948 pud = pud_offset(pgd, vstart);
949 if (pud_none(*pud)) {
952 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
953 alloc_bytes += PAGE_SIZE;
954 pud_populate(&init_mm, pud, new);
957 pmd = pmd_offset(pud, vstart);
958 if (!pmd_present(*pmd)) {
961 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
962 alloc_bytes += PAGE_SIZE;
963 pmd_populate_kernel(&init_mm, pmd, new);
966 pte = pte_offset_kernel(pmd, vstart);
967 this_end = (vstart + PMD_SIZE) & PMD_MASK;
971 while (vstart < this_end) {
972 pte_val(*pte) = (paddr | pgprot_val(prot));
983 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
984 static int pall_ents __initdata;
986 extern unsigned int kvmap_linear_patch[1];
988 static void __init kernel_physical_mapping_init(void)
990 unsigned long i, mem_alloced = 0UL;
992 read_obp_memory("reg", &pall[0], &pall_ents);
994 for (i = 0; i < pall_ents; i++) {
995 unsigned long phys_start, phys_end;
997 phys_start = pall[i].phys_addr;
998 phys_end = phys_start + pall[i].reg_size;
999 mem_alloced += kernel_map_range(phys_start, phys_end,
1003 printk("Allocated %ld bytes for kernel page tables.\n",
1006 kvmap_linear_patch[0] = 0x01000000; /* nop */
1007 flushi(&kvmap_linear_patch[0]);
1012 void kernel_map_pages(struct page *page, int numpages, int enable)
1014 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1015 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1017 kernel_map_range(phys_start, phys_end,
1018 (enable ? PAGE_KERNEL : __pgprot(0)));
1020 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1021 PAGE_OFFSET + phys_end);
1023 /* we should perform an IPI and flush all tlbs,
1024 * but that can deadlock->flush only current cpu.
1026 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1027 PAGE_OFFSET + phys_end);
1031 unsigned long __init find_ecache_flush_span(unsigned long size)
1035 for (i = 0; i < pavail_ents; i++) {
1036 if (pavail[i].reg_size >= size)
1037 return pavail[i].phys_addr;
1043 static void __init tsb_phys_patch(void)
1045 struct tsb_ldquad_phys_patch_entry *pquad;
1046 struct tsb_phys_patch_entry *p;
1048 pquad = &__tsb_ldquad_phys_patch;
1049 while (pquad < &__tsb_ldquad_phys_patch_end) {
1050 unsigned long addr = pquad->addr;
1052 if (tlb_type == hypervisor)
1053 *(unsigned int *) addr = pquad->sun4v_insn;
1055 *(unsigned int *) addr = pquad->sun4u_insn;
1057 __asm__ __volatile__("flush %0"
1064 p = &__tsb_phys_patch;
1065 while (p < &__tsb_phys_patch_end) {
1066 unsigned long addr = p->addr;
1068 *(unsigned int *) addr = p->insn;
1070 __asm__ __volatile__("flush %0"
1078 /* Register this cpu's fault status area with the hypervisor. */
1079 void __cpuinit sun4v_register_fault_status(void)
1081 register unsigned long arg0 asm("%o0");
1082 register unsigned long arg1 asm("%o1");
1083 int cpu = hard_smp_processor_id();
1084 struct trap_per_cpu *tb = &trap_block[cpu];
1087 pa = kern_base + ((unsigned long) tb - KERNBASE);
1088 arg0 = HV_FAST_MMU_FAULT_AREA_CONF;
1090 __asm__ __volatile__("ta %4"
1091 : "=&r" (arg0), "=&r" (arg1)
1092 : "0" (arg0), "1" (arg1),
1093 "i" (HV_FAST_TRAP));
1096 /* paging_init() sets up the page tables */
1098 extern void cheetah_ecache_flush_init(void);
1099 extern void sun4v_patch_tlb_handlers(void);
1101 static unsigned long last_valid_pfn;
1102 pgd_t swapper_pg_dir[2048];
1104 void __init paging_init(void)
1106 unsigned long end_pfn, pages_avail, shift;
1107 unsigned long real_end, i;
1109 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1110 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1112 if (tlb_type == cheetah_plus ||
1113 tlb_type == hypervisor)
1116 if (tlb_type == hypervisor) {
1117 sun4v_patch_tlb_handlers();
1118 sun4v_register_fault_status();
1121 /* Find available physical memory... */
1122 read_obp_memory("available", &pavail[0], &pavail_ents);
1124 phys_base = 0xffffffffffffffffUL;
1125 for (i = 0; i < pavail_ents; i++)
1126 phys_base = min(phys_base, pavail[i].phys_addr);
1128 pfn_base = phys_base >> PAGE_SHIFT;
1130 set_bit(0, mmu_context_bmap);
1132 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1134 real_end = (unsigned long)_end;
1135 if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1137 if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1138 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1142 /* Set kernel pgd to upper alias so physical page computations
1145 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1147 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1149 /* Now can init the kernel/bad page tables. */
1150 pud_set(pud_offset(&swapper_pg_dir[0], 0),
1151 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1153 inherit_prom_mappings();
1155 /* Ok, we can use our TLB miss and window trap handlers safely. */
1160 /* Setup bootmem... */
1162 last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1164 #ifdef CONFIG_DEBUG_PAGEALLOC
1165 kernel_physical_mapping_init();
1169 unsigned long zones_size[MAX_NR_ZONES];
1170 unsigned long zholes_size[MAX_NR_ZONES];
1171 unsigned long npages;
1174 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1175 zones_size[znum] = zholes_size[znum] = 0;
1177 npages = end_pfn - pfn_base;
1178 zones_size[ZONE_DMA] = npages;
1179 zholes_size[ZONE_DMA] = npages - pages_avail;
1181 free_area_init_node(0, &contig_page_data, zones_size,
1182 phys_base >> PAGE_SHIFT, zholes_size);
1188 static void __init taint_real_pages(void)
1192 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1194 /* Find changes discovered in the physmem available rescan and
1195 * reserve the lost portions in the bootmem maps.
1197 for (i = 0; i < pavail_ents; i++) {
1198 unsigned long old_start, old_end;
1200 old_start = pavail[i].phys_addr;
1201 old_end = old_start +
1203 while (old_start < old_end) {
1206 for (n = 0; pavail_rescan_ents; n++) {
1207 unsigned long new_start, new_end;
1209 new_start = pavail_rescan[n].phys_addr;
1210 new_end = new_start +
1211 pavail_rescan[n].reg_size;
1213 if (new_start <= old_start &&
1214 new_end >= (old_start + PAGE_SIZE)) {
1215 set_bit(old_start >> 22,
1216 sparc64_valid_addr_bitmap);
1220 reserve_bootmem(old_start, PAGE_SIZE);
1223 old_start += PAGE_SIZE;
1228 void __init mem_init(void)
1230 unsigned long codepages, datapages, initpages;
1231 unsigned long addr, last;
1234 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1236 sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1237 if (sparc64_valid_addr_bitmap == NULL) {
1238 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1241 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1243 addr = PAGE_OFFSET + kern_base;
1244 last = PAGE_ALIGN(kern_size) + addr;
1245 while (addr < last) {
1246 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1252 max_mapnr = last_valid_pfn - pfn_base;
1253 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1255 #ifdef CONFIG_DEBUG_BOOTMEM
1256 prom_printf("mem_init: Calling free_all_bootmem().\n");
1258 totalram_pages = num_physpages = free_all_bootmem() - 1;
1261 * Set up the zero page, mark it reserved, so that page count
1262 * is not manipulated when freeing the page from user ptes.
1264 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1265 if (mem_map_zero == NULL) {
1266 prom_printf("paging_init: Cannot alloc zero page.\n");
1269 SetPageReserved(mem_map_zero);
1271 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1272 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1273 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1274 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1275 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1276 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1278 printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1279 nr_free_pages() << (PAGE_SHIFT-10),
1280 codepages << (PAGE_SHIFT-10),
1281 datapages << (PAGE_SHIFT-10),
1282 initpages << (PAGE_SHIFT-10),
1283 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1285 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1286 cheetah_ecache_flush_init();
1289 void free_initmem(void)
1291 unsigned long addr, initend;
1294 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1296 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1297 initend = (unsigned long)(__init_end) & PAGE_MASK;
1298 for (; addr < initend; addr += PAGE_SIZE) {
1303 ((unsigned long) __va(kern_base)) -
1304 ((unsigned long) KERNBASE));
1305 memset((void *)addr, 0xcc, PAGE_SIZE);
1306 p = virt_to_page(page);
1308 ClearPageReserved(p);
1309 set_page_count(p, 1);
1316 #ifdef CONFIG_BLK_DEV_INITRD
1317 void free_initrd_mem(unsigned long start, unsigned long end)
1320 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1321 for (; start < end; start += PAGE_SIZE) {
1322 struct page *p = virt_to_page(start);
1324 ClearPageReserved(p);
1325 set_page_count(p, 1);