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   1 /*  $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
   2  *  arch/sparc64/mm/init.c
   3  *
   4  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
   5  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   6  */
   7
   8 #include <linux/config.h>
   9 #include <linux/kernel.h>
  10 #include <linux/sched.h>
  11 #include <linux/string.h>
  12 #include <linux/init.h>
  13 #include <linux/bootmem.h>
  14 #include <linux/mm.h>
  15 #include <linux/hugetlb.h>
  16 #include <linux/slab.h>
  17 #include <linux/initrd.h>
  18 #include <linux/swap.h>
  19 #include <linux/pagemap.h>
  20 #include <linux/fs.h>
  21 #include <linux/seq_file.h>
  22 #include <linux/kprobes.h>
  23 #include <linux/cache.h>
  24 #include <linux/sort.h>
  25
  26 #include <asm/head.h>
  27 #include <asm/system.h>
  28 #include <asm/page.h>
  29 #include <asm/pgalloc.h>
  30 #include <asm/pgtable.h>
  31 #include <asm/oplib.h>
  32 #include <asm/iommu.h>
  33 #include <asm/io.h>
  34 #include <asm/uaccess.h>
  35 #include <asm/mmu_context.h>
  36 #include <asm/tlbflush.h>
  37 #include <asm/dma.h>
  38 #include <asm/starfire.h>
  39 #include <asm/tlb.h>
  40 #include <asm/spitfire.h>
  41 #include <asm/sections.h>
  42
  43 extern void device_scan(void);
  44
  45 #define MAX_BANKS       32
  46
  47 static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
  48 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
  49 static int pavail_ents __initdata;
  50 static int pavail_rescan_ents __initdata;
  51
  52 static int cmp_p64(const void *a, const void *b)
  53 {
  54         const struct linux_prom64_registers *x = a, *y = b;
  55
  56         if (x->phys_addr > y->phys_addr)
  57                 return 1;
  58         if (x->phys_addr < y->phys_addr)
  59                 return -1;
  60         return 0;
  61 }
  62
  63 static void __init read_obp_memory(const char *property,
  64                                    struct linux_prom64_registers *regs,
  65                                    int *num_ents)
  66 {
  67         int node = prom_finddevice("/memory");
  68         int prop_size = prom_getproplen(node, property);
  69         int ents, ret, i;
  70
  71         ents = prop_size / sizeof(struct linux_prom64_registers);
  72         if (ents > MAX_BANKS) {
  73                 prom_printf("The machine has more %s property entries than "
  74                             "this kernel can support (%d).\n",
  75                             property, MAX_BANKS);
  76                 prom_halt();
  77         }
  78
  79         ret = prom_getproperty(node, property, (char *) regs, prop_size);
  80         if (ret == -1) {
  81                 prom_printf("Couldn't get %s property from /memory.\n");
  82                 prom_halt();
  83         }
  84
  85         *num_ents = ents;
  86
  87         /* Sanitize what we got from the firmware, by page aligning
  88          * everything.
  89          */
  90         for (i = 0; i < ents; i++) {
  91                 unsigned long base, size;
  92
  93                 base = regs[i].phys_addr;
  94                 size = regs[i].reg_size;
  95
  96                 size &= PAGE_MASK;
  97                 if (base & ~PAGE_MASK) {
  98                         unsigned long new_base = PAGE_ALIGN(base);
  99
 100                         size -= new_base - base;
 101                         if ((long) size < 0L)
 102                                 size = 0UL;
 103                         base = new_base;
 104                 }
 105                 regs[i].phys_addr = base;
 106                 regs[i].reg_size = size;
 107         }
 108         sort(regs, ents, sizeof(struct linux_prom64_registers),
 109              cmp_p64, NULL);
 110 }
 111
 112 unsigned long *sparc64_valid_addr_bitmap __read_mostly;
 113
 114 /* Ugly, but necessary... -DaveM */
 115 unsigned long phys_base __read_mostly;
 116 unsigned long kern_base __read_mostly;
 117 unsigned long kern_size __read_mostly;
 118 unsigned long pfn_base __read_mostly;
 119
 120 /* get_new_mmu_context() uses "cache + 1".  */
 121 DEFINE_SPINLOCK(ctx_alloc_lock);
 122 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
 123 #define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
 124 unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
 125
 126 /* References to special section boundaries */
 127 extern char  _start[], _end[];
 128
 129 /* Initial ramdisk setup */
 130 extern unsigned long sparc_ramdisk_image64;
 131 extern unsigned int sparc_ramdisk_image;
 132 extern unsigned int sparc_ramdisk_size;
 133
 134 struct page *mem_map_zero __read_mostly;
 135
 136 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
 137
 138 unsigned long sparc64_kern_pri_context __read_mostly;
 139 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
 140 unsigned long sparc64_kern_sec_context __read_mostly;
 141
 142 int bigkernel = 0;
 143
 144 kmem_cache_t *pgtable_cache __read_mostly;
 145
 146 static void zero_ctor(void *addr, kmem_cache_t *cache, unsigned long flags)
 147 {
 148         clear_page(addr);
 149 }
 150
 151 void pgtable_cache_init(void)
 152 {
 153         pgtable_cache = kmem_cache_create("pgtable_cache",
 154                                           PAGE_SIZE, PAGE_SIZE,
 155                                           SLAB_HWCACHE_ALIGN |
 156                                           SLAB_MUST_HWCACHE_ALIGN,
 157                                           zero_ctor,
 158                                           NULL);
 159         if (!pgtable_cache) {
 160                 prom_printf("pgtable_cache_init(): Could not create!\n");
 161                 prom_halt();
 162         }
 163 }
 164
 165 #ifdef CONFIG_DEBUG_DCFLUSH
 166 atomic_t dcpage_flushes = ATOMIC_INIT(0);
 167 #ifdef CONFIG_SMP
 168 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
 169 #endif
 170 #endif
 171
 172 __inline__ void flush_dcache_page_impl(struct page *page)
 173 {
 174 #ifdef CONFIG_DEBUG_DCFLUSH
 175         atomic_inc(&dcpage_flushes);
 176 #endif
 177
 178 #ifdef DCACHE_ALIASING_POSSIBLE
 179         __flush_dcache_page(page_address(page),
 180                             ((tlb_type == spitfire) &&
 181                              page_mapping(page) != NULL));
 182 #else
 183         if (page_mapping(page) != NULL &&
 184             tlb_type == spitfire)
 185                 __flush_icache_page(__pa(page_address(page)));
 186 #endif
 187 }
 188
 189 #define PG_dcache_dirty         PG_arch_1
 190 #define PG_dcache_cpu_shift     24
 191 #define PG_dcache_cpu_mask      (256 - 1)
 192
 193 #if NR_CPUS > 256
 194 #error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
 195 #endif
 196
 197 #define dcache_dirty_cpu(page) \
 198         (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
 199
 200 static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
 201 {
 202         unsigned long mask = this_cpu;
 203         unsigned long non_cpu_bits;
 204
 205         non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
 206         mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
 207
 208         __asm__ __volatile__("1:\n\t"
 209                              "ldx       [%2], %%g7\n\t"
 210                              "and       %%g7, %1, %%g1\n\t"
 211                              "or        %%g1, %0, %%g1\n\t"
 212                              "casx      [%2], %%g7, %%g1\n\t"
 213                              "cmp       %%g7, %%g1\n\t"
 214                              "membar    #StoreLoad | #StoreStore\n\t"
 215                              "bne,pn    %%xcc, 1b\n\t"
 216                              " nop"
 217                              : /* no outputs */
 218                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
 219                              : "g1", "g7");
 220 }
 221
 222 static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
 223 {
 224         unsigned long mask = (1UL << PG_dcache_dirty);
 225
 226         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
 227                              "1:\n\t"
 228                              "ldx       [%2], %%g7\n\t"
 229                              "srlx      %%g7, %4, %%g1\n\t"
 230                              "and       %%g1, %3, %%g1\n\t"
 231                              "cmp       %%g1, %0\n\t"
 232                              "bne,pn    %%icc, 2f\n\t"
 233                              " andn     %%g7, %1, %%g1\n\t"
 234                              "casx      [%2], %%g7, %%g1\n\t"
 235                              "cmp       %%g7, %%g1\n\t"
 236                              "membar    #StoreLoad | #StoreStore\n\t"
 237                              "bne,pn    %%xcc, 1b\n\t"
 238                              " nop\n"
 239                              "2:"
 240                              : /* no outputs */
 241                              : "r" (cpu), "r" (mask), "r" (&page->flags),
 242                                "i" (PG_dcache_cpu_mask),
 243                                "i" (PG_dcache_cpu_shift)
 244                              : "g1", "g7");
 245 }
 246
 247 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
 248 {
 249         struct mm_struct *mm;
 250         struct page *page;
 251         unsigned long pfn;
 252         unsigned long pg_flags;
 253         unsigned long mm_rss;
 254
 255         pfn = pte_pfn(pte);
 256         if (pfn_valid(pfn) &&
 257             (page = pfn_to_page(pfn), page_mapping(page)) &&
 258             ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
 259                 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
 260                            PG_dcache_cpu_mask);
 261                 int this_cpu = get_cpu();
 262
 263                 /* This is just to optimize away some function calls
 264                  * in the SMP case.
 265                  */
 266                 if (cpu == this_cpu)
 267                         flush_dcache_page_impl(page);
 268                 else
 269                         smp_flush_dcache_page_impl(page, cpu);
 270
 271                 clear_dcache_dirty_cpu(page, cpu);
 272
 273                 put_cpu();
 274         }
 275
 276         mm = vma->vm_mm;
 277         mm_rss = get_mm_rss(mm);
 278         if (mm_rss >= mm->context.tsb_rss_limit)
 279                 tsb_grow(mm, mm_rss, GFP_ATOMIC);
 280
 281         if ((pte_val(pte) & _PAGE_ALL_SZ_BITS) == _PAGE_SZBITS) {
 282                 struct tsb *tsb;
 283                 unsigned long tag;
 284
 285                 tsb = &mm->context.tsb[(address >> PAGE_SHIFT) &
 286                                        (mm->context.tsb_nentries - 1UL)];
 287                 tag = (address >> 22UL) | CTX_HWBITS(mm->context) << 48UL;
 288                 tsb_insert(tsb, tag, pte_val(pte));
 289         }
 290 }
 291
 292 void flush_dcache_page(struct page *page)
 293 {
 294         struct address_space *mapping;
 295         int this_cpu;
 296
 297         /* Do not bother with the expensive D-cache flush if it
 298          * is merely the zero page.  The 'bigcore' testcase in GDB
 299          * causes this case to run millions of times.
 300          */
 301         if (page == ZERO_PAGE(0))
 302                 return;
 303
 304         this_cpu = get_cpu();
 305
 306         mapping = page_mapping(page);
 307         if (mapping && !mapping_mapped(mapping)) {
 308                 int dirty = test_bit(PG_dcache_dirty, &page->flags);
 309                 if (dirty) {
 310                         int dirty_cpu = dcache_dirty_cpu(page);
 311
 312                         if (dirty_cpu == this_cpu)
 313                                 goto out;
 314                         smp_flush_dcache_page_impl(page, dirty_cpu);
 315                 }
 316                 set_dcache_dirty(page, this_cpu);
 317         } else {
 318                 /* We could delay the flush for the !page_mapping
 319                  * case too.  But that case is for exec env/arg
 320                  * pages and those are %99 certainly going to get
 321                  * faulted into the tlb (and thus flushed) anyways.
 322                  */
 323                 flush_dcache_page_impl(page);
 324         }
 325
 326 out:
 327         put_cpu();
 328 }
 329
 330 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
 331 {
 332         /* Cheetah has coherent I-cache. */
 333         if (tlb_type == spitfire) {
 334                 unsigned long kaddr;
 335
 336                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
 337                         __flush_icache_page(__get_phys(kaddr));
 338         }
 339 }
 340
 341 unsigned long page_to_pfn(struct page *page)
 342 {
 343         return (unsigned long) ((page - mem_map) + pfn_base);
 344 }
 345
 346 struct page *pfn_to_page(unsigned long pfn)
 347 {
 348         return (mem_map + (pfn - pfn_base));
 349 }
 350
 351 void show_mem(void)
 352 {
 353         printk("Mem-info:\n");
 354         show_free_areas();
 355         printk("Free swap:       %6ldkB\n",
 356                nr_swap_pages << (PAGE_SHIFT-10));
 357         printk("%ld pages of RAM\n", num_physpages);
 358         printk("%d free pages\n", nr_free_pages());
 359 }
 360
 361 void mmu_info(struct seq_file *m)
 362 {
 363         if (tlb_type == cheetah)
 364                 seq_printf(m, "MMU Type\t: Cheetah\n");
 365         else if (tlb_type == cheetah_plus)
 366                 seq_printf(m, "MMU Type\t: Cheetah+\n");
 367         else if (tlb_type == spitfire)
 368                 seq_printf(m, "MMU Type\t: Spitfire\n");
 369         else
 370                 seq_printf(m, "MMU Type\t: ???\n");
 371
 372 #ifdef CONFIG_DEBUG_DCFLUSH
 373         seq_printf(m, "DCPageFlushes\t: %d\n",
 374                    atomic_read(&dcpage_flushes));
 375 #ifdef CONFIG_SMP
 376         seq_printf(m, "DCPageFlushesXC\t: %d\n",
 377                    atomic_read(&dcpage_flushes_xcall));
 378 #endif /* CONFIG_SMP */
 379 #endif /* CONFIG_DEBUG_DCFLUSH */
 380 }
 381
 382 struct linux_prom_translation {
 383         unsigned long virt;
 384         unsigned long size;
 385         unsigned long data;
 386 };
 387
 388 /* Exported for kernel TLB miss handling in ktlb.S */
 389 struct linux_prom_translation prom_trans[512] __read_mostly;
 390 unsigned int prom_trans_ents __read_mostly;
 391 unsigned int swapper_pgd_zero __read_mostly;
 392
 393 extern unsigned long prom_boot_page;
 394 extern void prom_remap(unsigned long physpage, unsigned long virtpage, int mmu_ihandle);
 395 extern int prom_get_mmu_ihandle(void);
 396 extern void register_prom_callbacks(void);
 397
 398 /* Exported for SMP bootup purposes. */
 399 unsigned long kern_locked_tte_data;
 400
 401 /*
 402  * Translate PROM's mapping we capture at boot time into physical address.
 403  * The second parameter is only set from prom_callback() invocations.
 404  */
 405 unsigned long prom_virt_to_phys(unsigned long promva, int *error)
 406 {
 407         int i;
 408
 409         for (i = 0; i < prom_trans_ents; i++) {
 410                 struct linux_prom_translation *p = &prom_trans[i];
 411
 412                 if (promva >= p->virt &&
 413                     promva < (p->virt + p->size)) {
 414                         unsigned long base = p->data & _PAGE_PADDR;
 415
 416                         if (error)
 417                                 *error = 0;
 418                         return base + (promva & (8192 - 1));
 419                 }
 420         }
 421         if (error)
 422                 *error = 1;
 423         return 0UL;
 424 }
 425
 426 /* The obp translations are saved based on 8k pagesize, since obp can
 427  * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
 428  * HI_OBP_ADDRESS range are handled in ktlb.S.
 429  */
 430 static inline int in_obp_range(unsigned long vaddr)
 431 {
 432         return (vaddr >= LOW_OBP_ADDRESS &&
 433                 vaddr < HI_OBP_ADDRESS);
 434 }
 435
 436 static int cmp_ptrans(const void *a, const void *b)
 437 {
 438         const struct linux_prom_translation *x = a, *y = b;
 439
 440         if (x->virt > y->virt)
 441                 return 1;
 442         if (x->virt < y->virt)
 443                 return -1;
 444         return 0;
 445 }
 446
 447 /* Read OBP translations property into 'prom_trans[]'.  */
 448 static void __init read_obp_translations(void)
 449 {
 450         int n, node, ents, first, last, i;
 451
 452         node = prom_finddevice("/virtual-memory");
 453         n = prom_getproplen(node, "translations");
 454         if (unlikely(n == 0 || n == -1)) {
 455                 prom_printf("prom_mappings: Couldn't get size.\n");
 456                 prom_halt();
 457         }
 458         if (unlikely(n > sizeof(prom_trans))) {
 459                 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
 460                 prom_halt();
 461         }
 462
 463         if ((n = prom_getproperty(node, "translations",
 464                                   (char *)&prom_trans[0],
 465                                   sizeof(prom_trans))) == -1) {
 466                 prom_printf("prom_mappings: Couldn't get property.\n");
 467                 prom_halt();
 468         }
 469
 470         n = n / sizeof(struct linux_prom_translation);
 471
 472         ents = n;
 473
 474         sort(prom_trans, ents, sizeof(struct linux_prom_translation),
 475              cmp_ptrans, NULL);
 476
 477         /* Now kick out all the non-OBP entries.  */
 478         for (i = 0; i < ents; i++) {
 479                 if (in_obp_range(prom_trans[i].virt))
 480                         break;
 481         }
 482         first = i;
 483         for (; i < ents; i++) {
 484                 if (!in_obp_range(prom_trans[i].virt))
 485                         break;
 486         }
 487         last = i;
 488
 489         for (i = 0; i < (last - first); i++) {
 490                 struct linux_prom_translation *src = &prom_trans[i + first];
 491                 struct linux_prom_translation *dest = &prom_trans[i];
 492
 493                 *dest = *src;
 494         }
 495         for (; i < ents; i++) {
 496                 struct linux_prom_translation *dest = &prom_trans[i];
 497                 dest->virt = dest->size = dest->data = 0x0UL;
 498         }
 499
 500         prom_trans_ents = last - first;
 501
 502         if (tlb_type == spitfire) {
 503                 /* Clear diag TTE bits. */
 504                 for (i = 0; i < prom_trans_ents; i++)
 505                         prom_trans[i].data &= ~0x0003fe0000000000UL;
 506         }
 507 }
 508
 509 static void __init remap_kernel(void)
 510 {
 511         unsigned long phys_page, tte_vaddr, tte_data;
 512         int tlb_ent = sparc64_highest_locked_tlbent();
 513
 514         tte_vaddr = (unsigned long) KERNBASE;
 515         phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
 516         tte_data = (phys_page | (_PAGE_VALID | _PAGE_SZ4MB |
 517                                  _PAGE_CP | _PAGE_CV | _PAGE_P |
 518                                  _PAGE_L | _PAGE_W));
 519
 520         kern_locked_tte_data = tte_data;
 521
 522         /* Now lock us into the TLBs via OBP. */
 523         prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
 524         prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
 525         if (bigkernel) {
 526                 tlb_ent -= 1;
 527                 prom_dtlb_load(tlb_ent,
 528                                tte_data + 0x400000,
 529                                tte_vaddr + 0x400000);
 530                 prom_itlb_load(tlb_ent,
 531                                tte_data + 0x400000,
 532                                tte_vaddr + 0x400000);
 533         }
 534         sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
 535         if (tlb_type == cheetah_plus) {
 536                 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
 537                                             CTX_CHEETAH_PLUS_NUC);
 538                 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
 539                 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
 540         }
 541 }
 542
 543
 544 static void __init inherit_prom_mappings(void)
 545 {
 546         read_obp_translations();
 547
 548         /* Now fixup OBP's idea about where we really are mapped. */
 549         prom_printf("Remapping the kernel... ");
 550         remap_kernel();
 551         prom_printf("done.\n");
 552
 553         prom_printf("Registering callbacks... ");
 554         register_prom_callbacks();
 555         prom_printf("done.\n");
 556 }
 557
 558 void prom_world(int enter)
 559 {
 560         if (!enter)
 561                 set_fs((mm_segment_t) { get_thread_current_ds() });
 562
 563         __asm__ __volatile__("flushw");
 564 }
 565
 566 #ifdef DCACHE_ALIASING_POSSIBLE
 567 void __flush_dcache_range(unsigned long start, unsigned long end)
 568 {
 569         unsigned long va;
 570
 571         if (tlb_type == spitfire) {
 572                 int n = 0;
 573
 574                 for (va = start; va < end; va += 32) {
 575                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
 576                         if (++n >= 512)
 577                                 break;
 578                 }
 579         } else {
 580                 start = __pa(start);
 581                 end = __pa(end);
 582                 for (va = start; va < end; va += 32)
 583                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 584                                              "membar #Sync"
 585                                              : /* no outputs */
 586                                              : "r" (va),
 587                                                "i" (ASI_DCACHE_INVALIDATE));
 588         }
 589 }
 590 #endif /* DCACHE_ALIASING_POSSIBLE */
 591
 592 /* If not locked, zap it. */
 593 void __flush_tlb_all(void)
 594 {
 595         unsigned long pstate;
 596         int i;
 597
 598         __asm__ __volatile__("flushw\n\t"
 599                              "rdpr      %%pstate, %0\n\t"
 600                              "wrpr      %0, %1, %%pstate"
 601                              : "=r" (pstate)
 602                              : "i" (PSTATE_IE));
 603         if (tlb_type == spitfire) {
 604                 for (i = 0; i < 64; i++) {
 605                         /* Spitfire Errata #32 workaround */
 606                         /* NOTE: Always runs on spitfire, so no
 607                          *       cheetah+ page size encodings.
 608                          */
 609                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 610                                              "flush     %%g6"
 611                                              : /* No outputs */
 612                                              : "r" (0),
 613                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 614
 615                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L)) {
 616                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 617                                                      "membar #Sync"
 618                                                      : /* no outputs */
 619                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 620                                 spitfire_put_dtlb_data(i, 0x0UL);
 621                         }
 622
 623                         /* Spitfire Errata #32 workaround */
 624                         /* NOTE: Always runs on spitfire, so no
 625                          *       cheetah+ page size encodings.
 626                          */
 627                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 628                                              "flush     %%g6"
 629                                              : /* No outputs */
 630                                              : "r" (0),
 631                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 632
 633                         if (!(spitfire_get_itlb_data(i) & _PAGE_L)) {
 634                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 635                                                      "membar #Sync"
 636                                                      : /* no outputs */
 637                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
 638                                 spitfire_put_itlb_data(i, 0x0UL);
 639                         }
 640                 }
 641         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 642                 cheetah_flush_dtlb_all();
 643                 cheetah_flush_itlb_all();
 644         }
 645         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
 646                              : : "r" (pstate));
 647 }
 648
 649 /* Caller does TLB context flushing on local CPU if necessary.
 650  * The caller also ensures that CTX_VALID(mm->context) is false.
 651  *
 652  * We must be careful about boundary cases so that we never
 653  * let the user have CTX 0 (nucleus) or we ever use a CTX
 654  * version of zero (and thus NO_CONTEXT would not be caught
 655  * by version mis-match tests in mmu_context.h).
 656  */
 657 void get_new_mmu_context(struct mm_struct *mm)
 658 {
 659         unsigned long ctx, new_ctx;
 660         unsigned long orig_pgsz_bits;
 661
 662
 663         spin_lock(&ctx_alloc_lock);
 664         orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
 665         ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
 666         new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
 667         if (new_ctx >= (1 << CTX_NR_BITS)) {
 668                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
 669                 if (new_ctx >= ctx) {
 670                         int i;
 671                         new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
 672                                 CTX_FIRST_VERSION;
 673                         if (new_ctx == 1)
 674                                 new_ctx = CTX_FIRST_VERSION;
 675
 676                         /* Don't call memset, for 16 entries that's just
 677                          * plain silly...
 678                          */
 679                         mmu_context_bmap[0] = 3;
 680                         mmu_context_bmap[1] = 0;
 681                         mmu_context_bmap[2] = 0;
 682                         mmu_context_bmap[3] = 0;
 683                         for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
 684                                 mmu_context_bmap[i + 0] = 0;
 685                                 mmu_context_bmap[i + 1] = 0;
 686                                 mmu_context_bmap[i + 2] = 0;
 687                                 mmu_context_bmap[i + 3] = 0;
 688                         }
 689                         goto out;
 690                 }
 691         }
 692         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
 693         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
 694 out:
 695         tlb_context_cache = new_ctx;
 696         mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
 697         spin_unlock(&ctx_alloc_lock);
 698 }
 699
 700 void sparc_ultra_dump_itlb(void)
 701 {
 702         int slot;
 703
 704         if (tlb_type == spitfire) {
 705                 printk ("Contents of itlb: ");
 706                 for (slot = 0; slot < 14; slot++) printk ("    ");
 707                 printk ("%2x:%016lx,%016lx\n",
 708                         0,
 709                         spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
 710                 for (slot = 1; slot < 64; slot+=3) {
 711                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 712                                 slot,
 713                                 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
 714                                 slot+1,
 715                                 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
 716                                 slot+2,
 717                                 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
 718                 }
 719         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 720                 printk ("Contents of itlb0:\n");
 721                 for (slot = 0; slot < 16; slot+=2) {
 722                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 723                                 slot,
 724                                 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
 725                                 slot+1,
 726                                 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
 727                 }
 728                 printk ("Contents of itlb2:\n");
 729                 for (slot = 0; slot < 128; slot+=2) {
 730                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 731                                 slot,
 732                                 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
 733                                 slot+1,
 734                                 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
 735                 }
 736         }
 737 }
 738
 739 void sparc_ultra_dump_dtlb(void)
 740 {
 741         int slot;
 742
 743         if (tlb_type == spitfire) {
 744                 printk ("Contents of dtlb: ");
 745                 for (slot = 0; slot < 14; slot++) printk ("    ");
 746                 printk ("%2x:%016lx,%016lx\n", 0,
 747                         spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
 748                 for (slot = 1; slot < 64; slot+=3) {
 749                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 750                                 slot,
 751                                 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
 752                                 slot+1,
 753                                 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
 754                                 slot+2,
 755                                 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
 756                 }
 757         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 758                 printk ("Contents of dtlb0:\n");
 759                 for (slot = 0; slot < 16; slot+=2) {
 760                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 761                                 slot,
 762                                 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
 763                                 slot+1,
 764                                 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
 765                 }
 766                 printk ("Contents of dtlb2:\n");
 767                 for (slot = 0; slot < 512; slot+=2) {
 768                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 769                                 slot,
 770                                 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
 771                                 slot+1,
 772                                 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
 773                 }
 774                 if (tlb_type == cheetah_plus) {
 775                         printk ("Contents of dtlb3:\n");
 776                         for (slot = 0; slot < 512; slot+=2) {
 777                                 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
 778                                         slot,
 779                                         cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
 780                                         slot+1,
 781                                         cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
 782                         }
 783                 }
 784         }
 785 }
 786
 787 static inline void spitfire_errata32(void)
 788 {
 789         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 790                              "flush     %%g6"
 791                              : /* No outputs */
 792                              : "r" (0),
 793                                "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 794 }
 795
 796 extern unsigned long cmdline_memory_size;
 797
 798 unsigned long __init bootmem_init(unsigned long *pages_avail)
 799 {
 800         unsigned long bootmap_size, start_pfn, end_pfn;
 801         unsigned long end_of_phys_memory = 0UL;
 802         unsigned long bootmap_pfn, bytes_avail, size;
 803         int i;
 804
 805 #ifdef CONFIG_DEBUG_BOOTMEM
 806         prom_printf("bootmem_init: Scan pavail, ");
 807 #endif
 808
 809         bytes_avail = 0UL;
 810         for (i = 0; i < pavail_ents; i++) {
 811                 end_of_phys_memory = pavail[i].phys_addr +
 812                         pavail[i].reg_size;
 813                 bytes_avail += pavail[i].reg_size;
 814                 if (cmdline_memory_size) {
 815                         if (bytes_avail > cmdline_memory_size) {
 816                                 unsigned long slack = bytes_avail - cmdline_memory_size;
 817
 818                                 bytes_avail -= slack;
 819                                 end_of_phys_memory -= slack;
 820
 821                                 pavail[i].reg_size -= slack;
 822                                 if ((long)pavail[i].reg_size <= 0L) {
 823                                         pavail[i].phys_addr = 0xdeadbeefUL;
 824                                         pavail[i].reg_size = 0UL;
 825                                         pavail_ents = i;
 826                                 } else {
 827                                         pavail[i+1].reg_size = 0Ul;
 828                                         pavail[i+1].phys_addr = 0xdeadbeefUL;
 829                                         pavail_ents = i + 1;
 830                                 }
 831                                 break;
 832                         }
 833                 }
 834         }
 835
 836         *pages_avail = bytes_avail >> PAGE_SHIFT;
 837
 838         /* Start with page aligned address of last symbol in kernel
 839          * image.  The kernel is hard mapped below PAGE_OFFSET in a
 840          * 4MB locked TLB translation.
 841          */
 842         start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT;
 843
 844         bootmap_pfn = start_pfn;
 845
 846         end_pfn = end_of_phys_memory >> PAGE_SHIFT;
 847
 848 #ifdef CONFIG_BLK_DEV_INITRD
 849         /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
 850         if (sparc_ramdisk_image || sparc_ramdisk_image64) {
 851                 unsigned long ramdisk_image = sparc_ramdisk_image ?
 852                         sparc_ramdisk_image : sparc_ramdisk_image64;
 853                 if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
 854                         ramdisk_image -= KERNBASE;
 855                 initrd_start = ramdisk_image + phys_base;
 856                 initrd_end = initrd_start + sparc_ramdisk_size;
 857                 if (initrd_end > end_of_phys_memory) {
 858                         printk(KERN_CRIT "initrd extends beyond end of memory "
 859                                          "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
 860                                initrd_end, end_of_phys_memory);
 861                         initrd_start = 0;
 862                 }
 863                 if (initrd_start) {
 864                         if (initrd_start >= (start_pfn << PAGE_SHIFT) &&
 865                             initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE)
 866                                 bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT;
 867                 }
 868         }
 869 #endif
 870         /* Initialize the boot-time allocator. */
 871         max_pfn = max_low_pfn = end_pfn;
 872         min_low_pfn = pfn_base;
 873
 874 #ifdef CONFIG_DEBUG_BOOTMEM
 875         prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
 876                     min_low_pfn, bootmap_pfn, max_low_pfn);
 877 #endif
 878         bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn);
 879
 880         /* Now register the available physical memory with the
 881          * allocator.
 882          */
 883         for (i = 0; i < pavail_ents; i++) {
 884 #ifdef CONFIG_DEBUG_BOOTMEM
 885                 prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
 886                             i, pavail[i].phys_addr, pavail[i].reg_size);
 887 #endif
 888                 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
 889         }
 890
 891 #ifdef CONFIG_BLK_DEV_INITRD
 892         if (initrd_start) {
 893                 size = initrd_end - initrd_start;
 894
 895                 /* Resert the initrd image area. */
 896 #ifdef CONFIG_DEBUG_BOOTMEM
 897                 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
 898                         initrd_start, initrd_end);
 899 #endif
 900                 reserve_bootmem(initrd_start, size);
 901                 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
 902
 903                 initrd_start += PAGE_OFFSET;
 904                 initrd_end += PAGE_OFFSET;
 905         }
 906 #endif
 907         /* Reserve the kernel text/data/bss. */
 908 #ifdef CONFIG_DEBUG_BOOTMEM
 909         prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
 910 #endif
 911         reserve_bootmem(kern_base, kern_size);
 912         *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
 913
 914         /* Reserve the bootmem map.   We do not account for it
 915          * in pages_avail because we will release that memory
 916          * in free_all_bootmem.
 917          */
 918         size = bootmap_size;
 919 #ifdef CONFIG_DEBUG_BOOTMEM
 920         prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
 921                     (bootmap_pfn << PAGE_SHIFT), size);
 922 #endif
 923         reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
 924         *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
 925
 926         return end_pfn;
 927 }
 928
 929 #ifdef CONFIG_DEBUG_PAGEALLOC
 930 static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
 931 {
 932         unsigned long vstart = PAGE_OFFSET + pstart;
 933         unsigned long vend = PAGE_OFFSET + pend;
 934         unsigned long alloc_bytes = 0UL;
 935
 936         if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
 937                 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
 938                             vstart, vend);
 939                 prom_halt();
 940         }
 941
 942         while (vstart < vend) {
 943                 unsigned long this_end, paddr = __pa(vstart);
 944                 pgd_t *pgd = pgd_offset_k(vstart);
 945                 pud_t *pud;
 946                 pmd_t *pmd;
 947                 pte_t *pte;
 948
 949                 pud = pud_offset(pgd, vstart);
 950                 if (pud_none(*pud)) {
 951                         pmd_t *new;
 952
 953                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
 954                         alloc_bytes += PAGE_SIZE;
 955                         pud_populate(&init_mm, pud, new);
 956                 }
 957
 958                 pmd = pmd_offset(pud, vstart);
 959                 if (!pmd_present(*pmd)) {
 960                         pte_t *new;
 961
 962                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
 963                         alloc_bytes += PAGE_SIZE;
 964                         pmd_populate_kernel(&init_mm, pmd, new);
 965                 }
 966
 967                 pte = pte_offset_kernel(pmd, vstart);
 968                 this_end = (vstart + PMD_SIZE) & PMD_MASK;
 969                 if (this_end > vend)
 970                         this_end = vend;
 971
 972                 while (vstart < this_end) {
 973                         pte_val(*pte) = (paddr | pgprot_val(prot));
 974
 975                         vstart += PAGE_SIZE;
 976                         paddr += PAGE_SIZE;
 977                         pte++;
 978                 }
 979         }
 980
 981         return alloc_bytes;
 982 }
 983
 984 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
 985 static int pall_ents __initdata;
 986
 987 extern unsigned int kvmap_linear_patch[1];
 988
 989 static void __init kernel_physical_mapping_init(void)
 990 {
 991         unsigned long i, mem_alloced = 0UL;
 992
 993         read_obp_memory("reg", &pall[0], &pall_ents);
 994
 995         for (i = 0; i < pall_ents; i++) {
 996                 unsigned long phys_start, phys_end;
 997
 998                 phys_start = pall[i].phys_addr;
 999                 phys_end = phys_start + pall[i].reg_size;
1000                 mem_alloced += kernel_map_range(phys_start, phys_end,
1001                                                 PAGE_KERNEL);
1002         }
1003
1004         printk("Allocated %ld bytes for kernel page tables.\n",
1005                mem_alloced);
1006
1007         kvmap_linear_patch[0] = 0x01000000; /* nop */
1008         flushi(&kvmap_linear_patch[0]);
1009
1010         __flush_tlb_all();
1011 }
1012
1013 void kernel_map_pages(struct page *page, int numpages, int enable)
1014 {
1015         unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1016         unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1017
1018         kernel_map_range(phys_start, phys_end,
1019                          (enable ? PAGE_KERNEL : __pgprot(0)));
1020
1021         flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1022                                PAGE_OFFSET + phys_end);
1023
1024         /* we should perform an IPI and flush all tlbs,
1025          * but that can deadlock->flush only current cpu.
1026          */
1027         __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1028                                  PAGE_OFFSET + phys_end);
1029 }
1030 #endif
1031
1032 unsigned long __init find_ecache_flush_span(unsigned long size)
1033 {
1034         int i;
1035
1036         for (i = 0; i < pavail_ents; i++) {
1037                 if (pavail[i].reg_size >= size)
1038                         return pavail[i].phys_addr;
1039         }
1040
1041         return ~0UL;
1042 }
1043
1044 /* paging_init() sets up the page tables */
1045
1046 extern void cheetah_ecache_flush_init(void);
1047
1048 static unsigned long last_valid_pfn;
1049 pgd_t swapper_pg_dir[2048];
1050
1051 void __init paging_init(void)
1052 {
1053         unsigned long end_pfn, pages_avail, shift;
1054         unsigned long real_end, i;
1055
1056         /* Find available physical memory... */
1057         read_obp_memory("available", &pavail[0], &pavail_ents);
1058
1059         phys_base = 0xffffffffffffffffUL;
1060         for (i = 0; i < pavail_ents; i++)
1061                 phys_base = min(phys_base, pavail[i].phys_addr);
1062
1063         pfn_base = phys_base >> PAGE_SHIFT;
1064
1065         kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1066         kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1067
1068         set_bit(0, mmu_context_bmap);
1069
1070         shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1071
1072         real_end = (unsigned long)_end;
1073         if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1074                 bigkernel = 1;
1075         if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1076                 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1077                 prom_halt();
1078         }
1079
1080         /* Set kernel pgd to upper alias so physical page computations
1081          * work.
1082          */
1083         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1084
1085         memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1086
1087         /* Now can init the kernel/bad page tables. */
1088         pud_set(pud_offset(&swapper_pg_dir[0], 0),
1089                 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1090
1091         swapper_pgd_zero = pgd_val(swapper_pg_dir[0]);
1092
1093         inherit_prom_mappings();
1094
1095         /* Ok, we can use our TLB miss and window trap handlers safely.
1096          * We need to do a quick peek here to see if we are on StarFire
1097          * or not, so setup_tba can setup the IRQ globals correctly (it
1098          * needs to get the hard smp processor id correctly).
1099          */
1100         {
1101                 extern void setup_tba(int);
1102                 setup_tba(this_is_starfire);
1103         }
1104
1105         __flush_tlb_all();
1106
1107         /* Setup bootmem... */
1108         pages_avail = 0;
1109         last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1110
1111 #ifdef CONFIG_DEBUG_PAGEALLOC
1112         kernel_physical_mapping_init();
1113 #endif
1114
1115         {
1116                 unsigned long zones_size[MAX_NR_ZONES];
1117                 unsigned long zholes_size[MAX_NR_ZONES];
1118                 unsigned long npages;
1119                 int znum;
1120
1121                 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1122                         zones_size[znum] = zholes_size[znum] = 0;
1123
1124                 npages = end_pfn - pfn_base;
1125                 zones_size[ZONE_DMA] = npages;
1126                 zholes_size[ZONE_DMA] = npages - pages_avail;
1127
1128                 free_area_init_node(0, &contig_page_data, zones_size,
1129                                     phys_base >> PAGE_SHIFT, zholes_size);
1130         }
1131
1132         device_scan();
1133 }
1134
1135 static void __init taint_real_pages(void)
1136 {
1137         int i;
1138
1139         read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1140
1141         /* Find changes discovered in the physmem available rescan and
1142          * reserve the lost portions in the bootmem maps.
1143          */
1144         for (i = 0; i < pavail_ents; i++) {
1145                 unsigned long old_start, old_end;
1146
1147                 old_start = pavail[i].phys_addr;
1148                 old_end = old_start +
1149                         pavail[i].reg_size;
1150                 while (old_start < old_end) {
1151                         int n;
1152
1153                         for (n = 0; pavail_rescan_ents; n++) {
1154                                 unsigned long new_start, new_end;
1155
1156                                 new_start = pavail_rescan[n].phys_addr;
1157                                 new_end = new_start +
1158                                         pavail_rescan[n].reg_size;
1159
1160                                 if (new_start <= old_start &&
1161                                     new_end >= (old_start + PAGE_SIZE)) {
1162                                         set_bit(old_start >> 22,
1163                                                 sparc64_valid_addr_bitmap);
1164                                         goto do_next_page;
1165                                 }
1166                         }
1167                         reserve_bootmem(old_start, PAGE_SIZE);
1168
1169                 do_next_page:
1170                         old_start += PAGE_SIZE;
1171                 }
1172         }
1173 }
1174
1175 void __init mem_init(void)
1176 {
1177         unsigned long codepages, datapages, initpages;
1178         unsigned long addr, last;
1179         int i;
1180
1181         i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1182         i += 1;
1183         sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1184         if (sparc64_valid_addr_bitmap == NULL) {
1185                 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1186                 prom_halt();
1187         }
1188         memset(sparc64_valid_addr_bitmap, 0, i << 3);
1189
1190         addr = PAGE_OFFSET + kern_base;
1191         last = PAGE_ALIGN(kern_size) + addr;
1192         while (addr < last) {
1193                 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1194                 addr += PAGE_SIZE;
1195         }
1196
1197         taint_real_pages();
1198
1199         max_mapnr = last_valid_pfn - pfn_base;
1200         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1201
1202 #ifdef CONFIG_DEBUG_BOOTMEM
1203         prom_printf("mem_init: Calling free_all_bootmem().\n");
1204 #endif
1205         totalram_pages = num_physpages = free_all_bootmem() - 1;
1206
1207         /*
1208          * Set up the zero page, mark it reserved, so that page count
1209          * is not manipulated when freeing the page from user ptes.
1210          */
1211         mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1212         if (mem_map_zero == NULL) {
1213                 prom_printf("paging_init: Cannot alloc zero page.\n");
1214                 prom_halt();
1215         }
1216         SetPageReserved(mem_map_zero);
1217
1218         codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1219         codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1220         datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1221         datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1222         initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1223         initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1224
1225         printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1226                nr_free_pages() << (PAGE_SHIFT-10),
1227                codepages << (PAGE_SHIFT-10),
1228                datapages << (PAGE_SHIFT-10),
1229                initpages << (PAGE_SHIFT-10),
1230                PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1231
1232         if (tlb_type == cheetah || tlb_type == cheetah_plus)
1233                 cheetah_ecache_flush_init();
1234 }
1235
1236 void free_initmem(void)
1237 {
1238         unsigned long addr, initend;
1239
1240         /*
1241          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1242          */
1243         addr = PAGE_ALIGN((unsigned long)(__init_begin));
1244         initend = (unsigned long)(__init_end) & PAGE_MASK;
1245         for (; addr < initend; addr += PAGE_SIZE) {
1246                 unsigned long page;
1247                 struct page *p;
1248
1249                 page = (addr +
1250                         ((unsigned long) __va(kern_base)) -
1251                         ((unsigned long) KERNBASE));
1252                 memset((void *)addr, 0xcc, PAGE_SIZE);
1253                 p = virt_to_page(page);
1254
1255                 ClearPageReserved(p);
1256                 set_page_count(p, 1);
1257                 __free_page(p);
1258                 num_physpages++;
1259                 totalram_pages++;
1260         }
1261 }
1262
1263 #ifdef CONFIG_BLK_DEV_INITRD
1264 void free_initrd_mem(unsigned long start, unsigned long end)
1265 {
1266         if (start < end)
1267                 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1268         for (; start < end; start += PAGE_SIZE) {
1269                 struct page *p = virt_to_page(start);
1270
1271                 ClearPageReserved(p);
1272                 set_page_count(p, 1);
1273                 __free_page(p);
1274                 num_physpages++;
1275                 totalram_pages++;
1276         }
1277 }
1278 #endif