1 /* pci.c: UltraSparc PCI controller support.
3 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
7 * OF tree based PCI bus probing taken from the PowerPC port
8 * with minor modifications, see there for credits.
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/string.h>
14 #include <linux/sched.h>
15 #include <linux/capability.h>
16 #include <linux/errno.h>
17 #include <linux/smp_lock.h>
18 #include <linux/msi.h>
19 #include <linux/irq.h>
20 #include <linux/init.h>
22 #include <asm/uaccess.h>
24 #include <asm/pgtable.h>
33 unsigned long pci_memspace_mask = 0xffffffffUL;
36 /* A "nop" PCI implementation. */
37 asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn,
38 unsigned long off, unsigned long len,
43 asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn,
44 unsigned long off, unsigned long len,
51 /* List of all PCI controllers found in the system. */
52 struct pci_controller_info *pci_controller_root = NULL;
54 /* Each PCI controller found gets a unique index. */
55 int pci_num_controllers = 0;
57 volatile int pci_poke_in_progress;
58 volatile int pci_poke_cpu = -1;
59 volatile int pci_poke_faulted;
61 static DEFINE_SPINLOCK(pci_poke_lock);
63 void pci_config_read8(u8 *addr, u8 *ret)
68 spin_lock_irqsave(&pci_poke_lock, flags);
69 pci_poke_cpu = smp_processor_id();
70 pci_poke_in_progress = 1;
72 __asm__ __volatile__("membar #Sync\n\t"
73 "lduba [%1] %2, %0\n\t"
76 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
78 pci_poke_in_progress = 0;
80 if (!pci_poke_faulted)
82 spin_unlock_irqrestore(&pci_poke_lock, flags);
85 void pci_config_read16(u16 *addr, u16 *ret)
90 spin_lock_irqsave(&pci_poke_lock, flags);
91 pci_poke_cpu = smp_processor_id();
92 pci_poke_in_progress = 1;
94 __asm__ __volatile__("membar #Sync\n\t"
95 "lduha [%1] %2, %0\n\t"
98 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
100 pci_poke_in_progress = 0;
102 if (!pci_poke_faulted)
104 spin_unlock_irqrestore(&pci_poke_lock, flags);
107 void pci_config_read32(u32 *addr, u32 *ret)
112 spin_lock_irqsave(&pci_poke_lock, flags);
113 pci_poke_cpu = smp_processor_id();
114 pci_poke_in_progress = 1;
115 pci_poke_faulted = 0;
116 __asm__ __volatile__("membar #Sync\n\t"
117 "lduwa [%1] %2, %0\n\t"
120 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
122 pci_poke_in_progress = 0;
124 if (!pci_poke_faulted)
126 spin_unlock_irqrestore(&pci_poke_lock, flags);
129 void pci_config_write8(u8 *addr, u8 val)
133 spin_lock_irqsave(&pci_poke_lock, flags);
134 pci_poke_cpu = smp_processor_id();
135 pci_poke_in_progress = 1;
136 pci_poke_faulted = 0;
137 __asm__ __volatile__("membar #Sync\n\t"
138 "stba %0, [%1] %2\n\t"
141 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
143 pci_poke_in_progress = 0;
145 spin_unlock_irqrestore(&pci_poke_lock, flags);
148 void pci_config_write16(u16 *addr, u16 val)
152 spin_lock_irqsave(&pci_poke_lock, flags);
153 pci_poke_cpu = smp_processor_id();
154 pci_poke_in_progress = 1;
155 pci_poke_faulted = 0;
156 __asm__ __volatile__("membar #Sync\n\t"
157 "stha %0, [%1] %2\n\t"
160 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
162 pci_poke_in_progress = 0;
164 spin_unlock_irqrestore(&pci_poke_lock, flags);
167 void pci_config_write32(u32 *addr, u32 val)
171 spin_lock_irqsave(&pci_poke_lock, flags);
172 pci_poke_cpu = smp_processor_id();
173 pci_poke_in_progress = 1;
174 pci_poke_faulted = 0;
175 __asm__ __volatile__("membar #Sync\n\t"
176 "stwa %0, [%1] %2\n\t"
179 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
181 pci_poke_in_progress = 0;
183 spin_unlock_irqrestore(&pci_poke_lock, flags);
186 /* Probe for all PCI controllers in the system. */
187 extern void sabre_init(struct device_node *, const char *);
188 extern void psycho_init(struct device_node *, const char *);
189 extern void schizo_init(struct device_node *, const char *);
190 extern void schizo_plus_init(struct device_node *, const char *);
191 extern void tomatillo_init(struct device_node *, const char *);
192 extern void sun4v_pci_init(struct device_node *, const char *);
196 void (*init)(struct device_node *, const char *);
197 } pci_controller_table[] __initdata = {
198 { "SUNW,sabre", sabre_init },
199 { "pci108e,a000", sabre_init },
200 { "pci108e,a001", sabre_init },
201 { "SUNW,psycho", psycho_init },
202 { "pci108e,8000", psycho_init },
203 { "SUNW,schizo", schizo_init },
204 { "pci108e,8001", schizo_init },
205 { "SUNW,schizo+", schizo_plus_init },
206 { "pci108e,8002", schizo_plus_init },
207 { "SUNW,tomatillo", tomatillo_init },
208 { "pci108e,a801", tomatillo_init },
209 { "SUNW,sun4v-pci", sun4v_pci_init },
211 #define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \
212 sizeof(pci_controller_table[0]))
214 static int __init pci_controller_init(const char *model_name, int namelen, struct device_node *dp)
218 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
219 if (!strncmp(model_name,
220 pci_controller_table[i].model_name,
222 pci_controller_table[i].init(dp, model_name);
230 static int __init pci_is_controller(const char *model_name, int namelen, struct device_node *dp)
234 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
235 if (!strncmp(model_name,
236 pci_controller_table[i].model_name,
244 static int __init pci_controller_scan(int (*handler)(const char *, int, struct device_node *))
246 struct device_node *dp;
249 for_each_node_by_name(dp, "pci") {
250 struct property *prop;
253 prop = of_find_property(dp, "model", &len);
255 prop = of_find_property(dp, "compatible", &len);
258 const char *model = prop->value;
261 /* Our value may be a multi-valued string in the
262 * case of some compatible properties. For sanity,
263 * only try the first one.
265 while (model[item_len] && len) {
270 if (handler(model, item_len, dp))
279 /* Is there some PCI controller in the system? */
280 int __init pcic_present(void)
282 return pci_controller_scan(pci_is_controller);
285 const struct pci_iommu_ops *pci_iommu_ops;
286 EXPORT_SYMBOL(pci_iommu_ops);
288 extern const struct pci_iommu_ops pci_sun4u_iommu_ops,
291 /* Find each controller in the system, attach and initialize
292 * software state structure for each and link into the
293 * pci_controller_root. Setup the controller enough such
294 * that bus scanning can be done.
296 static void __init pci_controller_probe(void)
298 if (tlb_type == hypervisor)
299 pci_iommu_ops = &pci_sun4v_iommu_ops;
301 pci_iommu_ops = &pci_sun4u_iommu_ops;
303 printk("PCI: Probing for controllers.\n");
305 pci_controller_scan(pci_controller_init);
308 static unsigned long pci_parse_of_flags(u32 addr0)
310 unsigned long flags = 0;
312 if (addr0 & 0x02000000) {
313 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
314 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
315 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
316 if (addr0 & 0x40000000)
317 flags |= IORESOURCE_PREFETCH
318 | PCI_BASE_ADDRESS_MEM_PREFETCH;
319 } else if (addr0 & 0x01000000)
320 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
324 /* The of_device layer has translated all of the assigned-address properties
325 * into physical address resources, we only have to figure out the register
328 static void pci_parse_of_addrs(struct of_device *op,
329 struct device_node *node,
332 struct resource *op_res;
336 addrs = of_get_property(node, "assigned-addresses", &proplen);
339 printk(" parse addresses (%d bytes) @ %p\n", proplen, addrs);
340 op_res = &op->resource[0];
341 for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
342 struct resource *res;
346 flags = pci_parse_of_flags(addrs[0]);
350 printk(" start: %lx, end: %lx, i: %x\n",
351 op_res->start, op_res->end, i);
353 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
354 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
355 } else if (i == dev->rom_base_reg) {
356 res = &dev->resource[PCI_ROM_RESOURCE];
357 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
359 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
362 res->start = op_res->start;
363 res->end = op_res->end;
365 res->name = pci_name(dev);
369 struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
370 struct device_node *node,
371 struct pci_bus *bus, int devfn,
374 struct dev_archdata *sd;
379 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
383 sd = &dev->dev.archdata;
384 sd->iommu = pbm->iommu;
386 sd->host_controller = pbm;
387 sd->prom_node = node;
388 sd->op = of_find_device_by_node(node);
389 sd->msi_num = 0xffffffff;
391 type = of_get_property(node, "device_type", NULL);
395 printk(" create device, devfn: %x, type: %s\n", devfn, type);
399 dev->dev.parent = bus->bridge;
400 dev->dev.bus = &pci_bus_type;
402 dev->multifunction = 0; /* maybe a lie? */
404 if (host_controller) {
405 dev->vendor = 0x108e;
406 dev->device = 0x8000;
407 dev->subsystem_vendor = 0x0000;
408 dev->subsystem_device = 0x0000;
411 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
412 dev->device = of_getintprop_default(node, "device-id", 0xffff);
413 dev->subsystem_vendor =
414 of_getintprop_default(node, "subsystem-vendor-id", 0);
415 dev->subsystem_device =
416 of_getintprop_default(node, "subsystem-id", 0);
418 dev->cfg_size = pci_cfg_space_size(dev);
420 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
421 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
423 if (host_controller) {
424 dev->class = PCI_CLASS_BRIDGE_HOST << 8;
426 /* We can't actually use the firmware value, we have
427 * to read what is in the register right now. One
428 * reason is that in the case of IDE interfaces the
429 * firmware can sample the value before the the IDE
430 * interface is programmed into native mode.
432 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
433 dev->class = class >> 8;
435 printk(" class: 0x%x\n", dev->class);
437 dev->current_state = 4; /* unknown power state */
438 dev->error_state = pci_channel_io_normal;
440 if (host_controller) {
441 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
442 dev->rom_base_reg = PCI_ROM_ADDRESS1;
443 dev->irq = PCI_IRQ_NONE;
445 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
446 /* a PCI-PCI bridge */
447 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
448 dev->rom_base_reg = PCI_ROM_ADDRESS1;
449 } else if (!strcmp(type, "cardbus")) {
450 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
452 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
453 dev->rom_base_reg = PCI_ROM_ADDRESS;
455 dev->irq = sd->op->irqs[0];
456 if (dev->irq == 0xffffffff)
457 dev->irq = PCI_IRQ_NONE;
460 pci_parse_of_addrs(sd->op, node, dev);
462 printk(" adding to system ...\n");
464 pci_device_add(dev, bus);
469 static void __init apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
471 u32 idx, first, last;
475 for (idx = 0; idx < 8; idx++) {
476 if ((map & (1 << idx)) != 0) {
488 static void __init pci_resource_adjust(struct resource *res,
489 struct resource *root)
491 res->start += root->start;
492 res->end += root->start;
495 /* Cook up fake bus resources for SUNW,simba PCI bridges which lack
496 * a proper 'ranges' property.
498 static void __init apb_fake_ranges(struct pci_dev *dev,
500 struct pci_pbm_info *pbm)
502 struct resource *res;
506 pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
507 apb_calc_first_last(map, &first, &last);
508 res = bus->resource[0];
509 res->start = (first << 21);
510 res->end = (last << 21) + ((1 << 21) - 1);
511 res->flags = IORESOURCE_IO;
512 pci_resource_adjust(res, &pbm->io_space);
514 pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
515 apb_calc_first_last(map, &first, &last);
516 res = bus->resource[1];
517 res->start = (first << 21);
518 res->end = (last << 21) + ((1 << 21) - 1);
519 res->flags = IORESOURCE_MEM;
520 pci_resource_adjust(res, &pbm->mem_space);
523 static void __init pci_of_scan_bus(struct pci_pbm_info *pbm,
524 struct device_node *node,
525 struct pci_bus *bus);
527 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
529 void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
530 struct device_node *node,
534 const u32 *busrange, *ranges;
536 struct resource *res;
540 printk("of_scan_pci_bridge(%s)\n", node->full_name);
542 /* parse bus-range property */
543 busrange = of_get_property(node, "bus-range", &len);
544 if (busrange == NULL || len != 8) {
545 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
549 ranges = of_get_property(node, "ranges", &len);
551 if (ranges == NULL) {
552 char *model = of_get_property(node, "model", NULL);
553 if (model && !strcmp(model, "SUNW,simba")) {
556 printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
562 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
564 printk(KERN_ERR "Failed to create pci bus for %s\n",
569 bus->primary = dev->bus->number;
570 bus->subordinate = busrange[1];
573 /* parse ranges property, or cook one up by hand for Simba */
574 /* PCI #address-cells == 3 and #size-cells == 2 always */
575 res = &dev->resource[PCI_BRIDGE_RESOURCES];
576 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
578 bus->resource[i] = res;
582 apb_fake_ranges(dev, bus, pbm);
586 for (; len >= 32; len -= 32, ranges += 8) {
587 struct resource *root;
589 flags = pci_parse_of_flags(ranges[0]);
590 size = GET_64BIT(ranges, 6);
591 if (flags == 0 || size == 0)
593 if (flags & IORESOURCE_IO) {
594 res = bus->resource[0];
596 printk(KERN_ERR "PCI: ignoring extra I/O range"
597 " for bridge %s\n", node->full_name);
600 root = &pbm->io_space;
602 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
603 printk(KERN_ERR "PCI: too many memory ranges"
604 " for bridge %s\n", node->full_name);
607 res = bus->resource[i];
609 root = &pbm->mem_space;
612 res->start = GET_64BIT(ranges, 1);
613 res->end = res->start + size - 1;
616 /* Another way to implement this would be to add an of_device
617 * layer routine that can calculate a resource for a given
618 * range property value in a PCI device.
620 pci_resource_adjust(res, root);
623 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
625 printk(" bus name: %s\n", bus->name);
627 pci_of_scan_bus(pbm, node, bus);
630 static void __init pci_of_scan_bus(struct pci_pbm_info *pbm,
631 struct device_node *node,
634 struct device_node *child;
639 printk("PCI: scan_bus[%s] bus no %d\n",
640 node->full_name, bus->number);
643 while ((child = of_get_next_child(node, child)) != NULL) {
644 printk(" * %s\n", child->full_name);
645 reg = of_get_property(child, "reg", ®len);
646 if (reg == NULL || reglen < 20)
648 devfn = (reg[0] >> 8) & 0xff;
650 /* create a new pci_dev for this device */
651 dev = of_create_pci_dev(pbm, child, bus, devfn, 0);
654 printk("PCI: dev header type: %x\n", dev->hdr_type);
656 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
657 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
658 of_scan_pci_bridge(pbm, child, dev);
663 show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
665 struct pci_dev *pdev;
666 struct device_node *dp;
668 pdev = to_pci_dev(dev);
669 dp = pdev->dev.archdata.prom_node;
671 return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name);
674 static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
676 static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus)
679 struct pci_bus *child_bus;
682 list_for_each_entry(dev, &bus->devices, bus_list) {
683 /* we don't really care if we can create this file or
684 * not, but we need to assign the result of the call
685 * or the world will fall under alien invasion and
686 * everybody will be frozen on a spaceship ready to be
687 * eaten on alpha centauri by some green and jelly
690 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
692 list_for_each_entry(child_bus, &bus->children, node)
693 pci_bus_register_of_sysfs(child_bus);
696 int pci_host_bridge_read_pci_cfg(struct pci_bus *bus_dev,
701 static u8 fake_pci_config[] = {
702 0x8e, 0x10, /* Vendor: 0x108e (Sun) */
703 0x00, 0x80, /* Device: 0x8000 (PBM) */
704 0x46, 0x01, /* Command: 0x0146 (SERR, PARITY, MASTER, MEM) */
705 0xa0, 0x22, /* Status: 0x02a0 (DEVSEL_MED, FB2B, 66MHZ) */
706 0x00, 0x00, 0x00, 0x06, /* Class: 0x06000000 host bridge */
707 0x00, /* Cacheline: 0x00 */
708 0x40, /* Latency: 0x40 */
709 0x00, /* Header-Type: 0x00 normal */
713 if (where >= 0 && where < sizeof(fake_pci_config) &&
714 (where + size) >= 0 &&
715 (where + size) < sizeof(fake_pci_config) &&
716 size <= sizeof(u32)) {
719 *value |= fake_pci_config[where + size];
723 return PCIBIOS_SUCCESSFUL;
726 int pci_host_bridge_write_pci_cfg(struct pci_bus *bus_dev,
731 return PCIBIOS_SUCCESSFUL;
734 struct pci_bus * __init pci_scan_one_pbm(struct pci_pbm_info *pbm)
736 struct pci_controller_info *p = pbm->parent;
737 struct device_node *node = pbm->prom_node;
738 struct pci_dev *host_pdev;
741 printk("PCI: Scanning PBM %s\n", node->full_name);
743 /* XXX parent device? XXX */
744 bus = pci_create_bus(NULL, pbm->pci_first_busno, p->pci_ops, pbm);
746 printk(KERN_ERR "Failed to create bus for %s\n",
750 bus->secondary = pbm->pci_first_busno;
751 bus->subordinate = pbm->pci_last_busno;
753 bus->resource[0] = &pbm->io_space;
754 bus->resource[1] = &pbm->mem_space;
756 /* Create the dummy host bridge and link it in. */
757 host_pdev = of_create_pci_dev(pbm, node, bus, 0x00, 1);
758 bus->self = host_pdev;
760 pci_of_scan_bus(pbm, node, bus);
761 pci_bus_add_devices(bus);
762 pci_bus_register_of_sysfs(bus);
767 static void __init pci_scan_each_controller_bus(void)
769 struct pci_controller_info *p;
771 for (p = pci_controller_root; p; p = p->next)
775 extern void power_init(void);
777 static int __init pcibios_init(void)
779 pci_controller_probe();
780 if (pci_controller_root == NULL)
783 pci_scan_each_controller_bus();
792 subsys_initcall(pcibios_init);
794 void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
796 struct pci_pbm_info *pbm = pbus->sysdata;
798 /* Generic PCI bus probing sets these to point at
799 * &io{port,mem}_resouce which is wrong for us.
801 pbus->resource[0] = &pbm->io_space;
802 pbus->resource[1] = &pbm->mem_space;
805 struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *r)
807 struct pci_pbm_info *pbm = pdev->bus->sysdata;
808 struct resource *root = NULL;
810 if (r->flags & IORESOURCE_IO)
811 root = &pbm->io_space;
812 if (r->flags & IORESOURCE_MEM)
813 root = &pbm->mem_space;
818 void pcibios_update_irq(struct pci_dev *pdev, int irq)
822 void pcibios_align_resource(void *data, struct resource *res,
823 resource_size_t size, resource_size_t align)
827 int pcibios_enable_device(struct pci_dev *dev, int mask)
832 pci_read_config_word(dev, PCI_COMMAND, &cmd);
835 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
836 struct resource *res = &dev->resource[i];
838 /* Only set up the requested stuff */
839 if (!(mask & (1<<i)))
842 if (res->flags & IORESOURCE_IO)
843 cmd |= PCI_COMMAND_IO;
844 if (res->flags & IORESOURCE_MEM)
845 cmd |= PCI_COMMAND_MEMORY;
849 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
851 /* Enable the appropriate bits in the PCI command register. */
852 pci_write_config_word(dev, PCI_COMMAND, cmd);
857 void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region,
858 struct resource *res)
860 struct pci_pbm_info *pbm = pdev->bus->sysdata;
861 struct resource zero_res, *root;
865 zero_res.flags = res->flags;
867 if (res->flags & IORESOURCE_IO)
868 root = &pbm->io_space;
870 root = &pbm->mem_space;
872 pci_resource_adjust(&zero_res, root);
874 region->start = res->start - zero_res.start;
875 region->end = res->end - zero_res.start;
877 EXPORT_SYMBOL(pcibios_resource_to_bus);
879 void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res,
880 struct pci_bus_region *region)
882 struct pci_pbm_info *pbm = pdev->bus->sysdata;
883 struct resource *root;
885 res->start = region->start;
886 res->end = region->end;
888 if (res->flags & IORESOURCE_IO)
889 root = &pbm->io_space;
891 root = &pbm->mem_space;
893 pci_resource_adjust(res, root);
895 EXPORT_SYMBOL(pcibios_bus_to_resource);
897 char * __devinit pcibios_setup(char *str)
902 /* Platform support for /proc/bus/pci/X/Y mmap()s. */
904 /* If the user uses a host-bridge as the PCI device, he may use
905 * this to perform a raw mmap() of the I/O or MEM space behind
908 * This can be useful for execution of x86 PCI bios initialization code
909 * on a PCI card, like the xfree86 int10 stuff does.
911 static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
912 enum pci_mmap_state mmap_state)
914 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
915 struct pci_controller_info *p;
916 unsigned long space_size, user_offset, user_size;
919 if (mmap_state == pci_mmap_io) {
920 space_size = (pbm->io_space.end -
921 pbm->io_space.start) + 1;
923 space_size = (pbm->mem_space.end -
924 pbm->mem_space.start) + 1;
927 /* Make sure the request is in range. */
928 user_offset = vma->vm_pgoff << PAGE_SHIFT;
929 user_size = vma->vm_end - vma->vm_start;
931 if (user_offset >= space_size ||
932 (user_offset + user_size) > space_size)
935 if (mmap_state == pci_mmap_io) {
936 vma->vm_pgoff = (pbm->io_space.start +
937 user_offset) >> PAGE_SHIFT;
939 vma->vm_pgoff = (pbm->mem_space.start +
940 user_offset) >> PAGE_SHIFT;
946 /* Adjust vm_pgoff of VMA such that it is the physical page offset corresponding
947 * to the 32-bit pci bus offset for DEV requested by the user.
949 * Basically, the user finds the base address for his device which he wishes
950 * to mmap. They read the 32-bit value from the config space base register,
951 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
952 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
954 * Returns negative error code on failure, zero on success.
956 static int __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
957 enum pci_mmap_state mmap_state)
959 unsigned long user_offset = vma->vm_pgoff << PAGE_SHIFT;
960 unsigned long user32 = user_offset & pci_memspace_mask;
961 unsigned long largest_base, this_base, addr32;
964 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
965 return __pci_mmap_make_offset_bus(dev, vma, mmap_state);
967 /* Figure out which base address this is for. */
969 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
970 struct resource *rp = &dev->resource[i];
977 if (i == PCI_ROM_RESOURCE) {
978 if (mmap_state != pci_mmap_mem)
981 if ((mmap_state == pci_mmap_io &&
982 (rp->flags & IORESOURCE_IO) == 0) ||
983 (mmap_state == pci_mmap_mem &&
984 (rp->flags & IORESOURCE_MEM) == 0))
988 this_base = rp->start;
990 addr32 = (this_base & PAGE_MASK) & pci_memspace_mask;
992 if (mmap_state == pci_mmap_io)
995 if (addr32 <= user32 && this_base > largest_base)
996 largest_base = this_base;
999 if (largest_base == 0UL)
1002 /* Now construct the final physical address. */
1003 if (mmap_state == pci_mmap_io)
1004 vma->vm_pgoff = (((largest_base & ~0xffffffUL) | user32) >> PAGE_SHIFT);
1006 vma->vm_pgoff = (((largest_base & ~(pci_memspace_mask)) | user32) >> PAGE_SHIFT);
1011 /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
1014 static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
1015 enum pci_mmap_state mmap_state)
1017 vma->vm_flags |= (VM_IO | VM_RESERVED);
1020 /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
1023 static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
1024 enum pci_mmap_state mmap_state)
1026 /* Our io_remap_pfn_range takes care of this, do nothing. */
1029 /* Perform the actual remap of the pages for a PCI device mapping, as appropriate
1030 * for this architecture. The region in the process to map is described by vm_start
1031 * and vm_end members of VMA, the base physical address is found in vm_pgoff.
1032 * The pci device structure is provided so that architectures may make mapping
1033 * decisions on a per-device or per-bus basis.
1035 * Returns a negative error code on failure, zero on success.
1037 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
1038 enum pci_mmap_state mmap_state,
1043 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
1047 __pci_mmap_set_flags(dev, vma, mmap_state);
1048 __pci_mmap_set_pgprot(dev, vma, mmap_state);
1050 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1051 ret = io_remap_pfn_range(vma, vma->vm_start,
1053 vma->vm_end - vma->vm_start,
1061 /* Return the domain nuber for this pci bus */
1063 int pci_domain_nr(struct pci_bus *pbus)
1065 struct pci_pbm_info *pbm = pbus->sysdata;
1068 if (pbm == NULL || pbm->parent == NULL) {
1071 struct pci_controller_info *p = pbm->parent;
1075 ((pbm == &pbm->parent->pbm_B) ? 1 : 0));
1080 EXPORT_SYMBOL(pci_domain_nr);
1082 #ifdef CONFIG_PCI_MSI
1083 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
1085 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1086 struct pci_controller_info *p = pbm->parent;
1089 if (!pbm->msi_num || !p->setup_msi_irq)
1092 err = p->setup_msi_irq(&virt_irq, pdev, desc);
1099 void arch_teardown_msi_irq(unsigned int virt_irq)
1101 struct msi_desc *entry = get_irq_msi(virt_irq);
1102 struct pci_dev *pdev = entry->dev;
1103 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1104 struct pci_controller_info *p = pbm->parent;
1106 if (!pbm->msi_num || !p->setup_msi_irq)
1109 return p->teardown_msi_irq(virt_irq, pdev);
1111 #endif /* !(CONFIG_PCI_MSI) */
1113 struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
1115 return pdev->dev.archdata.prom_node;
1117 EXPORT_SYMBOL(pci_device_to_OF_node);
1119 #endif /* !(CONFIG_PCI) */