1 /* arch/sparc64/kernel/ktlb.S: Kernel mapping TLB miss handling.
3 * Copyright (C) 1995, 1997, 2005 David S. Miller <davem@davemloft.net>
4 * Copyright (C) 1996 Eddie C. Dost (ecd@brainaid.de)
5 * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
6 * Copyright (C) 1996,98,99 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
9 #include <linux/config.h>
13 #include <asm/pgtable.h>
21 mov TLB_TAG_ACCESS, %g4
22 ldxa [%g4] ASI_IMMU, %g4
24 /* sun4v_itlb_miss branches here with the missing virtual
25 * address already loaded into %g4
30 /* Catch kernel NULL pointer calls. */
31 sethi %hi(PAGE_SIZE), %g5
33 bleu,pn %xcc, kvmap_dtlb_longpath
36 KERN_TSB_LOOKUP_TL1(%g4, %g6, %g5, %g1, %g2, %g3, kvmap_itlb_load)
39 sethi %hi(LOW_OBP_ADDRESS), %g5
41 blu,pn %xcc, kvmap_itlb_vmalloc_addr
45 blu,pn %xcc, kvmap_itlb_obp
48 kvmap_itlb_vmalloc_addr:
49 KERN_PGTABLE_WALK(%g4, %g5, %g2, kvmap_itlb_longpath)
51 KTSB_LOCK_TAG(%g1, %g2, %g7)
53 /* Load and check PTE. */
54 ldxa [%g5] ASI_PHYS_USE_EC, %g5
55 brgez,a,pn %g5, kvmap_itlb_longpath
58 KTSB_WRITE(%g1, %g5, %g6)
60 /* fallthrough to TLB load */
64 661: stxa %g5, [%g0] ASI_ITLB_DATA_IN
66 .section .sun4v_2insn_patch, "ax"
72 /* For sun4v the ASI_ITLB_DATA_IN store and the retry
73 * instruction get nop'd out and we get here to branch
74 * to the sun4v tlb load code. The registers are setup
81 * The sun4v TLB load wants the PTE in %g3 so we fix that
84 ba,pt %xcc, sun4v_itlb_load
89 661: rdpr %pstate, %g5
90 wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
91 .section .sun4v_2insn_patch, "ax"
98 ba,pt %xcc, sparc64_realfault_common
99 mov FAULT_CODE_ITLB, %g4
102 OBP_TRANS_LOOKUP(%g4, %g5, %g2, %g3, kvmap_itlb_longpath)
104 KTSB_LOCK_TAG(%g1, %g2, %g7)
106 KTSB_WRITE(%g1, %g5, %g6)
108 ba,pt %xcc, kvmap_itlb_load
112 OBP_TRANS_LOOKUP(%g4, %g5, %g2, %g3, kvmap_dtlb_longpath)
114 KTSB_LOCK_TAG(%g1, %g2, %g7)
116 KTSB_WRITE(%g1, %g5, %g6)
118 ba,pt %xcc, kvmap_dtlb_load
123 /* %g6: TAG TARGET */
124 mov TLB_TAG_ACCESS, %g4
125 ldxa [%g4] ASI_DMMU, %g4
127 /* sun4v_dtlb_miss branches here with the missing virtual
128 * address already loaded into %g4
131 brgez,pn %g4, kvmap_dtlb_nonlinear
134 #define KERN_HIGHBITS ((_PAGE_VALID|_PAGE_SZ4MB)^0xfffff80000000000)
135 #define KERN_LOWBITS (_PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_W)
137 sethi %uhi(KERN_HIGHBITS), %g2
138 or %g2, %ulo(KERN_HIGHBITS), %g2
140 or %g2, KERN_LOWBITS, %g2
145 .globl kvmap_linear_patch
147 ba,pt %xcc, kvmap_dtlb_load
150 kvmap_dtlb_vmalloc_addr:
151 KERN_PGTABLE_WALK(%g4, %g5, %g2, kvmap_dtlb_longpath)
153 KTSB_LOCK_TAG(%g1, %g2, %g7)
155 /* Load and check PTE. */
156 ldxa [%g5] ASI_PHYS_USE_EC, %g5
157 brgez,a,pn %g5, kvmap_dtlb_longpath
160 KTSB_WRITE(%g1, %g5, %g6)
162 /* fallthrough to TLB load */
166 661: stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Reload TLB
168 .section .sun4v_2insn_patch, "ax"
174 /* For sun4v the ASI_DTLB_DATA_IN store and the retry
175 * instruction get nop'd out and we get here to branch
176 * to the sun4v tlb load code. The registers are setup
183 * The sun4v TLB load wants the PTE in %g3 so we fix that
186 ba,pt %xcc, sun4v_dtlb_load
189 kvmap_dtlb_nonlinear:
190 /* Catch kernel NULL pointer derefs. */
191 sethi %hi(PAGE_SIZE), %g5
193 bleu,pn %xcc, kvmap_dtlb_longpath
196 KERN_TSB_LOOKUP_TL1(%g4, %g6, %g5, %g1, %g2, %g3, kvmap_dtlb_load)
199 sethi %hi(MODULES_VADDR), %g5
201 blu,pn %xcc, kvmap_dtlb_longpath
202 mov (VMALLOC_END >> 24), %g5
205 bgeu,pn %xcc, kvmap_dtlb_longpath
209 sethi %hi(LOW_OBP_ADDRESS), %g5
211 blu,pn %xcc, kvmap_dtlb_vmalloc_addr
215 blu,pn %xcc, kvmap_dtlb_obp
217 ba,pt %xcc, kvmap_dtlb_vmalloc_addr
222 661: rdpr %pstate, %g5
223 wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
224 .section .sun4v_2insn_patch, "ax"
233 661: mov TLB_TAG_ACCESS, %g4
234 ldxa [%g4] ASI_DMMU, %g5
235 .section .sun4v_2insn_patch, "ax"
241 be,pt %xcc, sparc64_realfault_common
242 mov FAULT_CODE_DTLB, %g4
243 ba,pt %xcc, winfix_trampoline