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   1 /* $Id: irq.c,v 1.114 2002/01/11 08:45:38 davem Exp $
   2  * irq.c: UltraSparc IRQ handling/init/registry.
   3  *
   4  * Copyright (C) 1997  David S. Miller  (davem@caip.rutgers.edu)
   5  * Copyright (C) 1998  Eddie C. Dost    (ecd@skynet.be)
   6  * Copyright (C) 1998  Jakub Jelinek    (jj@ultra.linux.cz)
   7  */
   8
   9 #include <linux/config.h>
  10 #include <linux/module.h>
  11 #include <linux/sched.h>
  12 #include <linux/ptrace.h>
  13 #include <linux/errno.h>
  14 #include <linux/kernel_stat.h>
  15 #include <linux/signal.h>
  16 #include <linux/mm.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/slab.h>
  19 #include <linux/random.h>
  20 #include <linux/init.h>
  21 #include <linux/delay.h>
  22 #include <linux/proc_fs.h>
  23 #include <linux/seq_file.h>
  24
  25 #include <asm/ptrace.h>
  26 #include <asm/processor.h>
  27 #include <asm/atomic.h>
  28 #include <asm/system.h>
  29 #include <asm/irq.h>
  30 #include <asm/io.h>
  31 #include <asm/sbus.h>
  32 #include <asm/iommu.h>
  33 #include <asm/upa.h>
  34 #include <asm/oplib.h>
  35 #include <asm/timer.h>
  36 #include <asm/smp.h>
  37 #include <asm/starfire.h>
  38 #include <asm/uaccess.h>
  39 #include <asm/cache.h>
  40 #include <asm/cpudata.h>
  41 #include <asm/auxio.h>
  42 #include <asm/head.h>
  43
  44 #ifdef CONFIG_SMP
  45 static void distribute_irqs(void);
  46 #endif
  47
  48 /* UPA nodes send interrupt packet to UltraSparc with first data reg
  49  * value low 5 (7 on Starfire) bits holding the IRQ identifier being
  50  * delivered.  We must translate this into a non-vector IRQ so we can
  51  * set the softint on this cpu.
  52  *
  53  * To make processing these packets efficient and race free we use
  54  * an array of irq buckets below.  The interrupt vector handler in
  55  * entry.S feeds incoming packets into per-cpu pil-indexed lists.
  56  * The IVEC handler does not need to act atomically, the PIL dispatch
  57  * code uses CAS to get an atomic snapshot of the list and clear it
  58  * at the same time.
  59  */
  60
  61 struct ino_bucket ivector_table[NUM_IVECS] __attribute__ ((aligned (SMP_CACHE_BYTES)));
  62
  63 /* This has to be in the main kernel image, it cannot be
  64  * turned into per-cpu data.  The reason is that the main
  65  * kernel image is locked into the TLB and this structure
  66  * is accessed from the vectored interrupt trap handler.  If
  67  * access to this structure takes a TLB miss it could cause
  68  * the 5-level sparc v9 trap stack to overflow.
  69  */
  70 struct irq_work_struct {
  71         unsigned int    irq_worklists[16];
  72 };
  73 struct irq_work_struct __irq_work[NR_CPUS];
  74 #define irq_work(__cpu, __pil)  &(__irq_work[(__cpu)].irq_worklists[(__pil)])
  75
  76 static struct irqaction *irq_action[NR_IRQS+1];
  77
  78 /* This only synchronizes entities which modify IRQ handler
  79  * state and some selected user-level spots that want to
  80  * read things in the table.  IRQ handler processing orders
  81  * its' accesses such that no locking is needed.
  82  */
  83 static DEFINE_SPINLOCK(irq_action_lock);
  84
  85 static void register_irq_proc (unsigned int irq);
  86
  87 /*
  88  * Upper 2b of irqaction->flags holds the ino.
  89  * irqaction->mask holds the smp affinity information.
  90  */
  91 #define put_ino_in_irqaction(action, irq) \
  92         action->flags &= 0xffffffffffffUL; \
  93         if (__bucket(irq) == &pil0_dummy_bucket) \
  94                 action->flags |= 0xdeadUL << 48;  \
  95         else \
  96                 action->flags |= __irq_ino(irq) << 48;
  97 #define get_ino_in_irqaction(action)    (action->flags >> 48)
  98
  99 #define put_smpaff_in_irqaction(action, smpaff) (action)->mask = (smpaff)
 100 #define get_smpaff_in_irqaction(action)         ((action)->mask)
 101
 102 int show_interrupts(struct seq_file *p, void *v)
 103 {
 104         unsigned long flags;
 105         int i = *(loff_t *) v;
 106         struct irqaction *action;
 107 #ifdef CONFIG_SMP
 108         int j;
 109 #endif
 110
 111         spin_lock_irqsave(&irq_action_lock, flags);
 112         if (i <= NR_IRQS) {
 113                 if (!(action = *(i + irq_action)))
 114                         goto out_unlock;
 115                 seq_printf(p, "%3d: ", i);
 116 #ifndef CONFIG_SMP
 117                 seq_printf(p, "%10u ", kstat_irqs(i));
 118 #else
 119                 for (j = 0; j < NR_CPUS; j++) {
 120                         if (!cpu_online(j))
 121                                 continue;
 122                         seq_printf(p, "%10u ",
 123                                    kstat_cpu(j).irqs[i]);
 124                 }
 125 #endif
 126                 seq_printf(p, " %s:%lx", action->name,
 127                            get_ino_in_irqaction(action));
 128                 for (action = action->next; action; action = action->next) {
 129                         seq_printf(p, ", %s:%lx", action->name,
 130                                    get_ino_in_irqaction(action));
 131                 }
 132                 seq_putc(p, '\n');
 133         }
 134 out_unlock:
 135         spin_unlock_irqrestore(&irq_action_lock, flags);
 136
 137         return 0;
 138 }
 139
 140 /* Now these are always passed a true fully specified sun4u INO. */
 141 void enable_irq(unsigned int irq)
 142 {
 143         struct ino_bucket *bucket = __bucket(irq);
 144         unsigned long imap;
 145         unsigned long tid;
 146
 147         imap = bucket->imap;
 148         if (imap == 0UL)
 149                 return;
 150
 151         preempt_disable();
 152
 153         if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 154                 unsigned long ver;
 155
 156                 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
 157                 if ((ver >> 32) == __JALAPENO_ID ||
 158                     (ver >> 32) == __SERRANO_ID) {
 159                         /* We set it to our JBUS ID. */
 160                         __asm__ __volatile__("ldxa [%%g0] %1, %0"
 161                                              : "=r" (tid)
 162                                              : "i" (ASI_JBUS_CONFIG));
 163                         tid = ((tid & (0x1fUL<<17)) << 9);
 164                         tid &= IMAP_TID_JBUS;
 165                 } else {
 166                         /* We set it to our Safari AID. */
 167                         __asm__ __volatile__("ldxa [%%g0] %1, %0"
 168                                              : "=r" (tid)
 169                                              : "i" (ASI_SAFARI_CONFIG));
 170                         tid = ((tid & (0x3ffUL<<17)) << 9);
 171                         tid &= IMAP_AID_SAFARI;
 172                 }
 173         } else if (this_is_starfire == 0) {
 174                 /* We set it to our UPA MID. */
 175                 __asm__ __volatile__("ldxa [%%g0] %1, %0"
 176                                      : "=r" (tid)
 177                                      : "i" (ASI_UPA_CONFIG));
 178                 tid = ((tid & UPA_CONFIG_MID) << 9);
 179                 tid &= IMAP_TID_UPA;
 180         } else {
 181                 tid = (starfire_translate(imap, smp_processor_id()) << 26);
 182                 tid &= IMAP_TID_UPA;
 183         }
 184
 185         /* NOTE NOTE NOTE, IGN and INO are read-only, IGN is a product
 186          * of this SYSIO's preconfigured IGN in the SYSIO Control
 187          * Register, the hardware just mirrors that value here.
 188          * However for Graphics and UPA Slave devices the full
 189          * IMAP_INR field can be set by the programmer here.
 190          *
 191          * Things like FFB can now be handled via the new IRQ mechanism.
 192          */
 193         upa_writel(tid | IMAP_VALID, imap);
 194
 195         preempt_enable();
 196 }
 197
 198 /* This now gets passed true ino's as well. */
 199 void disable_irq(unsigned int irq)
 200 {
 201         struct ino_bucket *bucket = __bucket(irq);
 202         unsigned long imap;
 203
 204         imap = bucket->imap;
 205         if (imap != 0UL) {
 206                 u32 tmp;
 207
 208                 /* NOTE: We do not want to futz with the IRQ clear registers
 209                  *       and move the state to IDLE, the SCSI code does call
 210                  *       disable_irq() to assure atomicity in the queue cmd
 211                  *       SCSI adapter driver code.  Thus we'd lose interrupts.
 212                  */
 213                 tmp = upa_readl(imap);
 214                 tmp &= ~IMAP_VALID;
 215                 upa_writel(tmp, imap);
 216         }
 217 }
 218
 219 /* The timer is the one "weird" interrupt which is generated by
 220  * the CPU %tick register and not by some normal vectored interrupt
 221  * source.  To handle this special case, we use this dummy INO bucket.
 222  */
 223 static struct irq_desc pil0_dummy_desc;
 224 static struct ino_bucket pil0_dummy_bucket = {
 225         .irq_info       =       &pil0_dummy_desc,
 226 };
 227
 228 static void build_irq_error(const char *msg, unsigned int ino, int pil, int inofixup,
 229                             unsigned long iclr, unsigned long imap,
 230                             struct ino_bucket *bucket)
 231 {
 232         prom_printf("IRQ: INO %04x (%d:%016lx:%016lx) --> "
 233                     "(%d:%d:%016lx:%016lx), halting...\n",
 234                     ino, bucket->pil, bucket->iclr, bucket->imap,
 235                     pil, inofixup, iclr, imap);
 236         prom_halt();
 237 }
 238
 239 unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap)
 240 {
 241         struct ino_bucket *bucket;
 242         int ino;
 243
 244         if (pil == 0) {
 245                 if (iclr != 0UL || imap != 0UL) {
 246                         prom_printf("Invalid dummy bucket for PIL0 (%lx:%lx)\n",
 247                                     iclr, imap);
 248                         prom_halt();
 249                 }
 250                 return __irq(&pil0_dummy_bucket);
 251         }
 252
 253         /* RULE: Both must be specified in all other cases. */
 254         if (iclr == 0UL || imap == 0UL) {
 255                 prom_printf("Invalid build_irq %d %d %016lx %016lx\n",
 256                             pil, inofixup, iclr, imap);
 257                 prom_halt();
 258         }
 259
 260         ino = (upa_readl(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
 261         if (ino > NUM_IVECS) {
 262                 prom_printf("Invalid INO %04x (%d:%d:%016lx:%016lx)\n",
 263                             ino, pil, inofixup, iclr, imap);
 264                 prom_halt();
 265         }
 266
 267         bucket = &ivector_table[ino];
 268         if (bucket->flags & IBF_ACTIVE)
 269                 build_irq_error("IRQ: Trying to build active INO bucket.\n",
 270                                 ino, pil, inofixup, iclr, imap, bucket);
 271
 272         if (bucket->irq_info) {
 273                 if (bucket->imap != imap || bucket->iclr != iclr)
 274                         build_irq_error("IRQ: Trying to reinit INO bucket.\n",
 275                                         ino, pil, inofixup, iclr, imap, bucket);
 276
 277                 goto out;
 278         }
 279
 280         bucket->irq_info = kmalloc(sizeof(struct irq_desc), GFP_ATOMIC);
 281         if (!bucket->irq_info) {
 282                 prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n");
 283                 prom_halt();
 284         }
 285         memset(bucket->irq_info, 0, sizeof(struct irq_desc));
 286
 287         /* Ok, looks good, set it up.  Don't touch the irq_chain or
 288          * the pending flag.
 289          */
 290         bucket->imap  = imap;
 291         bucket->iclr  = iclr;
 292         bucket->pil   = pil;
 293         bucket->flags = 0;
 294
 295 out:
 296         return __irq(bucket);
 297 }
 298
 299 static void atomic_bucket_insert(struct ino_bucket *bucket)
 300 {
 301         unsigned long pstate;
 302         unsigned int *ent;
 303
 304         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
 305         __asm__ __volatile__("wrpr %0, %1, %%pstate"
 306                              : : "r" (pstate), "i" (PSTATE_IE));
 307         ent = irq_work(smp_processor_id(), bucket->pil);
 308         bucket->irq_chain = *ent;
 309         *ent = __irq(bucket);
 310         __asm__ __volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate));
 311 }
 312
 313 static int check_irq_sharing(int pil, unsigned long irqflags)
 314 {
 315         struct irqaction *action, *tmp;
 316
 317         action = *(irq_action + pil);
 318         if (action) {
 319                 if ((action->flags & SA_SHIRQ) && (irqflags & SA_SHIRQ)) {
 320                         for (tmp = action; tmp->next; tmp = tmp->next)
 321                                 ;
 322                 } else {
 323                         return -EBUSY;
 324                 }
 325         }
 326         return 0;
 327 }
 328
 329 static void append_irq_action(int pil, struct irqaction *action)
 330 {
 331         struct irqaction **pp = irq_action + pil;
 332
 333         while (*pp)
 334                 pp = &((*pp)->next);
 335         *pp = action;
 336 }
 337
 338 static struct irqaction *get_action_slot(struct ino_bucket *bucket)
 339 {
 340         struct irq_desc *desc = bucket->irq_info;
 341         int max_irq, i;
 342
 343         max_irq = 1;
 344         if (bucket->flags & IBF_PCI)
 345                 max_irq = MAX_IRQ_DESC_ACTION;
 346         for (i = 0; i < max_irq; i++) {
 347                 struct irqaction *p = &desc->action[i];
 348                 u32 mask = (1 << i);
 349
 350                 if (desc->action_active_mask & mask)
 351                         continue;
 352
 353                 desc->action_active_mask |= mask;
 354                 return p;
 355         }
 356         return NULL;
 357 }
 358
 359 int request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_regs *),
 360                 unsigned long irqflags, const char *name, void *dev_id)
 361 {
 362         struct irqaction *action;
 363         struct ino_bucket *bucket = __bucket(irq);
 364         unsigned long flags;
 365         int pending = 0;
 366
 367         if (unlikely(!handler))
 368                 return -EINVAL;
 369
 370         if (unlikely(!bucket->irq_info))
 371                 return -ENODEV;
 372
 373         if ((bucket != &pil0_dummy_bucket) && (irqflags & SA_SAMPLE_RANDOM)) {
 374                 /*
 375                  * This function might sleep, we want to call it first,
 376                  * outside of the atomic block. In SA_STATIC_ALLOC case,
 377                  * random driver's kmalloc will fail, but it is safe.
 378                  * If already initialized, random driver will not reinit.
 379                  * Yes, this might clear the entropy pool if the wrong
 380                  * driver is attempted to be loaded, without actually
 381                  * installing a new handler, but is this really a problem,
 382                  * only the sysadmin is able to do this.
 383                  */
 384                 rand_initialize_irq(irq);
 385         }
 386
 387         spin_lock_irqsave(&irq_action_lock, flags);
 388
 389         if (check_irq_sharing(bucket->pil, irqflags)) {
 390                 spin_unlock_irqrestore(&irq_action_lock, flags);
 391                 return -EBUSY;
 392         }
 393
 394         action = get_action_slot(bucket);
 395         if (!action) {
 396                 spin_unlock_irqrestore(&irq_action_lock, flags);
 397                 return -ENOMEM;
 398         }
 399
 400         bucket->flags |= IBF_ACTIVE;
 401         pending = 0;
 402         if (bucket != &pil0_dummy_bucket) {
 403                 pending = bucket->pending;
 404                 if (pending)
 405                         bucket->pending = 0;
 406         }
 407
 408         action->handler = handler;
 409         action->flags = irqflags;
 410         action->name = name;
 411         action->next = NULL;
 412         action->dev_id = dev_id;
 413         put_ino_in_irqaction(action, irq);
 414         put_smpaff_in_irqaction(action, CPU_MASK_NONE);
 415
 416         append_irq_action(bucket->pil, action);
 417
 418         enable_irq(irq);
 419
 420         /* We ate the IVEC already, this makes sure it does not get lost. */
 421         if (pending) {
 422                 atomic_bucket_insert(bucket);
 423                 set_softint(1 << bucket->pil);
 424         }
 425
 426         spin_unlock_irqrestore(&irq_action_lock, flags);
 427
 428         if (bucket != &pil0_dummy_bucket)
 429                 register_irq_proc(__irq_ino(irq));
 430
 431 #ifdef CONFIG_SMP
 432         distribute_irqs();
 433 #endif
 434         return 0;
 435 }
 436
 437 EXPORT_SYMBOL(request_irq);
 438
 439 static struct irqaction *unlink_irq_action(unsigned int irq, void *dev_id)
 440 {
 441         struct ino_bucket *bucket = __bucket(irq);
 442         struct irqaction *action, **pp;
 443
 444         pp = irq_action + bucket->pil;
 445         action = *pp;
 446         if (unlikely(!action))
 447                 return NULL;
 448
 449         if (unlikely(!action->handler)) {
 450                 printk("Freeing free IRQ %d\n", bucket->pil);
 451                 return NULL;
 452         }
 453
 454         while (action && action->dev_id != dev_id) {
 455                 pp = &action->next;
 456                 action = *pp;
 457         }
 458
 459         if (likely(action))
 460                 *pp = action->next;
 461
 462         return action;
 463 }
 464
 465 void free_irq(unsigned int irq, void *dev_id)
 466 {
 467         struct irqaction *action;
 468         struct ino_bucket *bucket;
 469         unsigned long flags;
 470
 471         spin_lock_irqsave(&irq_action_lock, flags);
 472
 473         action = unlink_irq_action(irq, dev_id);
 474
 475         spin_unlock_irqrestore(&irq_action_lock, flags);
 476
 477         if (unlikely(!action))
 478                 return;
 479
 480         synchronize_irq(irq);
 481
 482         spin_lock_irqsave(&irq_action_lock, flags);
 483
 484         bucket = __bucket(irq);
 485         if (bucket != &pil0_dummy_bucket) {
 486                 struct irq_desc *desc = bucket->irq_info;
 487                 unsigned long imap = bucket->imap;
 488                 int ent, i;
 489
 490                 for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) {
 491                         struct irqaction *p = &desc->action[i];
 492
 493                         if (p == action) {
 494                                 desc->action_active_mask &= ~(1 << i);
 495                                 break;
 496                         }
 497                 }
 498
 499                 if (!desc->action_active_mask) {
 500                         /* This unique interrupt source is now inactive. */
 501                         bucket->flags &= ~IBF_ACTIVE;
 502
 503                         /* See if any other buckets share this bucket's IMAP
 504                          * and are still active.
 505                          */
 506                         for (ent = 0; ent < NUM_IVECS; ent++) {
 507                                 struct ino_bucket *bp = &ivector_table[ent];
 508                                 if (bp != bucket        &&
 509                                     bp->imap == imap    &&
 510                                     (bp->flags & IBF_ACTIVE) != 0)
 511                                         break;
 512                         }
 513
 514                         /* Only disable when no other sub-irq levels of
 515                          * the same IMAP are active.
 516                          */
 517                         if (ent == NUM_IVECS)
 518                                 disable_irq(irq);
 519                 }
 520         }
 521
 522         spin_unlock_irqrestore(&irq_action_lock, flags);
 523 }
 524
 525 EXPORT_SYMBOL(free_irq);
 526
 527 #ifdef CONFIG_SMP
 528 void synchronize_irq(unsigned int irq)
 529 {
 530         struct ino_bucket *bucket = __bucket(irq);
 531
 532 #if 0
 533         /* The following is how I wish I could implement this.
 534          * Unfortunately the ICLR registers are read-only, you can
 535          * only write ICLR_foo values to them.  To get the current
 536          * IRQ status you would need to get at the IRQ diag registers
 537          * in the PCI/SBUS controller and the layout of those vary
 538          * from one controller to the next, sigh... -DaveM
 539          */
 540         unsigned long iclr = bucket->iclr;
 541
 542         while (1) {
 543                 u32 tmp = upa_readl(iclr);
 544
 545                 if (tmp == ICLR_TRANSMIT ||
 546                     tmp == ICLR_PENDING) {
 547                         cpu_relax();
 548                         continue;
 549                 }
 550                 break;
 551         }
 552 #else
 553         /* So we have to do this with a INPROGRESS bit just like x86.  */
 554         while (bucket->flags & IBF_INPROGRESS)
 555                 cpu_relax();
 556 #endif
 557 }
 558 #endif /* CONFIG_SMP */
 559
 560 static void process_bucket(int irq, struct ino_bucket *bp, struct pt_regs *regs)
 561 {
 562         struct irq_desc *desc = bp->irq_info;
 563         unsigned char flags = bp->flags;
 564         u32 action_mask, i;
 565         int random;
 566
 567         bp->flags |= IBF_INPROGRESS;
 568
 569         if (unlikely(!(flags & IBF_ACTIVE))) {
 570                 bp->pending = 1;
 571                 goto out;
 572         }
 573
 574         if (desc->pre_handler)
 575                 desc->pre_handler(bp,
 576                                   desc->pre_handler_arg1,
 577                                   desc->pre_handler_arg2);
 578
 579         action_mask = desc->action_active_mask;
 580         random = 0;
 581         for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) {
 582                 struct irqaction *p = &desc->action[i];
 583                 u32 mask = (1 << i);
 584
 585                 if (!(action_mask & mask))
 586                         continue;
 587
 588                 action_mask &= ~mask;
 589
 590                 if (p->handler(__irq(bp), p->dev_id, regs) == IRQ_HANDLED)
 591                         random |= p->flags;
 592
 593                 if (!action_mask)
 594                         break;
 595         }
 596         if (bp->pil != 0) {
 597                 upa_writel(ICLR_IDLE, bp->iclr);
 598                 /* Test and add entropy */
 599                 if (random & SA_SAMPLE_RANDOM)
 600                         add_interrupt_randomness(irq);
 601         }
 602 out:
 603         bp->flags &= ~IBF_INPROGRESS;
 604 }
 605
 606 void handler_irq(int irq, struct pt_regs *regs)
 607 {
 608         struct ino_bucket *bp;
 609         int cpu = smp_processor_id();
 610
 611 #ifndef CONFIG_SMP
 612         /*
 613          * Check for TICK_INT on level 14 softint.
 614          */
 615         {
 616                 unsigned long clr_mask = 1 << irq;
 617                 unsigned long tick_mask = tick_ops->softint_mask;
 618
 619                 if ((irq == 14) && (get_softint() & tick_mask)) {
 620                         irq = 0;
 621                         clr_mask = tick_mask;
 622                 }
 623                 clear_softint(clr_mask);
 624         }
 625 #else
 626         clear_softint(1 << irq);
 627 #endif
 628
 629         irq_enter();
 630         kstat_this_cpu.irqs[irq]++;
 631
 632         /* Sliiiick... */
 633 #ifndef CONFIG_SMP
 634         bp = ((irq != 0) ?
 635               __bucket(xchg32(irq_work(cpu, irq), 0)) :
 636               &pil0_dummy_bucket);
 637 #else
 638         bp = __bucket(xchg32(irq_work(cpu, irq), 0));
 639 #endif
 640         while (bp) {
 641                 struct ino_bucket *nbp = __bucket(bp->irq_chain);
 642
 643                 bp->irq_chain = 0;
 644                 process_bucket(irq, bp, regs);
 645                 bp = nbp;
 646         }
 647         irq_exit();
 648 }
 649
 650 #ifdef CONFIG_BLK_DEV_FD
 651 extern irqreturn_t floppy_interrupt(int, void *, struct pt_regs *);;
 652
 653 /* XXX No easy way to include asm/floppy.h XXX */
 654 extern unsigned char *pdma_vaddr;
 655 extern unsigned long pdma_size;
 656 extern volatile int doing_pdma;
 657 extern unsigned long fdc_status;
 658
 659 irqreturn_t sparc_floppy_irq(int irq, void *dev_cookie, struct pt_regs *regs)
 660 {
 661         if (likely(doing_pdma)) {
 662                 void __iomem *stat = (void __iomem *) fdc_status;
 663                 unsigned char *vaddr = pdma_vaddr;
 664                 unsigned long size = pdma_size;
 665                 u8 val;
 666
 667                 while (size) {
 668                         val = readb(stat);
 669                         if (unlikely(!(val & 0x80))) {
 670                                 pdma_vaddr = vaddr;
 671                                 pdma_size = size;
 672                                 return IRQ_HANDLED;
 673                         }
 674                         if (unlikely(!(val & 0x20))) {
 675                                 pdma_vaddr = vaddr;
 676                                 pdma_size = size;
 677                                 doing_pdma = 0;
 678                                 goto main_interrupt;
 679                         }
 680                         if (val & 0x40) {
 681                                 /* read */
 682                                 *vaddr++ = readb(stat + 1);
 683                         } else {
 684                                 unsigned char data = *vaddr++;
 685
 686                                 /* write */
 687                                 writeb(data, stat + 1);
 688                         }
 689                         size--;
 690                 }
 691
 692                 pdma_vaddr = vaddr;
 693                 pdma_size = size;
 694
 695                 /* Send Terminal Count pulse to floppy controller. */
 696                 val = readb(auxio_register);
 697                 val |= AUXIO_AUX1_FTCNT;
 698                 writeb(val, auxio_register);
 699                 val &= ~AUXIO_AUX1_FTCNT;
 700                 writeb(val, auxio_register);
 701
 702                 doing_pdma = 0;
 703         }
 704
 705 main_interrupt:
 706         return floppy_interrupt(irq, dev_cookie, regs);
 707 }
 708 EXPORT_SYMBOL(sparc_floppy_irq);
 709 #endif
 710
 711 /* We really don't need these at all on the Sparc.  We only have
 712  * stubs here because they are exported to modules.
 713  */
 714 unsigned long probe_irq_on(void)
 715 {
 716         return 0;
 717 }
 718
 719 EXPORT_SYMBOL(probe_irq_on);
 720
 721 int probe_irq_off(unsigned long mask)
 722 {
 723         return 0;
 724 }
 725
 726 EXPORT_SYMBOL(probe_irq_off);
 727
 728 #ifdef CONFIG_SMP
 729 static int retarget_one_irq(struct irqaction *p, int goal_cpu)
 730 {
 731         struct ino_bucket *bucket = get_ino_in_irqaction(p) + ivector_table;
 732         unsigned long imap = bucket->imap;
 733         unsigned int tid;
 734
 735         while (!cpu_online(goal_cpu)) {
 736                 if (++goal_cpu >= NR_CPUS)
 737                         goal_cpu = 0;
 738         }
 739
 740         if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 741                 tid = goal_cpu << 26;
 742                 tid &= IMAP_AID_SAFARI;
 743         } else if (this_is_starfire == 0) {
 744                 tid = goal_cpu << 26;
 745                 tid &= IMAP_TID_UPA;
 746         } else {
 747                 tid = (starfire_translate(imap, goal_cpu) << 26);
 748                 tid &= IMAP_TID_UPA;
 749         }
 750         upa_writel(tid | IMAP_VALID, imap);
 751
 752         do {
 753                 if (++goal_cpu >= NR_CPUS)
 754                         goal_cpu = 0;
 755         } while (!cpu_online(goal_cpu));
 756
 757         return goal_cpu;
 758 }
 759
 760 /* Called from request_irq. */
 761 static void distribute_irqs(void)
 762 {
 763         unsigned long flags;
 764         int cpu, level;
 765
 766         spin_lock_irqsave(&irq_action_lock, flags);
 767         cpu = 0;
 768
 769         /*
 770          * Skip the timer at [0], and very rare error/power intrs at [15].
 771          * Also level [12], it causes problems on Ex000 systems.
 772          */
 773         for (level = 1; level < NR_IRQS; level++) {
 774                 struct irqaction *p = irq_action[level];
 775
 776                 if (level == 12)
 777                         continue;
 778
 779                 while(p) {
 780                         cpu = retarget_one_irq(p, cpu);
 781                         p = p->next;
 782                 }
 783         }
 784         spin_unlock_irqrestore(&irq_action_lock, flags);
 785 }
 786 #endif
 787
 788 struct sun5_timer {
 789         u64     count0;
 790         u64     limit0;
 791         u64     count1;
 792         u64     limit1;
 793 };
 794
 795 static struct sun5_timer *prom_timers;
 796 static u64 prom_limit0, prom_limit1;
 797
 798 static void map_prom_timers(void)
 799 {
 800         unsigned int addr[3];
 801         int tnode, err;
 802
 803         /* PROM timer node hangs out in the top level of device siblings... */
 804         tnode = prom_finddevice("/counter-timer");
 805
 806         /* Assume if node is not present, PROM uses different tick mechanism
 807          * which we should not care about.
 808          */
 809         if (tnode == 0 || tnode == -1) {
 810                 prom_timers = (struct sun5_timer *) 0;
 811                 return;
 812         }
 813
 814         /* If PROM is really using this, it must be mapped by him. */
 815         err = prom_getproperty(tnode, "address", (char *)addr, sizeof(addr));
 816         if (err == -1) {
 817                 prom_printf("PROM does not have timer mapped, trying to continue.\n");
 818                 prom_timers = (struct sun5_timer *) 0;
 819                 return;
 820         }
 821         prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
 822 }
 823
 824 static void kill_prom_timer(void)
 825 {
 826         if (!prom_timers)
 827                 return;
 828
 829         /* Save them away for later. */
 830         prom_limit0 = prom_timers->limit0;
 831         prom_limit1 = prom_timers->limit1;
 832
 833         /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
 834          * We turn both off here just to be paranoid.
 835          */
 836         prom_timers->limit0 = 0;
 837         prom_timers->limit1 = 0;
 838
 839         /* Wheee, eat the interrupt packet too... */
 840         __asm__ __volatile__(
 841 "       mov     0x40, %%g2\n"
 842 "       ldxa    [%%g0] %0, %%g1\n"
 843 "       ldxa    [%%g2] %1, %%g1\n"
 844 "       stxa    %%g0, [%%g0] %0\n"
 845 "       membar  #Sync\n"
 846         : /* no outputs */
 847         : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
 848         : "g1", "g2");
 849 }
 850
 851 void init_irqwork_curcpu(void)
 852 {
 853         int cpu = hard_smp_processor_id();
 854
 855         memset(__irq_work + cpu, 0, sizeof(struct irq_work_struct));
 856 }
 857
 858 static void __cpuinit init_one_mondo(unsigned long *pa_ptr, unsigned long type)
 859 {
 860         register unsigned long func __asm__("%o0");
 861         register unsigned long arg0 __asm__("%o1");
 862         register unsigned long arg1 __asm__("%o2");
 863         register unsigned long arg2 __asm__("%o3");
 864         unsigned long page = get_zeroed_page(GFP_ATOMIC);
 865
 866         if (!page) {
 867                 prom_printf("SUN4V: Error, cannot allocate mondo queue.\n");
 868                 prom_halt();
 869         }
 870
 871         *pa_ptr = __pa(page);
 872
 873         func = HV_FAST_CPU_QCONF;
 874         arg0 = type;
 875         arg1 = *pa_ptr;
 876         arg2 = 128; /* XXX Implied by Niagara queue offsets. XXX */
 877         __asm__ __volatile__("ta        %8"
 878                              : "=&r" (func), "=&r" (arg0),
 879                                "=&r" (arg1), "=&r" (arg2)
 880                              : "0" (func), "1" (arg0),
 881                                "2" (arg1), "3" (arg2),
 882                                "i" (HV_FAST_TRAP));
 883
 884         if (func != HV_EOK) {
 885                 prom_printf("SUN4V: cpu_qconf(%lu) failed with error %lu\n",
 886                             type, func);
 887                 prom_halt();
 888         }
 889 }
 890
 891 /* Allocate and init the mondo queues for this cpu.  */
 892 void __cpuinit sun4v_init_mondo_queues(void)
 893 {
 894         int cpu = hard_smp_processor_id();
 895         struct trap_per_cpu *tb = &trap_block[cpu];
 896
 897         init_one_mondo(&tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO);
 898         init_one_mondo(&tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO);
 899         init_one_mondo(&tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR);
 900         init_one_mondo(&tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR);
 901 }
 902
 903 /* Only invoked on boot processor. */
 904 void __init init_IRQ(void)
 905 {
 906         map_prom_timers();
 907         kill_prom_timer();
 908         memset(&ivector_table[0], 0, sizeof(ivector_table));
 909
 910         if (tlb_type == hypervisor)
 911                 sun4v_init_mondo_queues();
 912
 913         /* We need to clear any IRQ's pending in the soft interrupt
 914          * registers, a spurious one could be left around from the
 915          * PROM timer which we just disabled.
 916          */
 917         clear_softint(get_softint());
 918
 919         /* Now that ivector table is initialized, it is safe
 920          * to receive IRQ vector traps.  We will normally take
 921          * one or two right now, in case some device PROM used
 922          * to boot us wants to speak to us.  We just ignore them.
 923          */
 924         __asm__ __volatile__("rdpr      %%pstate, %%g1\n\t"
 925                              "or        %%g1, %0, %%g1\n\t"
 926                              "wrpr      %%g1, 0x0, %%pstate"
 927                              : /* No outputs */
 928                              : "i" (PSTATE_IE)
 929                              : "g1");
 930 }
 931
 932 static struct proc_dir_entry * root_irq_dir;
 933 static struct proc_dir_entry * irq_dir [NUM_IVECS];
 934
 935 #ifdef CONFIG_SMP
 936
 937 static int irq_affinity_read_proc (char *page, char **start, off_t off,
 938                         int count, int *eof, void *data)
 939 {
 940         struct ino_bucket *bp = ivector_table + (long)data;
 941         struct irq_desc *desc = bp->irq_info;
 942         struct irqaction *ap = desc->action;
 943         cpumask_t mask;
 944         int len;
 945
 946         mask = get_smpaff_in_irqaction(ap);
 947         if (cpus_empty(mask))
 948                 mask = cpu_online_map;
 949
 950         len = cpumask_scnprintf(page, count, mask);
 951         if (count - len < 2)
 952                 return -EINVAL;
 953         len += sprintf(page + len, "\n");
 954         return len;
 955 }
 956
 957 static inline void set_intr_affinity(int irq, cpumask_t hw_aff)
 958 {
 959         struct ino_bucket *bp = ivector_table + irq;
 960         struct irq_desc *desc = bp->irq_info;
 961         struct irqaction *ap = desc->action;
 962
 963         /* Users specify affinity in terms of hw cpu ids.
 964          * As soon as we do this, handler_irq() might see and take action.
 965          */
 966         put_smpaff_in_irqaction(ap, hw_aff);
 967
 968         /* Migration is simply done by the next cpu to service this
 969          * interrupt.
 970          */
 971 }
 972
 973 static int irq_affinity_write_proc (struct file *file, const char __user *buffer,
 974                                         unsigned long count, void *data)
 975 {
 976         int irq = (long) data, full_count = count, err;
 977         cpumask_t new_value;
 978
 979         err = cpumask_parse(buffer, count, new_value);
 980
 981         /*
 982          * Do not allow disabling IRQs completely - it's a too easy
 983          * way to make the system unusable accidentally :-) At least
 984          * one online CPU still has to be targeted.
 985          */
 986         cpus_and(new_value, new_value, cpu_online_map);
 987         if (cpus_empty(new_value))
 988                 return -EINVAL;
 989
 990         set_intr_affinity(irq, new_value);
 991
 992         return full_count;
 993 }
 994
 995 #endif
 996
 997 #define MAX_NAMELEN 10
 998
 999 static void register_irq_proc (unsigned int irq)
1000 {
1001         char name [MAX_NAMELEN];
1002
1003         if (!root_irq_dir || irq_dir[irq])
1004                 return;
1005
1006         memset(name, 0, MAX_NAMELEN);
1007         sprintf(name, "%x", irq);
1008
1009         /* create /proc/irq/1234 */
1010         irq_dir[irq] = proc_mkdir(name, root_irq_dir);
1011
1012 #ifdef CONFIG_SMP
1013         /* XXX SMP affinity not supported on starfire yet. */
1014         if (this_is_starfire == 0) {
1015                 struct proc_dir_entry *entry;
1016
1017                 /* create /proc/irq/1234/smp_affinity */
1018                 entry = create_proc_entry("smp_affinity", 0600, irq_dir[irq]);
1019
1020                 if (entry) {
1021                         entry->nlink = 1;
1022                         entry->data = (void *)(long)irq;
1023                         entry->read_proc = irq_affinity_read_proc;
1024                         entry->write_proc = irq_affinity_write_proc;
1025                 }
1026         }
1027 #endif
1028 }
1029
1030 void init_irq_proc (void)
1031 {
1032         /* create /proc/irq */
1033         root_irq_dir = proc_mkdir("irq", NULL);
1034 }
1035