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   1 /* $Id: irq.c,v 1.114 2002/01/11 08:45:38 davem Exp $
   2  * irq.c: UltraSparc IRQ handling/init/registry.
   3  *
   4  * Copyright (C) 1997  David S. Miller  (davem@caip.rutgers.edu)
   5  * Copyright (C) 1998  Eddie C. Dost    (ecd@skynet.be)
   6  * Copyright (C) 1998  Jakub Jelinek    (jj@ultra.linux.cz)
   7  */
   8
   9 #include <linux/config.h>
  10 #include <linux/module.h>
  11 #include <linux/sched.h>
  12 #include <linux/ptrace.h>
  13 #include <linux/errno.h>
  14 #include <linux/kernel_stat.h>
  15 #include <linux/signal.h>
  16 #include <linux/mm.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/slab.h>
  19 #include <linux/random.h>
  20 #include <linux/init.h>
  21 #include <linux/delay.h>
  22 #include <linux/proc_fs.h>
  23 #include <linux/seq_file.h>
  24 #include <linux/bootmem.h>
  25
  26 #include <asm/ptrace.h>
  27 #include <asm/processor.h>
  28 #include <asm/atomic.h>
  29 #include <asm/system.h>
  30 #include <asm/irq.h>
  31 #include <asm/io.h>
  32 #include <asm/sbus.h>
  33 #include <asm/iommu.h>
  34 #include <asm/upa.h>
  35 #include <asm/oplib.h>
  36 #include <asm/timer.h>
  37 #include <asm/smp.h>
  38 #include <asm/starfire.h>
  39 #include <asm/uaccess.h>
  40 #include <asm/cache.h>
  41 #include <asm/cpudata.h>
  42 #include <asm/auxio.h>
  43 #include <asm/head.h>
  44
  45 #ifdef CONFIG_SMP
  46 static void distribute_irqs(void);
  47 #endif
  48
  49 /* UPA nodes send interrupt packet to UltraSparc with first data reg
  50  * value low 5 (7 on Starfire) bits holding the IRQ identifier being
  51  * delivered.  We must translate this into a non-vector IRQ so we can
  52  * set the softint on this cpu.
  53  *
  54  * To make processing these packets efficient and race free we use
  55  * an array of irq buckets below.  The interrupt vector handler in
  56  * entry.S feeds incoming packets into per-cpu pil-indexed lists.
  57  * The IVEC handler does not need to act atomically, the PIL dispatch
  58  * code uses CAS to get an atomic snapshot of the list and clear it
  59  * at the same time.
  60  */
  61
  62 struct ino_bucket ivector_table[NUM_IVECS] __attribute__ ((aligned (SMP_CACHE_BYTES)));
  63
  64 /* This has to be in the main kernel image, it cannot be
  65  * turned into per-cpu data.  The reason is that the main
  66  * kernel image is locked into the TLB and this structure
  67  * is accessed from the vectored interrupt trap handler.  If
  68  * access to this structure takes a TLB miss it could cause
  69  * the 5-level sparc v9 trap stack to overflow.
  70  */
  71 struct irq_work_struct {
  72         unsigned int    irq_worklists[16];
  73 };
  74 struct irq_work_struct __irq_work[NR_CPUS];
  75 #define irq_work(__cpu, __pil)  &(__irq_work[(__cpu)].irq_worklists[(__pil)])
  76
  77 static struct irqaction *irq_action[NR_IRQS+1];
  78
  79 /* This only synchronizes entities which modify IRQ handler
  80  * state and some selected user-level spots that want to
  81  * read things in the table.  IRQ handler processing orders
  82  * its' accesses such that no locking is needed.
  83  */
  84 static DEFINE_SPINLOCK(irq_action_lock);
  85
  86 static void register_irq_proc (unsigned int irq);
  87
  88 /*
  89  * Upper 2b of irqaction->flags holds the ino.
  90  * irqaction->mask holds the smp affinity information.
  91  */
  92 #define put_ino_in_irqaction(action, irq) \
  93         action->flags &= 0xffffffffffffUL; \
  94         if (__bucket(irq) == &pil0_dummy_bucket) \
  95                 action->flags |= 0xdeadUL << 48;  \
  96         else \
  97                 action->flags |= __irq_ino(irq) << 48;
  98 #define get_ino_in_irqaction(action)    (action->flags >> 48)
  99
 100 #define put_smpaff_in_irqaction(action, smpaff) (action)->mask = (smpaff)
 101 #define get_smpaff_in_irqaction(action)         ((action)->mask)
 102
 103 int show_interrupts(struct seq_file *p, void *v)
 104 {
 105         unsigned long flags;
 106         int i = *(loff_t *) v;
 107         struct irqaction *action;
 108 #ifdef CONFIG_SMP
 109         int j;
 110 #endif
 111
 112         spin_lock_irqsave(&irq_action_lock, flags);
 113         if (i <= NR_IRQS) {
 114                 if (!(action = *(i + irq_action)))
 115                         goto out_unlock;
 116                 seq_printf(p, "%3d: ", i);
 117 #ifndef CONFIG_SMP
 118                 seq_printf(p, "%10u ", kstat_irqs(i));
 119 #else
 120                 for (j = 0; j < NR_CPUS; j++) {
 121                         if (!cpu_online(j))
 122                                 continue;
 123                         seq_printf(p, "%10u ",
 124                                    kstat_cpu(j).irqs[i]);
 125                 }
 126 #endif
 127                 seq_printf(p, " %s:%lx", action->name,
 128                            get_ino_in_irqaction(action));
 129                 for (action = action->next; action; action = action->next) {
 130                         seq_printf(p, ", %s:%lx", action->name,
 131                                    get_ino_in_irqaction(action));
 132                 }
 133                 seq_putc(p, '\n');
 134         }
 135 out_unlock:
 136         spin_unlock_irqrestore(&irq_action_lock, flags);
 137
 138         return 0;
 139 }
 140
 141 /* Now these are always passed a true fully specified sun4u INO. */
 142 void enable_irq(unsigned int irq)
 143 {
 144         struct ino_bucket *bucket = __bucket(irq);
 145         unsigned long imap;
 146         unsigned long tid;
 147
 148         imap = bucket->imap;
 149         if (imap == 0UL)
 150                 return;
 151
 152         preempt_disable();
 153
 154         if (tlb_type == hypervisor) {
 155                 unsigned int ino = __irq_ino(irq);
 156                 int cpu = hard_smp_processor_id();
 157                 int err;
 158
 159                 err = sun4v_intr_settarget(ino, cpu);
 160                 if (err != HV_EOK)
 161                         printk("sun4v_intr_settarget(%x,%d): err(%d)\n",
 162                                ino, cpu, err);
 163                 err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
 164                 if (err != HV_EOK)
 165                         printk("sun4v_intr_setenabled(%x): err(%d)\n",
 166                                ino, err);
 167                 err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
 168                 if (err != HV_EOK)
 169                         printk("sun4v_intr_setstate(%x): "
 170                                "err(%d)\n", ino, err);
 171         } else {
 172                 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 173                         unsigned long ver;
 174
 175                         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
 176                         if ((ver >> 32) == __JALAPENO_ID ||
 177                             (ver >> 32) == __SERRANO_ID) {
 178                                 /* We set it to our JBUS ID. */
 179                                 __asm__ __volatile__("ldxa [%%g0] %1, %0"
 180                                                      : "=r" (tid)
 181                                                      : "i" (ASI_JBUS_CONFIG));
 182                                 tid = ((tid & (0x1fUL<<17)) << 9);
 183                                 tid &= IMAP_TID_JBUS;
 184                         } else {
 185                                 /* We set it to our Safari AID. */
 186                                 __asm__ __volatile__("ldxa [%%g0] %1, %0"
 187                                                      : "=r" (tid)
 188                                                      : "i"(ASI_SAFARI_CONFIG));
 189                                 tid = ((tid & (0x3ffUL<<17)) << 9);
 190                                 tid &= IMAP_AID_SAFARI;
 191                         }
 192                 } else if (this_is_starfire == 0) {
 193                         /* We set it to our UPA MID. */
 194                         __asm__ __volatile__("ldxa [%%g0] %1, %0"
 195                                              : "=r" (tid)
 196                                              : "i" (ASI_UPA_CONFIG));
 197                         tid = ((tid & UPA_CONFIG_MID) << 9);
 198                         tid &= IMAP_TID_UPA;
 199                 } else {
 200                         tid = (starfire_translate(imap,
 201                                                   smp_processor_id()) << 26);
 202                         tid &= IMAP_TID_UPA;
 203                 }
 204
 205                 /* NOTE NOTE NOTE, IGN and INO are read-only, IGN is a product
 206                  * of this SYSIO's preconfigured IGN in the SYSIO Control
 207                  * Register, the hardware just mirrors that value here.
 208                  * However for Graphics and UPA Slave devices the full
 209                  * IMAP_INR field can be set by the programmer here.
 210                  *
 211                  * Things like FFB can now be handled via the new IRQ
 212                  * mechanism.
 213                  */
 214                 upa_writel(tid | IMAP_VALID, imap);
 215         }
 216
 217         preempt_enable();
 218 }
 219
 220 /* This now gets passed true ino's as well. */
 221 void disable_irq(unsigned int irq)
 222 {
 223         struct ino_bucket *bucket = __bucket(irq);
 224         unsigned long imap;
 225
 226         imap = bucket->imap;
 227         if (imap != 0UL) {
 228                 if (tlb_type == hypervisor) {
 229                         unsigned int ino = __irq_ino(irq);
 230                         int err;
 231
 232                         err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED);
 233                         if (err != HV_EOK)
 234                                 printk("sun4v_intr_setenabled(%x): "
 235                                        "err(%d)\n", ino, err);
 236                 } else {
 237                         u32 tmp;
 238
 239                         /* NOTE: We do not want to futz with the IRQ clear registers
 240                          *       and move the state to IDLE, the SCSI code does call
 241                          *       disable_irq() to assure atomicity in the queue cmd
 242                          *       SCSI adapter driver code.  Thus we'd lose interrupts.
 243                          */
 244                         tmp = upa_readl(imap);
 245                         tmp &= ~IMAP_VALID;
 246                         upa_writel(tmp, imap);
 247                 }
 248         }
 249 }
 250
 251 /* The timer is the one "weird" interrupt which is generated by
 252  * the CPU %tick register and not by some normal vectored interrupt
 253  * source.  To handle this special case, we use this dummy INO bucket.
 254  */
 255 static struct irq_desc pil0_dummy_desc;
 256 static struct ino_bucket pil0_dummy_bucket = {
 257         .irq_info       =       &pil0_dummy_desc,
 258 };
 259
 260 static void build_irq_error(const char *msg, unsigned int ino, int pil, int inofixup,
 261                             unsigned long iclr, unsigned long imap,
 262                             struct ino_bucket *bucket)
 263 {
 264         prom_printf("IRQ: INO %04x (%d:%016lx:%016lx) --> "
 265                     "(%d:%d:%016lx:%016lx), halting...\n",
 266                     ino, bucket->pil, bucket->iclr, bucket->imap,
 267                     pil, inofixup, iclr, imap);
 268         prom_halt();
 269 }
 270
 271 unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap)
 272 {
 273         struct ino_bucket *bucket;
 274         int ino;
 275
 276         if (pil == 0) {
 277                 if (iclr != 0UL || imap != 0UL) {
 278                         prom_printf("Invalid dummy bucket for PIL0 (%lx:%lx)\n",
 279                                     iclr, imap);
 280                         prom_halt();
 281                 }
 282                 return __irq(&pil0_dummy_bucket);
 283         }
 284
 285         BUG_ON(tlb_type == hypervisor);
 286
 287         /* RULE: Both must be specified in all other cases. */
 288         if (iclr == 0UL || imap == 0UL) {
 289                 prom_printf("Invalid build_irq %d %d %016lx %016lx\n",
 290                             pil, inofixup, iclr, imap);
 291                 prom_halt();
 292         }
 293
 294         ino = (upa_readl(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
 295         if (ino > NUM_IVECS) {
 296                 prom_printf("Invalid INO %04x (%d:%d:%016lx:%016lx)\n",
 297                             ino, pil, inofixup, iclr, imap);
 298                 prom_halt();
 299         }
 300
 301         bucket = &ivector_table[ino];
 302         if (bucket->flags & IBF_ACTIVE)
 303                 build_irq_error("IRQ: Trying to build active INO bucket.\n",
 304                                 ino, pil, inofixup, iclr, imap, bucket);
 305
 306         if (bucket->irq_info) {
 307                 if (bucket->imap != imap || bucket->iclr != iclr)
 308                         build_irq_error("IRQ: Trying to reinit INO bucket.\n",
 309                                         ino, pil, inofixup, iclr, imap, bucket);
 310
 311                 goto out;
 312         }
 313
 314         bucket->irq_info = kmalloc(sizeof(struct irq_desc), GFP_ATOMIC);
 315         if (!bucket->irq_info) {
 316                 prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n");
 317                 prom_halt();
 318         }
 319         memset(bucket->irq_info, 0, sizeof(struct irq_desc));
 320
 321         /* Ok, looks good, set it up.  Don't touch the irq_chain or
 322          * the pending flag.
 323          */
 324         bucket->imap  = imap;
 325         bucket->iclr  = iclr;
 326         bucket->pil   = pil;
 327         bucket->flags = 0;
 328
 329 out:
 330         return __irq(bucket);
 331 }
 332
 333 unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino, int pil, unsigned char flags)
 334 {
 335         struct ino_bucket *bucket;
 336         unsigned long sysino;
 337
 338         sysino = sun4v_devino_to_sysino(devhandle, devino);
 339
 340         bucket = &ivector_table[sysino];
 341
 342         /* Catch accidental accesses to these things.  IMAP/ICLR handling
 343          * is done by hypervisor calls on sun4v platforms, not by direct
 344          * register accesses.
 345          */
 346         bucket->imap = ~0UL;
 347         bucket->iclr = ~0UL;
 348
 349         bucket->pil = pil;
 350         bucket->flags = flags;
 351
 352         bucket->irq_info = kmalloc(sizeof(struct irq_desc), GFP_ATOMIC);
 353         if (!bucket->irq_info) {
 354                 prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n");
 355                 prom_halt();
 356         }
 357         memset(bucket->irq_info, 0, sizeof(struct irq_desc));
 358
 359         return __irq(bucket);
 360 }
 361
 362 static void atomic_bucket_insert(struct ino_bucket *bucket)
 363 {
 364         unsigned long pstate;
 365         unsigned int *ent;
 366
 367         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
 368         __asm__ __volatile__("wrpr %0, %1, %%pstate"
 369                              : : "r" (pstate), "i" (PSTATE_IE));
 370         ent = irq_work(smp_processor_id(), bucket->pil);
 371         bucket->irq_chain = *ent;
 372         *ent = __irq(bucket);
 373         __asm__ __volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate));
 374 }
 375
 376 static int check_irq_sharing(int pil, unsigned long irqflags)
 377 {
 378         struct irqaction *action, *tmp;
 379
 380         action = *(irq_action + pil);
 381         if (action) {
 382                 if ((action->flags & SA_SHIRQ) && (irqflags & SA_SHIRQ)) {
 383                         for (tmp = action; tmp->next; tmp = tmp->next)
 384                                 ;
 385                 } else {
 386                         return -EBUSY;
 387                 }
 388         }
 389         return 0;
 390 }
 391
 392 static void append_irq_action(int pil, struct irqaction *action)
 393 {
 394         struct irqaction **pp = irq_action + pil;
 395
 396         while (*pp)
 397                 pp = &((*pp)->next);
 398         *pp = action;
 399 }
 400
 401 static struct irqaction *get_action_slot(struct ino_bucket *bucket)
 402 {
 403         struct irq_desc *desc = bucket->irq_info;
 404         int max_irq, i;
 405
 406         max_irq = 1;
 407         if (bucket->flags & IBF_PCI)
 408                 max_irq = MAX_IRQ_DESC_ACTION;
 409         for (i = 0; i < max_irq; i++) {
 410                 struct irqaction *p = &desc->action[i];
 411                 u32 mask = (1 << i);
 412
 413                 if (desc->action_active_mask & mask)
 414                         continue;
 415
 416                 desc->action_active_mask |= mask;
 417                 return p;
 418         }
 419         return NULL;
 420 }
 421
 422 int request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_regs *),
 423                 unsigned long irqflags, const char *name, void *dev_id)
 424 {
 425         struct irqaction *action;
 426         struct ino_bucket *bucket = __bucket(irq);
 427         unsigned long flags;
 428         int pending = 0;
 429
 430         if (unlikely(!handler))
 431                 return -EINVAL;
 432
 433         if (unlikely(!bucket->irq_info))
 434                 return -ENODEV;
 435
 436         if ((bucket != &pil0_dummy_bucket) && (irqflags & SA_SAMPLE_RANDOM)) {
 437                 /*
 438                  * This function might sleep, we want to call it first,
 439                  * outside of the atomic block. In SA_STATIC_ALLOC case,
 440                  * random driver's kmalloc will fail, but it is safe.
 441                  * If already initialized, random driver will not reinit.
 442                  * Yes, this might clear the entropy pool if the wrong
 443                  * driver is attempted to be loaded, without actually
 444                  * installing a new handler, but is this really a problem,
 445                  * only the sysadmin is able to do this.
 446                  */
 447                 rand_initialize_irq(irq);
 448         }
 449
 450         spin_lock_irqsave(&irq_action_lock, flags);
 451
 452         if (check_irq_sharing(bucket->pil, irqflags)) {
 453                 spin_unlock_irqrestore(&irq_action_lock, flags);
 454                 return -EBUSY;
 455         }
 456
 457         action = get_action_slot(bucket);
 458         if (!action) {
 459                 spin_unlock_irqrestore(&irq_action_lock, flags);
 460                 return -ENOMEM;
 461         }
 462
 463         bucket->flags |= IBF_ACTIVE;
 464         pending = 0;
 465         if (bucket != &pil0_dummy_bucket) {
 466                 pending = bucket->pending;
 467                 if (pending)
 468                         bucket->pending = 0;
 469         }
 470
 471         action->handler = handler;
 472         action->flags = irqflags;
 473         action->name = name;
 474         action->next = NULL;
 475         action->dev_id = dev_id;
 476         put_ino_in_irqaction(action, irq);
 477         put_smpaff_in_irqaction(action, CPU_MASK_NONE);
 478
 479         append_irq_action(bucket->pil, action);
 480
 481         enable_irq(irq);
 482
 483         /* We ate the IVEC already, this makes sure it does not get lost. */
 484         if (pending) {
 485                 atomic_bucket_insert(bucket);
 486                 set_softint(1 << bucket->pil);
 487         }
 488
 489         spin_unlock_irqrestore(&irq_action_lock, flags);
 490
 491         if (bucket != &pil0_dummy_bucket)
 492                 register_irq_proc(__irq_ino(irq));
 493
 494 #ifdef CONFIG_SMP
 495         distribute_irqs();
 496 #endif
 497         return 0;
 498 }
 499
 500 EXPORT_SYMBOL(request_irq);
 501
 502 static struct irqaction *unlink_irq_action(unsigned int irq, void *dev_id)
 503 {
 504         struct ino_bucket *bucket = __bucket(irq);
 505         struct irqaction *action, **pp;
 506
 507         pp = irq_action + bucket->pil;
 508         action = *pp;
 509         if (unlikely(!action))
 510                 return NULL;
 511
 512         if (unlikely(!action->handler)) {
 513                 printk("Freeing free IRQ %d\n", bucket->pil);
 514                 return NULL;
 515         }
 516
 517         while (action && action->dev_id != dev_id) {
 518                 pp = &action->next;
 519                 action = *pp;
 520         }
 521
 522         if (likely(action))
 523                 *pp = action->next;
 524
 525         return action;
 526 }
 527
 528 void free_irq(unsigned int irq, void *dev_id)
 529 {
 530         struct irqaction *action;
 531         struct ino_bucket *bucket;
 532         unsigned long flags;
 533
 534         spin_lock_irqsave(&irq_action_lock, flags);
 535
 536         action = unlink_irq_action(irq, dev_id);
 537
 538         spin_unlock_irqrestore(&irq_action_lock, flags);
 539
 540         if (unlikely(!action))
 541                 return;
 542
 543         synchronize_irq(irq);
 544
 545         spin_lock_irqsave(&irq_action_lock, flags);
 546
 547         bucket = __bucket(irq);
 548         if (bucket != &pil0_dummy_bucket) {
 549                 struct irq_desc *desc = bucket->irq_info;
 550                 unsigned long imap = bucket->imap;
 551                 int ent, i;
 552
 553                 for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) {
 554                         struct irqaction *p = &desc->action[i];
 555
 556                         if (p == action) {
 557                                 desc->action_active_mask &= ~(1 << i);
 558                                 break;
 559                         }
 560                 }
 561
 562                 if (!desc->action_active_mask) {
 563                         /* This unique interrupt source is now inactive. */
 564                         bucket->flags &= ~IBF_ACTIVE;
 565
 566                         /* See if any other buckets share this bucket's IMAP
 567                          * and are still active.
 568                          */
 569                         for (ent = 0; ent < NUM_IVECS; ent++) {
 570                                 struct ino_bucket *bp = &ivector_table[ent];
 571                                 if (bp != bucket        &&
 572                                     bp->imap == imap    &&
 573                                     (bp->flags & IBF_ACTIVE) != 0)
 574                                         break;
 575                         }
 576
 577                         /* Only disable when no other sub-irq levels of
 578                          * the same IMAP are active.
 579                          */
 580                         if (ent == NUM_IVECS)
 581                                 disable_irq(irq);
 582                 }
 583         }
 584
 585         spin_unlock_irqrestore(&irq_action_lock, flags);
 586 }
 587
 588 EXPORT_SYMBOL(free_irq);
 589
 590 #ifdef CONFIG_SMP
 591 void synchronize_irq(unsigned int irq)
 592 {
 593         struct ino_bucket *bucket = __bucket(irq);
 594
 595 #if 0
 596         /* The following is how I wish I could implement this.
 597          * Unfortunately the ICLR registers are read-only, you can
 598          * only write ICLR_foo values to them.  To get the current
 599          * IRQ status you would need to get at the IRQ diag registers
 600          * in the PCI/SBUS controller and the layout of those vary
 601          * from one controller to the next, sigh... -DaveM
 602          */
 603         unsigned long iclr = bucket->iclr;
 604
 605         while (1) {
 606                 u32 tmp = upa_readl(iclr);
 607
 608                 if (tmp == ICLR_TRANSMIT ||
 609                     tmp == ICLR_PENDING) {
 610                         cpu_relax();
 611                         continue;
 612                 }
 613                 break;
 614         }
 615 #else
 616         /* So we have to do this with a INPROGRESS bit just like x86.  */
 617         while (bucket->flags & IBF_INPROGRESS)
 618                 cpu_relax();
 619 #endif
 620 }
 621 #endif /* CONFIG_SMP */
 622
 623 static void process_bucket(int irq, struct ino_bucket *bp, struct pt_regs *regs)
 624 {
 625         struct irq_desc *desc = bp->irq_info;
 626         unsigned char flags = bp->flags;
 627         u32 action_mask, i;
 628         int random;
 629
 630         bp->flags |= IBF_INPROGRESS;
 631
 632         if (unlikely(!(flags & IBF_ACTIVE))) {
 633                 bp->pending = 1;
 634                 goto out;
 635         }
 636
 637         if (desc->pre_handler)
 638                 desc->pre_handler(bp,
 639                                   desc->pre_handler_arg1,
 640                                   desc->pre_handler_arg2);
 641
 642         action_mask = desc->action_active_mask;
 643         random = 0;
 644         for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) {
 645                 struct irqaction *p = &desc->action[i];
 646                 u32 mask = (1 << i);
 647
 648                 if (!(action_mask & mask))
 649                         continue;
 650
 651                 action_mask &= ~mask;
 652
 653                 if (p->handler(__irq(bp), p->dev_id, regs) == IRQ_HANDLED)
 654                         random |= p->flags;
 655
 656                 if (!action_mask)
 657                         break;
 658         }
 659         if (bp->pil != 0) {
 660                 if (tlb_type == hypervisor) {
 661                         unsigned int ino = __irq_ino(bp);
 662                         int err;
 663
 664                         err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
 665                         if (err != HV_EOK)
 666                                 printk("sun4v_intr_setstate(%x): "
 667                                        "err(%d)\n", ino, err);
 668                 } else {
 669                         upa_writel(ICLR_IDLE, bp->iclr);
 670                 }
 671
 672                 /* Test and add entropy */
 673                 if (random & SA_SAMPLE_RANDOM)
 674                         add_interrupt_randomness(irq);
 675         }
 676 out:
 677         bp->flags &= ~IBF_INPROGRESS;
 678 }
 679
 680 void handler_irq(int irq, struct pt_regs *regs)
 681 {
 682         struct ino_bucket *bp;
 683         int cpu = smp_processor_id();
 684
 685 #ifndef CONFIG_SMP
 686         /*
 687          * Check for TICK_INT on level 14 softint.
 688          */
 689         {
 690                 unsigned long clr_mask = 1 << irq;
 691                 unsigned long tick_mask = tick_ops->softint_mask;
 692
 693                 if ((irq == 14) && (get_softint() & tick_mask)) {
 694                         irq = 0;
 695                         clr_mask = tick_mask;
 696                 }
 697                 clear_softint(clr_mask);
 698         }
 699 #else
 700         clear_softint(1 << irq);
 701 #endif
 702
 703         irq_enter();
 704         kstat_this_cpu.irqs[irq]++;
 705
 706         /* Sliiiick... */
 707 #ifndef CONFIG_SMP
 708         bp = ((irq != 0) ?
 709               __bucket(xchg32(irq_work(cpu, irq), 0)) :
 710               &pil0_dummy_bucket);
 711 #else
 712         bp = __bucket(xchg32(irq_work(cpu, irq), 0));
 713 #endif
 714         while (bp) {
 715                 struct ino_bucket *nbp = __bucket(bp->irq_chain);
 716
 717                 bp->irq_chain = 0;
 718                 process_bucket(irq, bp, regs);
 719                 bp = nbp;
 720         }
 721         irq_exit();
 722 }
 723
 724 #ifdef CONFIG_BLK_DEV_FD
 725 extern irqreturn_t floppy_interrupt(int, void *, struct pt_regs *);;
 726
 727 /* XXX No easy way to include asm/floppy.h XXX */
 728 extern unsigned char *pdma_vaddr;
 729 extern unsigned long pdma_size;
 730 extern volatile int doing_pdma;
 731 extern unsigned long fdc_status;
 732
 733 irqreturn_t sparc_floppy_irq(int irq, void *dev_cookie, struct pt_regs *regs)
 734 {
 735         if (likely(doing_pdma)) {
 736                 void __iomem *stat = (void __iomem *) fdc_status;
 737                 unsigned char *vaddr = pdma_vaddr;
 738                 unsigned long size = pdma_size;
 739                 u8 val;
 740
 741                 while (size) {
 742                         val = readb(stat);
 743                         if (unlikely(!(val & 0x80))) {
 744                                 pdma_vaddr = vaddr;
 745                                 pdma_size = size;
 746                                 return IRQ_HANDLED;
 747                         }
 748                         if (unlikely(!(val & 0x20))) {
 749                                 pdma_vaddr = vaddr;
 750                                 pdma_size = size;
 751                                 doing_pdma = 0;
 752                                 goto main_interrupt;
 753                         }
 754                         if (val & 0x40) {
 755                                 /* read */
 756                                 *vaddr++ = readb(stat + 1);
 757                         } else {
 758                                 unsigned char data = *vaddr++;
 759
 760                                 /* write */
 761                                 writeb(data, stat + 1);
 762                         }
 763                         size--;
 764                 }
 765
 766                 pdma_vaddr = vaddr;
 767                 pdma_size = size;
 768
 769                 /* Send Terminal Count pulse to floppy controller. */
 770                 val = readb(auxio_register);
 771                 val |= AUXIO_AUX1_FTCNT;
 772                 writeb(val, auxio_register);
 773                 val &= ~AUXIO_AUX1_FTCNT;
 774                 writeb(val, auxio_register);
 775
 776                 doing_pdma = 0;
 777         }
 778
 779 main_interrupt:
 780         return floppy_interrupt(irq, dev_cookie, regs);
 781 }
 782 EXPORT_SYMBOL(sparc_floppy_irq);
 783 #endif
 784
 785 /* We really don't need these at all on the Sparc.  We only have
 786  * stubs here because they are exported to modules.
 787  */
 788 unsigned long probe_irq_on(void)
 789 {
 790         return 0;
 791 }
 792
 793 EXPORT_SYMBOL(probe_irq_on);
 794
 795 int probe_irq_off(unsigned long mask)
 796 {
 797         return 0;
 798 }
 799
 800 EXPORT_SYMBOL(probe_irq_off);
 801
 802 #ifdef CONFIG_SMP
 803 static int retarget_one_irq(struct irqaction *p, int goal_cpu)
 804 {
 805         struct ino_bucket *bucket = get_ino_in_irqaction(p) + ivector_table;
 806         unsigned long imap = bucket->imap;
 807
 808         while (!cpu_online(goal_cpu)) {
 809                 if (++goal_cpu >= NR_CPUS)
 810                         goal_cpu = 0;
 811         }
 812
 813         if (tlb_type == hypervisor) {
 814                 unsigned int ino = __irq_ino(bucket);
 815
 816                 sun4v_intr_settarget(ino, goal_cpu);
 817                 sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
 818         } else {
 819                 unsigned int tid;
 820
 821                 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 822                         tid = goal_cpu << 26;
 823                         tid &= IMAP_AID_SAFARI;
 824                 } else if (this_is_starfire == 0) {
 825                         tid = goal_cpu << 26;
 826                         tid &= IMAP_TID_UPA;
 827                 } else {
 828                         tid = (starfire_translate(imap, goal_cpu) << 26);
 829                         tid &= IMAP_TID_UPA;
 830                 }
 831                 upa_writel(tid | IMAP_VALID, imap);
 832         }
 833
 834         do {
 835                 if (++goal_cpu >= NR_CPUS)
 836                         goal_cpu = 0;
 837         } while (!cpu_online(goal_cpu));
 838
 839         return goal_cpu;
 840 }
 841
 842 /* Called from request_irq. */
 843 static void distribute_irqs(void)
 844 {
 845         unsigned long flags;
 846         int cpu, level;
 847
 848         spin_lock_irqsave(&irq_action_lock, flags);
 849         cpu = 0;
 850
 851         /*
 852          * Skip the timer at [0], and very rare error/power intrs at [15].
 853          * Also level [12], it causes problems on Ex000 systems.
 854          */
 855         for (level = 1; level < NR_IRQS; level++) {
 856                 struct irqaction *p = irq_action[level];
 857
 858                 if (level == 12)
 859                         continue;
 860
 861                 while(p) {
 862                         cpu = retarget_one_irq(p, cpu);
 863                         p = p->next;
 864                 }
 865         }
 866         spin_unlock_irqrestore(&irq_action_lock, flags);
 867 }
 868 #endif
 869
 870 struct sun5_timer {
 871         u64     count0;
 872         u64     limit0;
 873         u64     count1;
 874         u64     limit1;
 875 };
 876
 877 static struct sun5_timer *prom_timers;
 878 static u64 prom_limit0, prom_limit1;
 879
 880 static void map_prom_timers(void)
 881 {
 882         unsigned int addr[3];
 883         int tnode, err;
 884
 885         /* PROM timer node hangs out in the top level of device siblings... */
 886         tnode = prom_finddevice("/counter-timer");
 887
 888         /* Assume if node is not present, PROM uses different tick mechanism
 889          * which we should not care about.
 890          */
 891         if (tnode == 0 || tnode == -1) {
 892                 prom_timers = (struct sun5_timer *) 0;
 893                 return;
 894         }
 895
 896         /* If PROM is really using this, it must be mapped by him. */
 897         err = prom_getproperty(tnode, "address", (char *)addr, sizeof(addr));
 898         if (err == -1) {
 899                 prom_printf("PROM does not have timer mapped, trying to continue.\n");
 900                 prom_timers = (struct sun5_timer *) 0;
 901                 return;
 902         }
 903         prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
 904 }
 905
 906 static void kill_prom_timer(void)
 907 {
 908         if (!prom_timers)
 909                 return;
 910
 911         /* Save them away for later. */
 912         prom_limit0 = prom_timers->limit0;
 913         prom_limit1 = prom_timers->limit1;
 914
 915         /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
 916          * We turn both off here just to be paranoid.
 917          */
 918         prom_timers->limit0 = 0;
 919         prom_timers->limit1 = 0;
 920
 921         /* Wheee, eat the interrupt packet too... */
 922         __asm__ __volatile__(
 923 "       mov     0x40, %%g2\n"
 924 "       ldxa    [%%g0] %0, %%g1\n"
 925 "       ldxa    [%%g2] %1, %%g1\n"
 926 "       stxa    %%g0, [%%g0] %0\n"
 927 "       membar  #Sync\n"
 928         : /* no outputs */
 929         : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
 930         : "g1", "g2");
 931 }
 932
 933 void init_irqwork_curcpu(void)
 934 {
 935         int cpu = hard_smp_processor_id();
 936
 937         memset(__irq_work + cpu, 0, sizeof(struct irq_work_struct));
 938 }
 939
 940 static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type)
 941 {
 942         register unsigned long func __asm__("%o5");
 943         register unsigned long arg0 __asm__("%o0");
 944         register unsigned long arg1 __asm__("%o1");
 945         register unsigned long arg2 __asm__("%o2");
 946
 947         func = HV_FAST_CPU_QCONF;
 948         arg0 = type;
 949         arg1 = paddr;
 950         arg2 = 128; /* XXX Implied by Niagara queue offsets. XXX */
 951         __asm__ __volatile__("ta        %8"
 952                              : "=&r" (func), "=&r" (arg0),
 953                                "=&r" (arg1), "=&r" (arg2)
 954                              : "0" (func), "1" (arg0),
 955                                "2" (arg1), "3" (arg2),
 956                                "i" (HV_FAST_TRAP));
 957
 958         if (arg0 != HV_EOK) {
 959                 prom_printf("SUN4V: cpu_qconf(%lu) failed with error %lu\n",
 960                             type, func);
 961                 prom_halt();
 962         }
 963 }
 964
 965 static void __cpuinit sun4v_register_mondo_queues(int this_cpu)
 966 {
 967         struct trap_per_cpu *tb = &trap_block[this_cpu];
 968
 969         register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO);
 970         register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO);
 971         register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR);
 972         register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR);
 973 }
 974
 975 static void __cpuinit alloc_one_mondo(unsigned long *pa_ptr, int use_bootmem)
 976 {
 977         void *page;
 978
 979         if (use_bootmem)
 980                 page = alloc_bootmem_low_pages(PAGE_SIZE);
 981         else
 982                 page = (void *) get_zeroed_page(GFP_ATOMIC);
 983
 984         if (!page) {
 985                 prom_printf("SUN4V: Error, cannot allocate mondo queue.\n");
 986                 prom_halt();
 987         }
 988
 989         *pa_ptr = __pa(page);
 990 }
 991
 992 static void __cpuinit alloc_one_kbuf(unsigned long *pa_ptr, int use_bootmem)
 993 {
 994         void *page;
 995
 996         if (use_bootmem)
 997                 page = alloc_bootmem_low_pages(PAGE_SIZE);
 998         else
 999                 page = (void *) get_zeroed_page(GFP_ATOMIC);
1000
1001         if (!page) {
1002                 prom_printf("SUN4V: Error, cannot allocate kbuf page.\n");
1003                 prom_halt();
1004         }
1005
1006         *pa_ptr = __pa(page);
1007 }
1008
1009 static void __cpuinit init_cpu_send_mondo_info(struct trap_per_cpu *tb, int use_bootmem)
1010 {
1011 #ifdef CONFIG_SMP
1012         void *page;
1013
1014         BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64));
1015
1016         if (use_bootmem)
1017                 page = alloc_bootmem_low_pages(PAGE_SIZE);
1018         else
1019                 page = (void *) get_zeroed_page(GFP_ATOMIC);
1020
1021         if (!page) {
1022                 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
1023                 prom_halt();
1024         }
1025
1026         tb->cpu_mondo_block_pa = __pa(page);
1027         tb->cpu_list_pa = __pa(page + 64);
1028 #endif
1029 }
1030
1031 /* Allocate and register the mondo and error queues for this cpu.  */
1032 void __cpuinit sun4v_init_mondo_queues(int use_bootmem)
1033 {
1034         int cpu = hard_smp_processor_id();
1035         struct trap_per_cpu *tb = &trap_block[cpu];
1036
1037         alloc_one_mondo(&tb->cpu_mondo_pa, use_bootmem);
1038         alloc_one_mondo(&tb->dev_mondo_pa, use_bootmem);
1039         alloc_one_mondo(&tb->resum_mondo_pa, use_bootmem);
1040         alloc_one_kbuf(&tb->resum_kernel_buf_pa, use_bootmem);
1041         alloc_one_mondo(&tb->nonresum_mondo_pa, use_bootmem);
1042         alloc_one_kbuf(&tb->nonresum_kernel_buf_pa, use_bootmem);
1043
1044         init_cpu_send_mondo_info(tb, use_bootmem);
1045
1046         sun4v_register_mondo_queues(cpu);
1047 }
1048
1049 /* Only invoked on boot processor. */
1050 void __init init_IRQ(void)
1051 {
1052         map_prom_timers();
1053         kill_prom_timer();
1054         memset(&ivector_table[0], 0, sizeof(ivector_table));
1055
1056         if (tlb_type == hypervisor)
1057                 sun4v_init_mondo_queues(1);
1058
1059         /* We need to clear any IRQ's pending in the soft interrupt
1060          * registers, a spurious one could be left around from the
1061          * PROM timer which we just disabled.
1062          */
1063         clear_softint(get_softint());
1064
1065         /* Now that ivector table is initialized, it is safe
1066          * to receive IRQ vector traps.  We will normally take
1067          * one or two right now, in case some device PROM used
1068          * to boot us wants to speak to us.  We just ignore them.
1069          */
1070         __asm__ __volatile__("rdpr      %%pstate, %%g1\n\t"
1071                              "or        %%g1, %0, %%g1\n\t"
1072                              "wrpr      %%g1, 0x0, %%pstate"
1073                              : /* No outputs */
1074                              : "i" (PSTATE_IE)
1075                              : "g1");
1076 }
1077
1078 static struct proc_dir_entry * root_irq_dir;
1079 static struct proc_dir_entry * irq_dir [NUM_IVECS];
1080
1081 #ifdef CONFIG_SMP
1082
1083 static int irq_affinity_read_proc (char *page, char **start, off_t off,
1084                         int count, int *eof, void *data)
1085 {
1086         struct ino_bucket *bp = ivector_table + (long)data;
1087         struct irq_desc *desc = bp->irq_info;
1088         struct irqaction *ap = desc->action;
1089         cpumask_t mask;
1090         int len;
1091
1092         mask = get_smpaff_in_irqaction(ap);
1093         if (cpus_empty(mask))
1094                 mask = cpu_online_map;
1095
1096         len = cpumask_scnprintf(page, count, mask);
1097         if (count - len < 2)
1098                 return -EINVAL;
1099         len += sprintf(page + len, "\n");
1100         return len;
1101 }
1102
1103 static inline void set_intr_affinity(int irq, cpumask_t hw_aff)
1104 {
1105         struct ino_bucket *bp = ivector_table + irq;
1106         struct irq_desc *desc = bp->irq_info;
1107         struct irqaction *ap = desc->action;
1108
1109         /* Users specify affinity in terms of hw cpu ids.
1110          * As soon as we do this, handler_irq() might see and take action.
1111          */
1112         put_smpaff_in_irqaction(ap, hw_aff);
1113
1114         /* Migration is simply done by the next cpu to service this
1115          * interrupt.
1116          */
1117 }
1118
1119 static int irq_affinity_write_proc (struct file *file, const char __user *buffer,
1120                                         unsigned long count, void *data)
1121 {
1122         int irq = (long) data, full_count = count, err;
1123         cpumask_t new_value;
1124
1125         err = cpumask_parse(buffer, count, new_value);
1126
1127         /*
1128          * Do not allow disabling IRQs completely - it's a too easy
1129          * way to make the system unusable accidentally :-) At least
1130          * one online CPU still has to be targeted.
1131          */
1132         cpus_and(new_value, new_value, cpu_online_map);
1133         if (cpus_empty(new_value))
1134                 return -EINVAL;
1135
1136         set_intr_affinity(irq, new_value);
1137
1138         return full_count;
1139 }
1140
1141 #endif
1142
1143 #define MAX_NAMELEN 10
1144
1145 static void register_irq_proc (unsigned int irq)
1146 {
1147         char name [MAX_NAMELEN];
1148
1149         if (!root_irq_dir || irq_dir[irq])
1150                 return;
1151
1152         memset(name, 0, MAX_NAMELEN);
1153         sprintf(name, "%x", irq);
1154
1155         /* create /proc/irq/1234 */
1156         irq_dir[irq] = proc_mkdir(name, root_irq_dir);
1157
1158 #ifdef CONFIG_SMP
1159         /* XXX SMP affinity not supported on starfire yet. */
1160         if (this_is_starfire == 0) {
1161                 struct proc_dir_entry *entry;
1162
1163                 /* create /proc/irq/1234/smp_affinity */
1164                 entry = create_proc_entry("smp_affinity", 0600, irq_dir[irq]);
1165
1166                 if (entry) {
1167                         entry->nlink = 1;
1168                         entry->data = (void *)(long)irq;
1169                         entry->read_proc = irq_affinity_read_proc;
1170                         entry->write_proc = irq_affinity_write_proc;
1171                 }
1172         }
1173 #endif
1174 }
1175
1176 void init_irq_proc (void)
1177 {
1178         /* create /proc/irq */
1179         root_irq_dir = proc_mkdir("irq", NULL);
1180 }
1181