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   1 /* $Id: irq.c,v 1.114 2002/01/11 08:45:38 davem Exp $
   2  * irq.c: UltraSparc IRQ handling/init/registry.
   3  *
   4  * Copyright (C) 1997  David S. Miller  (davem@caip.rutgers.edu)
   5  * Copyright (C) 1998  Eddie C. Dost    (ecd@skynet.be)
   6  * Copyright (C) 1998  Jakub Jelinek    (jj@ultra.linux.cz)
   7  */
   8
   9 #include <linux/config.h>
  10 #include <linux/module.h>
  11 #include <linux/sched.h>
  12 #include <linux/ptrace.h>
  13 #include <linux/errno.h>
  14 #include <linux/kernel_stat.h>
  15 #include <linux/signal.h>
  16 #include <linux/mm.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/slab.h>
  19 #include <linux/random.h>
  20 #include <linux/init.h>
  21 #include <linux/delay.h>
  22 #include <linux/proc_fs.h>
  23 #include <linux/seq_file.h>
  24
  25 #include <asm/ptrace.h>
  26 #include <asm/processor.h>
  27 #include <asm/atomic.h>
  28 #include <asm/system.h>
  29 #include <asm/irq.h>
  30 #include <asm/io.h>
  31 #include <asm/sbus.h>
  32 #include <asm/iommu.h>
  33 #include <asm/upa.h>
  34 #include <asm/oplib.h>
  35 #include <asm/timer.h>
  36 #include <asm/smp.h>
  37 #include <asm/starfire.h>
  38 #include <asm/uaccess.h>
  39 #include <asm/cache.h>
  40 #include <asm/cpudata.h>
  41 #include <asm/auxio.h>
  42 #include <asm/head.h>
  43
  44 #ifdef CONFIG_SMP
  45 static void distribute_irqs(void);
  46 #endif
  47
  48 /* UPA nodes send interrupt packet to UltraSparc with first data reg
  49  * value low 5 (7 on Starfire) bits holding the IRQ identifier being
  50  * delivered.  We must translate this into a non-vector IRQ so we can
  51  * set the softint on this cpu.
  52  *
  53  * To make processing these packets efficient and race free we use
  54  * an array of irq buckets below.  The interrupt vector handler in
  55  * entry.S feeds incoming packets into per-cpu pil-indexed lists.
  56  * The IVEC handler does not need to act atomically, the PIL dispatch
  57  * code uses CAS to get an atomic snapshot of the list and clear it
  58  * at the same time.
  59  */
  60
  61 struct ino_bucket ivector_table[NUM_IVECS] __attribute__ ((aligned (SMP_CACHE_BYTES)));
  62
  63 /* This has to be in the main kernel image, it cannot be
  64  * turned into per-cpu data.  The reason is that the main
  65  * kernel image is locked into the TLB and this structure
  66  * is accessed from the vectored interrupt trap handler.  If
  67  * access to this structure takes a TLB miss it could cause
  68  * the 5-level sparc v9 trap stack to overflow.
  69  */
  70 struct irq_work_struct {
  71         unsigned int    irq_worklists[16];
  72 };
  73 struct irq_work_struct __irq_work[NR_CPUS];
  74 #define irq_work(__cpu, __pil)  &(__irq_work[(__cpu)].irq_worklists[(__pil)])
  75
  76 static struct irqaction *irq_action[NR_IRQS+1];
  77
  78 /* This only synchronizes entities which modify IRQ handler
  79  * state and some selected user-level spots that want to
  80  * read things in the table.  IRQ handler processing orders
  81  * its' accesses such that no locking is needed.
  82  */
  83 static DEFINE_SPINLOCK(irq_action_lock);
  84
  85 static void register_irq_proc (unsigned int irq);
  86
  87 /*
  88  * Upper 2b of irqaction->flags holds the ino.
  89  * irqaction->mask holds the smp affinity information.
  90  */
  91 #define put_ino_in_irqaction(action, irq) \
  92         action->flags &= 0xffffffffffffUL; \
  93         if (__bucket(irq) == &pil0_dummy_bucket) \
  94                 action->flags |= 0xdeadUL << 48;  \
  95         else \
  96                 action->flags |= __irq_ino(irq) << 48;
  97 #define get_ino_in_irqaction(action)    (action->flags >> 48)
  98
  99 #define put_smpaff_in_irqaction(action, smpaff) (action)->mask = (smpaff)
 100 #define get_smpaff_in_irqaction(action)         ((action)->mask)
 101
 102 int show_interrupts(struct seq_file *p, void *v)
 103 {
 104         unsigned long flags;
 105         int i = *(loff_t *) v;
 106         struct irqaction *action;
 107 #ifdef CONFIG_SMP
 108         int j;
 109 #endif
 110
 111         spin_lock_irqsave(&irq_action_lock, flags);
 112         if (i <= NR_IRQS) {
 113                 if (!(action = *(i + irq_action)))
 114                         goto out_unlock;
 115                 seq_printf(p, "%3d: ", i);
 116 #ifndef CONFIG_SMP
 117                 seq_printf(p, "%10u ", kstat_irqs(i));
 118 #else
 119                 for (j = 0; j < NR_CPUS; j++) {
 120                         if (!cpu_online(j))
 121                                 continue;
 122                         seq_printf(p, "%10u ",
 123                                    kstat_cpu(j).irqs[i]);
 124                 }
 125 #endif
 126                 seq_printf(p, " %s:%lx", action->name,
 127                            get_ino_in_irqaction(action));
 128                 for (action = action->next; action; action = action->next) {
 129                         seq_printf(p, ", %s:%lx", action->name,
 130                                    get_ino_in_irqaction(action));
 131                 }
 132                 seq_putc(p, '\n');
 133         }
 134 out_unlock:
 135         spin_unlock_irqrestore(&irq_action_lock, flags);
 136
 137         return 0;
 138 }
 139
 140 /* Now these are always passed a true fully specified sun4u INO. */
 141 void enable_irq(unsigned int irq)
 142 {
 143         struct ino_bucket *bucket = __bucket(irq);
 144         unsigned long imap;
 145         unsigned long tid;
 146
 147         imap = bucket->imap;
 148         if (imap == 0UL)
 149                 return;
 150
 151         preempt_disable();
 152
 153         if (tlb_type == hypervisor) {
 154                 /* XXX SUN4V: implement me... XXX */
 155         } else {
 156                 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 157                         unsigned long ver;
 158
 159                         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
 160                         if ((ver >> 32) == __JALAPENO_ID ||
 161                             (ver >> 32) == __SERRANO_ID) {
 162                                 /* We set it to our JBUS ID. */
 163                                 __asm__ __volatile__("ldxa [%%g0] %1, %0"
 164                                                      : "=r" (tid)
 165                                                      : "i" (ASI_JBUS_CONFIG));
 166                                 tid = ((tid & (0x1fUL<<17)) << 9);
 167                                 tid &= IMAP_TID_JBUS;
 168                         } else {
 169                                 /* We set it to our Safari AID. */
 170                                 __asm__ __volatile__("ldxa [%%g0] %1, %0"
 171                                                      : "=r" (tid)
 172                                                      : "i"(ASI_SAFARI_CONFIG));
 173                                 tid = ((tid & (0x3ffUL<<17)) << 9);
 174                                 tid &= IMAP_AID_SAFARI;
 175                         }
 176                 } else if (this_is_starfire == 0) {
 177                         /* We set it to our UPA MID. */
 178                         __asm__ __volatile__("ldxa [%%g0] %1, %0"
 179                                              : "=r" (tid)
 180                                              : "i" (ASI_UPA_CONFIG));
 181                         tid = ((tid & UPA_CONFIG_MID) << 9);
 182                         tid &= IMAP_TID_UPA;
 183                 } else {
 184                         tid = (starfire_translate(imap,
 185                                                   smp_processor_id()) << 26);
 186                         tid &= IMAP_TID_UPA;
 187                 }
 188
 189                 /* NOTE NOTE NOTE, IGN and INO are read-only, IGN is a product
 190                  * of this SYSIO's preconfigured IGN in the SYSIO Control
 191                  * Register, the hardware just mirrors that value here.
 192                  * However for Graphics and UPA Slave devices the full
 193                  * IMAP_INR field can be set by the programmer here.
 194                  *
 195                  * Things like FFB can now be handled via the new IRQ
 196                  * mechanism.
 197                  */
 198                 upa_writel(tid | IMAP_VALID, imap);
 199         }
 200
 201         preempt_enable();
 202 }
 203
 204 /* This now gets passed true ino's as well. */
 205 void disable_irq(unsigned int irq)
 206 {
 207         struct ino_bucket *bucket = __bucket(irq);
 208         unsigned long imap;
 209
 210         imap = bucket->imap;
 211         if (imap != 0UL) {
 212                 u32 tmp;
 213
 214                 /* NOTE: We do not want to futz with the IRQ clear registers
 215                  *       and move the state to IDLE, the SCSI code does call
 216                  *       disable_irq() to assure atomicity in the queue cmd
 217                  *       SCSI adapter driver code.  Thus we'd lose interrupts.
 218                  */
 219                 tmp = upa_readl(imap);
 220                 tmp &= ~IMAP_VALID;
 221                 upa_writel(tmp, imap);
 222         }
 223 }
 224
 225 /* The timer is the one "weird" interrupt which is generated by
 226  * the CPU %tick register and not by some normal vectored interrupt
 227  * source.  To handle this special case, we use this dummy INO bucket.
 228  */
 229 static struct irq_desc pil0_dummy_desc;
 230 static struct ino_bucket pil0_dummy_bucket = {
 231         .irq_info       =       &pil0_dummy_desc,
 232 };
 233
 234 static void build_irq_error(const char *msg, unsigned int ino, int pil, int inofixup,
 235                             unsigned long iclr, unsigned long imap,
 236                             struct ino_bucket *bucket)
 237 {
 238         prom_printf("IRQ: INO %04x (%d:%016lx:%016lx) --> "
 239                     "(%d:%d:%016lx:%016lx), halting...\n",
 240                     ino, bucket->pil, bucket->iclr, bucket->imap,
 241                     pil, inofixup, iclr, imap);
 242         prom_halt();
 243 }
 244
 245 unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap)
 246 {
 247         struct ino_bucket *bucket;
 248         int ino;
 249
 250         if (pil == 0) {
 251                 if (iclr != 0UL || imap != 0UL) {
 252                         prom_printf("Invalid dummy bucket for PIL0 (%lx:%lx)\n",
 253                                     iclr, imap);
 254                         prom_halt();
 255                 }
 256                 return __irq(&pil0_dummy_bucket);
 257         }
 258
 259         /* RULE: Both must be specified in all other cases. */
 260         if (iclr == 0UL || imap == 0UL) {
 261                 prom_printf("Invalid build_irq %d %d %016lx %016lx\n",
 262                             pil, inofixup, iclr, imap);
 263                 prom_halt();
 264         }
 265
 266         ino = (upa_readl(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
 267         if (ino > NUM_IVECS) {
 268                 prom_printf("Invalid INO %04x (%d:%d:%016lx:%016lx)\n",
 269                             ino, pil, inofixup, iclr, imap);
 270                 prom_halt();
 271         }
 272
 273         bucket = &ivector_table[ino];
 274         if (bucket->flags & IBF_ACTIVE)
 275                 build_irq_error("IRQ: Trying to build active INO bucket.\n",
 276                                 ino, pil, inofixup, iclr, imap, bucket);
 277
 278         if (bucket->irq_info) {
 279                 if (bucket->imap != imap || bucket->iclr != iclr)
 280                         build_irq_error("IRQ: Trying to reinit INO bucket.\n",
 281                                         ino, pil, inofixup, iclr, imap, bucket);
 282
 283                 goto out;
 284         }
 285
 286         bucket->irq_info = kmalloc(sizeof(struct irq_desc), GFP_ATOMIC);
 287         if (!bucket->irq_info) {
 288                 prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n");
 289                 prom_halt();
 290         }
 291         memset(bucket->irq_info, 0, sizeof(struct irq_desc));
 292
 293         /* Ok, looks good, set it up.  Don't touch the irq_chain or
 294          * the pending flag.
 295          */
 296         bucket->imap  = imap;
 297         bucket->iclr  = iclr;
 298         bucket->pil   = pil;
 299         bucket->flags = 0;
 300
 301 out:
 302         return __irq(bucket);
 303 }
 304
 305 static void atomic_bucket_insert(struct ino_bucket *bucket)
 306 {
 307         unsigned long pstate;
 308         unsigned int *ent;
 309
 310         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
 311         __asm__ __volatile__("wrpr %0, %1, %%pstate"
 312                              : : "r" (pstate), "i" (PSTATE_IE));
 313         ent = irq_work(smp_processor_id(), bucket->pil);
 314         bucket->irq_chain = *ent;
 315         *ent = __irq(bucket);
 316         __asm__ __volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate));
 317 }
 318
 319 static int check_irq_sharing(int pil, unsigned long irqflags)
 320 {
 321         struct irqaction *action, *tmp;
 322
 323         action = *(irq_action + pil);
 324         if (action) {
 325                 if ((action->flags & SA_SHIRQ) && (irqflags & SA_SHIRQ)) {
 326                         for (tmp = action; tmp->next; tmp = tmp->next)
 327                                 ;
 328                 } else {
 329                         return -EBUSY;
 330                 }
 331         }
 332         return 0;
 333 }
 334
 335 static void append_irq_action(int pil, struct irqaction *action)
 336 {
 337         struct irqaction **pp = irq_action + pil;
 338
 339         while (*pp)
 340                 pp = &((*pp)->next);
 341         *pp = action;
 342 }
 343
 344 static struct irqaction *get_action_slot(struct ino_bucket *bucket)
 345 {
 346         struct irq_desc *desc = bucket->irq_info;
 347         int max_irq, i;
 348
 349         max_irq = 1;
 350         if (bucket->flags & IBF_PCI)
 351                 max_irq = MAX_IRQ_DESC_ACTION;
 352         for (i = 0; i < max_irq; i++) {
 353                 struct irqaction *p = &desc->action[i];
 354                 u32 mask = (1 << i);
 355
 356                 if (desc->action_active_mask & mask)
 357                         continue;
 358
 359                 desc->action_active_mask |= mask;
 360                 return p;
 361         }
 362         return NULL;
 363 }
 364
 365 int request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_regs *),
 366                 unsigned long irqflags, const char *name, void *dev_id)
 367 {
 368         struct irqaction *action;
 369         struct ino_bucket *bucket = __bucket(irq);
 370         unsigned long flags;
 371         int pending = 0;
 372
 373         if (unlikely(!handler))
 374                 return -EINVAL;
 375
 376         if (unlikely(!bucket->irq_info))
 377                 return -ENODEV;
 378
 379         if ((bucket != &pil0_dummy_bucket) && (irqflags & SA_SAMPLE_RANDOM)) {
 380                 /*
 381                  * This function might sleep, we want to call it first,
 382                  * outside of the atomic block. In SA_STATIC_ALLOC case,
 383                  * random driver's kmalloc will fail, but it is safe.
 384                  * If already initialized, random driver will not reinit.
 385                  * Yes, this might clear the entropy pool if the wrong
 386                  * driver is attempted to be loaded, without actually
 387                  * installing a new handler, but is this really a problem,
 388                  * only the sysadmin is able to do this.
 389                  */
 390                 rand_initialize_irq(irq);
 391         }
 392
 393         spin_lock_irqsave(&irq_action_lock, flags);
 394
 395         if (check_irq_sharing(bucket->pil, irqflags)) {
 396                 spin_unlock_irqrestore(&irq_action_lock, flags);
 397                 return -EBUSY;
 398         }
 399
 400         action = get_action_slot(bucket);
 401         if (!action) {
 402                 spin_unlock_irqrestore(&irq_action_lock, flags);
 403                 return -ENOMEM;
 404         }
 405
 406         bucket->flags |= IBF_ACTIVE;
 407         pending = 0;
 408         if (bucket != &pil0_dummy_bucket) {
 409                 pending = bucket->pending;
 410                 if (pending)
 411                         bucket->pending = 0;
 412         }
 413
 414         action->handler = handler;
 415         action->flags = irqflags;
 416         action->name = name;
 417         action->next = NULL;
 418         action->dev_id = dev_id;
 419         put_ino_in_irqaction(action, irq);
 420         put_smpaff_in_irqaction(action, CPU_MASK_NONE);
 421
 422         append_irq_action(bucket->pil, action);
 423
 424         enable_irq(irq);
 425
 426         /* We ate the IVEC already, this makes sure it does not get lost. */
 427         if (pending) {
 428                 atomic_bucket_insert(bucket);
 429                 set_softint(1 << bucket->pil);
 430         }
 431
 432         spin_unlock_irqrestore(&irq_action_lock, flags);
 433
 434         if (bucket != &pil0_dummy_bucket)
 435                 register_irq_proc(__irq_ino(irq));
 436
 437 #ifdef CONFIG_SMP
 438         distribute_irqs();
 439 #endif
 440         return 0;
 441 }
 442
 443 EXPORT_SYMBOL(request_irq);
 444
 445 static struct irqaction *unlink_irq_action(unsigned int irq, void *dev_id)
 446 {
 447         struct ino_bucket *bucket = __bucket(irq);
 448         struct irqaction *action, **pp;
 449
 450         pp = irq_action + bucket->pil;
 451         action = *pp;
 452         if (unlikely(!action))
 453                 return NULL;
 454
 455         if (unlikely(!action->handler)) {
 456                 printk("Freeing free IRQ %d\n", bucket->pil);
 457                 return NULL;
 458         }
 459
 460         while (action && action->dev_id != dev_id) {
 461                 pp = &action->next;
 462                 action = *pp;
 463         }
 464
 465         if (likely(action))
 466                 *pp = action->next;
 467
 468         return action;
 469 }
 470
 471 void free_irq(unsigned int irq, void *dev_id)
 472 {
 473         struct irqaction *action;
 474         struct ino_bucket *bucket;
 475         unsigned long flags;
 476
 477         spin_lock_irqsave(&irq_action_lock, flags);
 478
 479         action = unlink_irq_action(irq, dev_id);
 480
 481         spin_unlock_irqrestore(&irq_action_lock, flags);
 482
 483         if (unlikely(!action))
 484                 return;
 485
 486         synchronize_irq(irq);
 487
 488         spin_lock_irqsave(&irq_action_lock, flags);
 489
 490         bucket = __bucket(irq);
 491         if (bucket != &pil0_dummy_bucket) {
 492                 struct irq_desc *desc = bucket->irq_info;
 493                 unsigned long imap = bucket->imap;
 494                 int ent, i;
 495
 496                 for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) {
 497                         struct irqaction *p = &desc->action[i];
 498
 499                         if (p == action) {
 500                                 desc->action_active_mask &= ~(1 << i);
 501                                 break;
 502                         }
 503                 }
 504
 505                 if (!desc->action_active_mask) {
 506                         /* This unique interrupt source is now inactive. */
 507                         bucket->flags &= ~IBF_ACTIVE;
 508
 509                         /* See if any other buckets share this bucket's IMAP
 510                          * and are still active.
 511                          */
 512                         for (ent = 0; ent < NUM_IVECS; ent++) {
 513                                 struct ino_bucket *bp = &ivector_table[ent];
 514                                 if (bp != bucket        &&
 515                                     bp->imap == imap    &&
 516                                     (bp->flags & IBF_ACTIVE) != 0)
 517                                         break;
 518                         }
 519
 520                         /* Only disable when no other sub-irq levels of
 521                          * the same IMAP are active.
 522                          */
 523                         if (ent == NUM_IVECS)
 524                                 disable_irq(irq);
 525                 }
 526         }
 527
 528         spin_unlock_irqrestore(&irq_action_lock, flags);
 529 }
 530
 531 EXPORT_SYMBOL(free_irq);
 532
 533 #ifdef CONFIG_SMP
 534 void synchronize_irq(unsigned int irq)
 535 {
 536         struct ino_bucket *bucket = __bucket(irq);
 537
 538 #if 0
 539         /* The following is how I wish I could implement this.
 540          * Unfortunately the ICLR registers are read-only, you can
 541          * only write ICLR_foo values to them.  To get the current
 542          * IRQ status you would need to get at the IRQ diag registers
 543          * in the PCI/SBUS controller and the layout of those vary
 544          * from one controller to the next, sigh... -DaveM
 545          */
 546         unsigned long iclr = bucket->iclr;
 547
 548         while (1) {
 549                 u32 tmp = upa_readl(iclr);
 550
 551                 if (tmp == ICLR_TRANSMIT ||
 552                     tmp == ICLR_PENDING) {
 553                         cpu_relax();
 554                         continue;
 555                 }
 556                 break;
 557         }
 558 #else
 559         /* So we have to do this with a INPROGRESS bit just like x86.  */
 560         while (bucket->flags & IBF_INPROGRESS)
 561                 cpu_relax();
 562 #endif
 563 }
 564 #endif /* CONFIG_SMP */
 565
 566 static void process_bucket(int irq, struct ino_bucket *bp, struct pt_regs *regs)
 567 {
 568         struct irq_desc *desc = bp->irq_info;
 569         unsigned char flags = bp->flags;
 570         u32 action_mask, i;
 571         int random;
 572
 573         bp->flags |= IBF_INPROGRESS;
 574
 575         if (unlikely(!(flags & IBF_ACTIVE))) {
 576                 bp->pending = 1;
 577                 goto out;
 578         }
 579
 580         if (desc->pre_handler)
 581                 desc->pre_handler(bp,
 582                                   desc->pre_handler_arg1,
 583                                   desc->pre_handler_arg2);
 584
 585         action_mask = desc->action_active_mask;
 586         random = 0;
 587         for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) {
 588                 struct irqaction *p = &desc->action[i];
 589                 u32 mask = (1 << i);
 590
 591                 if (!(action_mask & mask))
 592                         continue;
 593
 594                 action_mask &= ~mask;
 595
 596                 if (p->handler(__irq(bp), p->dev_id, regs) == IRQ_HANDLED)
 597                         random |= p->flags;
 598
 599                 if (!action_mask)
 600                         break;
 601         }
 602         if (bp->pil != 0) {
 603                 upa_writel(ICLR_IDLE, bp->iclr);
 604                 /* Test and add entropy */
 605                 if (random & SA_SAMPLE_RANDOM)
 606                         add_interrupt_randomness(irq);
 607         }
 608 out:
 609         bp->flags &= ~IBF_INPROGRESS;
 610 }
 611
 612 void handler_irq(int irq, struct pt_regs *regs)
 613 {
 614         struct ino_bucket *bp;
 615         int cpu = smp_processor_id();
 616
 617 #ifndef CONFIG_SMP
 618         /*
 619          * Check for TICK_INT on level 14 softint.
 620          */
 621         {
 622                 unsigned long clr_mask = 1 << irq;
 623                 unsigned long tick_mask = tick_ops->softint_mask;
 624
 625                 if ((irq == 14) && (get_softint() & tick_mask)) {
 626                         irq = 0;
 627                         clr_mask = tick_mask;
 628                 }
 629                 clear_softint(clr_mask);
 630         }
 631 #else
 632         clear_softint(1 << irq);
 633 #endif
 634
 635         irq_enter();
 636         kstat_this_cpu.irqs[irq]++;
 637
 638         /* Sliiiick... */
 639 #ifndef CONFIG_SMP
 640         bp = ((irq != 0) ?
 641               __bucket(xchg32(irq_work(cpu, irq), 0)) :
 642               &pil0_dummy_bucket);
 643 #else
 644         bp = __bucket(xchg32(irq_work(cpu, irq), 0));
 645 #endif
 646         while (bp) {
 647                 struct ino_bucket *nbp = __bucket(bp->irq_chain);
 648
 649                 bp->irq_chain = 0;
 650                 process_bucket(irq, bp, regs);
 651                 bp = nbp;
 652         }
 653         irq_exit();
 654 }
 655
 656 #ifdef CONFIG_BLK_DEV_FD
 657 extern irqreturn_t floppy_interrupt(int, void *, struct pt_regs *);;
 658
 659 /* XXX No easy way to include asm/floppy.h XXX */
 660 extern unsigned char *pdma_vaddr;
 661 extern unsigned long pdma_size;
 662 extern volatile int doing_pdma;
 663 extern unsigned long fdc_status;
 664
 665 irqreturn_t sparc_floppy_irq(int irq, void *dev_cookie, struct pt_regs *regs)
 666 {
 667         if (likely(doing_pdma)) {
 668                 void __iomem *stat = (void __iomem *) fdc_status;
 669                 unsigned char *vaddr = pdma_vaddr;
 670                 unsigned long size = pdma_size;
 671                 u8 val;
 672
 673                 while (size) {
 674                         val = readb(stat);
 675                         if (unlikely(!(val & 0x80))) {
 676                                 pdma_vaddr = vaddr;
 677                                 pdma_size = size;
 678                                 return IRQ_HANDLED;
 679                         }
 680                         if (unlikely(!(val & 0x20))) {
 681                                 pdma_vaddr = vaddr;
 682                                 pdma_size = size;
 683                                 doing_pdma = 0;
 684                                 goto main_interrupt;
 685                         }
 686                         if (val & 0x40) {
 687                                 /* read */
 688                                 *vaddr++ = readb(stat + 1);
 689                         } else {
 690                                 unsigned char data = *vaddr++;
 691
 692                                 /* write */
 693                                 writeb(data, stat + 1);
 694                         }
 695                         size--;
 696                 }
 697
 698                 pdma_vaddr = vaddr;
 699                 pdma_size = size;
 700
 701                 /* Send Terminal Count pulse to floppy controller. */
 702                 val = readb(auxio_register);
 703                 val |= AUXIO_AUX1_FTCNT;
 704                 writeb(val, auxio_register);
 705                 val &= ~AUXIO_AUX1_FTCNT;
 706                 writeb(val, auxio_register);
 707
 708                 doing_pdma = 0;
 709         }
 710
 711 main_interrupt:
 712         return floppy_interrupt(irq, dev_cookie, regs);
 713 }
 714 EXPORT_SYMBOL(sparc_floppy_irq);
 715 #endif
 716
 717 /* We really don't need these at all on the Sparc.  We only have
 718  * stubs here because they are exported to modules.
 719  */
 720 unsigned long probe_irq_on(void)
 721 {
 722         return 0;
 723 }
 724
 725 EXPORT_SYMBOL(probe_irq_on);
 726
 727 int probe_irq_off(unsigned long mask)
 728 {
 729         return 0;
 730 }
 731
 732 EXPORT_SYMBOL(probe_irq_off);
 733
 734 #ifdef CONFIG_SMP
 735 static int retarget_one_irq(struct irqaction *p, int goal_cpu)
 736 {
 737         struct ino_bucket *bucket = get_ino_in_irqaction(p) + ivector_table;
 738         unsigned long imap = bucket->imap;
 739         unsigned int tid;
 740
 741         while (!cpu_online(goal_cpu)) {
 742                 if (++goal_cpu >= NR_CPUS)
 743                         goal_cpu = 0;
 744         }
 745
 746         if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 747                 tid = goal_cpu << 26;
 748                 tid &= IMAP_AID_SAFARI;
 749         } else if (this_is_starfire == 0) {
 750                 tid = goal_cpu << 26;
 751                 tid &= IMAP_TID_UPA;
 752         } else {
 753                 tid = (starfire_translate(imap, goal_cpu) << 26);
 754                 tid &= IMAP_TID_UPA;
 755         }
 756         upa_writel(tid | IMAP_VALID, imap);
 757
 758         do {
 759                 if (++goal_cpu >= NR_CPUS)
 760                         goal_cpu = 0;
 761         } while (!cpu_online(goal_cpu));
 762
 763         return goal_cpu;
 764 }
 765
 766 /* Called from request_irq. */
 767 static void distribute_irqs(void)
 768 {
 769         unsigned long flags;
 770         int cpu, level;
 771
 772         spin_lock_irqsave(&irq_action_lock, flags);
 773         cpu = 0;
 774
 775         /*
 776          * Skip the timer at [0], and very rare error/power intrs at [15].
 777          * Also level [12], it causes problems on Ex000 systems.
 778          */
 779         for (level = 1; level < NR_IRQS; level++) {
 780                 struct irqaction *p = irq_action[level];
 781
 782                 if (level == 12)
 783                         continue;
 784
 785                 while(p) {
 786                         cpu = retarget_one_irq(p, cpu);
 787                         p = p->next;
 788                 }
 789         }
 790         spin_unlock_irqrestore(&irq_action_lock, flags);
 791 }
 792 #endif
 793
 794 struct sun5_timer {
 795         u64     count0;
 796         u64     limit0;
 797         u64     count1;
 798         u64     limit1;
 799 };
 800
 801 static struct sun5_timer *prom_timers;
 802 static u64 prom_limit0, prom_limit1;
 803
 804 static void map_prom_timers(void)
 805 {
 806         unsigned int addr[3];
 807         int tnode, err;
 808
 809         /* PROM timer node hangs out in the top level of device siblings... */
 810         tnode = prom_finddevice("/counter-timer");
 811
 812         /* Assume if node is not present, PROM uses different tick mechanism
 813          * which we should not care about.
 814          */
 815         if (tnode == 0 || tnode == -1) {
 816                 prom_timers = (struct sun5_timer *) 0;
 817                 return;
 818         }
 819
 820         /* If PROM is really using this, it must be mapped by him. */
 821         err = prom_getproperty(tnode, "address", (char *)addr, sizeof(addr));
 822         if (err == -1) {
 823                 prom_printf("PROM does not have timer mapped, trying to continue.\n");
 824                 prom_timers = (struct sun5_timer *) 0;
 825                 return;
 826         }
 827         prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
 828 }
 829
 830 static void kill_prom_timer(void)
 831 {
 832         if (!prom_timers)
 833                 return;
 834
 835         /* Save them away for later. */
 836         prom_limit0 = prom_timers->limit0;
 837         prom_limit1 = prom_timers->limit1;
 838
 839         /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
 840          * We turn both off here just to be paranoid.
 841          */
 842         prom_timers->limit0 = 0;
 843         prom_timers->limit1 = 0;
 844
 845         /* Wheee, eat the interrupt packet too... */
 846         __asm__ __volatile__(
 847 "       mov     0x40, %%g2\n"
 848 "       ldxa    [%%g0] %0, %%g1\n"
 849 "       ldxa    [%%g2] %1, %%g1\n"
 850 "       stxa    %%g0, [%%g0] %0\n"
 851 "       membar  #Sync\n"
 852         : /* no outputs */
 853         : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
 854         : "g1", "g2");
 855 }
 856
 857 void init_irqwork_curcpu(void)
 858 {
 859         int cpu = hard_smp_processor_id();
 860
 861         memset(__irq_work + cpu, 0, sizeof(struct irq_work_struct));
 862 }
 863
 864 static void __cpuinit init_one_mondo(unsigned long *pa_ptr, unsigned long type)
 865 {
 866         register unsigned long func __asm__("%o5");
 867         register unsigned long arg0 __asm__("%o0");
 868         register unsigned long arg1 __asm__("%o1");
 869         register unsigned long arg2 __asm__("%o2");
 870         unsigned long page = get_zeroed_page(GFP_ATOMIC);
 871
 872         if (!page) {
 873                 prom_printf("SUN4V: Error, cannot allocate mondo queue.\n");
 874                 prom_halt();
 875         }
 876
 877         *pa_ptr = __pa(page);
 878
 879         func = HV_FAST_CPU_QCONF;
 880         arg0 = type;
 881         arg1 = *pa_ptr;
 882         arg2 = 128; /* XXX Implied by Niagara queue offsets. XXX */
 883         __asm__ __volatile__("ta        %8"
 884                              : "=&r" (func), "=&r" (arg0),
 885                                "=&r" (arg1), "=&r" (arg2)
 886                              : "0" (func), "1" (arg0),
 887                                "2" (arg1), "3" (arg2),
 888                                "i" (HV_FAST_TRAP));
 889
 890         if (func != HV_EOK) {
 891                 prom_printf("SUN4V: cpu_qconf(%lu) failed with error %lu\n",
 892                             type, func);
 893                 prom_halt();
 894         }
 895 }
 896
 897 static void __cpuinit init_one_kbuf(unsigned long *pa_ptr)
 898 {
 899         unsigned long page = get_zeroed_page(GFP_ATOMIC);
 900
 901         if (!page) {
 902                 prom_printf("SUN4V: Error, cannot allocate kbuf page.\n");
 903                 prom_halt();
 904         }
 905
 906         *pa_ptr = __pa(page);
 907 }
 908
 909 static void __cpuinit init_cpu_send_mondo_info(struct trap_per_cpu *tb)
 910 {
 911 #ifdef CONFIG_SMP
 912         unsigned long page;
 913
 914         BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64));
 915
 916         page = get_zeroed_page(GFP_ATOMIC);
 917         if (!page) {
 918                 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
 919                 prom_halt();
 920         }
 921
 922         tb->cpu_mondo_block_pa = __pa(page);
 923         tb->cpu_list_pa = __pa(page + 64);
 924 #endif
 925 }
 926
 927 /* Allocate and init the mondo and error queues for this cpu.  */
 928 void __cpuinit sun4v_init_mondo_queues(void)
 929 {
 930         int cpu = hard_smp_processor_id();
 931         struct trap_per_cpu *tb = &trap_block[cpu];
 932
 933         init_one_mondo(&tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO);
 934         init_one_mondo(&tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO);
 935
 936         init_one_mondo(&tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR);
 937         init_one_kbuf(&tb->resum_kernel_buf_pa);
 938
 939         init_one_mondo(&tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR);
 940         init_one_kbuf(&tb->nonresum_kernel_buf_pa);
 941
 942         init_cpu_send_mondo_info(tb);
 943 }
 944
 945 /* Only invoked on boot processor. */
 946 void __init init_IRQ(void)
 947 {
 948         map_prom_timers();
 949         kill_prom_timer();
 950         memset(&ivector_table[0], 0, sizeof(ivector_table));
 951
 952         if (tlb_type == hypervisor)
 953                 sun4v_init_mondo_queues();
 954
 955         /* We need to clear any IRQ's pending in the soft interrupt
 956          * registers, a spurious one could be left around from the
 957          * PROM timer which we just disabled.
 958          */
 959         clear_softint(get_softint());
 960
 961         /* Now that ivector table is initialized, it is safe
 962          * to receive IRQ vector traps.  We will normally take
 963          * one or two right now, in case some device PROM used
 964          * to boot us wants to speak to us.  We just ignore them.
 965          */
 966         __asm__ __volatile__("rdpr      %%pstate, %%g1\n\t"
 967                              "or        %%g1, %0, %%g1\n\t"
 968                              "wrpr      %%g1, 0x0, %%pstate"
 969                              : /* No outputs */
 970                              : "i" (PSTATE_IE)
 971                              : "g1");
 972 }
 973
 974 static struct proc_dir_entry * root_irq_dir;
 975 static struct proc_dir_entry * irq_dir [NUM_IVECS];
 976
 977 #ifdef CONFIG_SMP
 978
 979 static int irq_affinity_read_proc (char *page, char **start, off_t off,
 980                         int count, int *eof, void *data)
 981 {
 982         struct ino_bucket *bp = ivector_table + (long)data;
 983         struct irq_desc *desc = bp->irq_info;
 984         struct irqaction *ap = desc->action;
 985         cpumask_t mask;
 986         int len;
 987
 988         mask = get_smpaff_in_irqaction(ap);
 989         if (cpus_empty(mask))
 990                 mask = cpu_online_map;
 991
 992         len = cpumask_scnprintf(page, count, mask);
 993         if (count - len < 2)
 994                 return -EINVAL;
 995         len += sprintf(page + len, "\n");
 996         return len;
 997 }
 998
 999 static inline void set_intr_affinity(int irq, cpumask_t hw_aff)
1000 {
1001         struct ino_bucket *bp = ivector_table + irq;
1002         struct irq_desc *desc = bp->irq_info;
1003         struct irqaction *ap = desc->action;
1004
1005         /* Users specify affinity in terms of hw cpu ids.
1006          * As soon as we do this, handler_irq() might see and take action.
1007          */
1008         put_smpaff_in_irqaction(ap, hw_aff);
1009
1010         /* Migration is simply done by the next cpu to service this
1011          * interrupt.
1012          */
1013 }
1014
1015 static int irq_affinity_write_proc (struct file *file, const char __user *buffer,
1016                                         unsigned long count, void *data)
1017 {
1018         int irq = (long) data, full_count = count, err;
1019         cpumask_t new_value;
1020
1021         err = cpumask_parse(buffer, count, new_value);
1022
1023         /*
1024          * Do not allow disabling IRQs completely - it's a too easy
1025          * way to make the system unusable accidentally :-) At least
1026          * one online CPU still has to be targeted.
1027          */
1028         cpus_and(new_value, new_value, cpu_online_map);
1029         if (cpus_empty(new_value))
1030                 return -EINVAL;
1031
1032         set_intr_affinity(irq, new_value);
1033
1034         return full_count;
1035 }
1036
1037 #endif
1038
1039 #define MAX_NAMELEN 10
1040
1041 static void register_irq_proc (unsigned int irq)
1042 {
1043         char name [MAX_NAMELEN];
1044
1045         if (!root_irq_dir || irq_dir[irq])
1046                 return;
1047
1048         memset(name, 0, MAX_NAMELEN);
1049         sprintf(name, "%x", irq);
1050
1051         /* create /proc/irq/1234 */
1052         irq_dir[irq] = proc_mkdir(name, root_irq_dir);
1053
1054 #ifdef CONFIG_SMP
1055         /* XXX SMP affinity not supported on starfire yet. */
1056         if (this_is_starfire == 0) {
1057                 struct proc_dir_entry *entry;
1058
1059                 /* create /proc/irq/1234/smp_affinity */
1060                 entry = create_proc_entry("smp_affinity", 0600, irq_dir[irq]);
1061
1062                 if (entry) {
1063                         entry->nlink = 1;
1064                         entry->data = (void *)(long)irq;
1065                         entry->read_proc = irq_affinity_read_proc;
1066                         entry->write_proc = irq_affinity_write_proc;
1067                 }
1068         }
1069 #endif
1070 }
1071
1072 void init_irq_proc (void)
1073 {
1074         /* create /proc/irq */
1075         root_irq_dir = proc_mkdir("irq", NULL);
1076 }
1077