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   1 /* $Id: irq.c,v 1.114 2002/01/11 08:45:38 davem Exp $
   2  * irq.c: UltraSparc IRQ handling/init/registry.
   3  *
   4  * Copyright (C) 1997  David S. Miller  (davem@caip.rutgers.edu)
   5  * Copyright (C) 1998  Eddie C. Dost    (ecd@skynet.be)
   6  * Copyright (C) 1998  Jakub Jelinek    (jj@ultra.linux.cz)
   7  */
   8
   9 #include <linux/config.h>
  10 #include <linux/module.h>
  11 #include <linux/sched.h>
  12 #include <linux/ptrace.h>
  13 #include <linux/errno.h>
  14 #include <linux/kernel_stat.h>
  15 #include <linux/signal.h>
  16 #include <linux/mm.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/slab.h>
  19 #include <linux/random.h>
  20 #include <linux/init.h>
  21 #include <linux/delay.h>
  22 #include <linux/proc_fs.h>
  23 #include <linux/seq_file.h>
  24 #include <linux/bootmem.h>
  25
  26 #include <asm/ptrace.h>
  27 #include <asm/processor.h>
  28 #include <asm/atomic.h>
  29 #include <asm/system.h>
  30 #include <asm/irq.h>
  31 #include <asm/io.h>
  32 #include <asm/sbus.h>
  33 #include <asm/iommu.h>
  34 #include <asm/upa.h>
  35 #include <asm/oplib.h>
  36 #include <asm/timer.h>
  37 #include <asm/smp.h>
  38 #include <asm/starfire.h>
  39 #include <asm/uaccess.h>
  40 #include <asm/cache.h>
  41 #include <asm/cpudata.h>
  42 #include <asm/auxio.h>
  43 #include <asm/head.h>
  44
  45 #ifdef CONFIG_SMP
  46 static void distribute_irqs(void);
  47 #endif
  48
  49 /* UPA nodes send interrupt packet to UltraSparc with first data reg
  50  * value low 5 (7 on Starfire) bits holding the IRQ identifier being
  51  * delivered.  We must translate this into a non-vector IRQ so we can
  52  * set the softint on this cpu.
  53  *
  54  * To make processing these packets efficient and race free we use
  55  * an array of irq buckets below.  The interrupt vector handler in
  56  * entry.S feeds incoming packets into per-cpu pil-indexed lists.
  57  * The IVEC handler does not need to act atomically, the PIL dispatch
  58  * code uses CAS to get an atomic snapshot of the list and clear it
  59  * at the same time.
  60  */
  61
  62 struct ino_bucket ivector_table[NUM_IVECS] __attribute__ ((aligned (SMP_CACHE_BYTES)));
  63
  64 /* This has to be in the main kernel image, it cannot be
  65  * turned into per-cpu data.  The reason is that the main
  66  * kernel image is locked into the TLB and this structure
  67  * is accessed from the vectored interrupt trap handler.  If
  68  * access to this structure takes a TLB miss it could cause
  69  * the 5-level sparc v9 trap stack to overflow.
  70  */
  71 struct irq_work_struct {
  72         unsigned int    irq_worklists[16];
  73 };
  74 struct irq_work_struct __irq_work[NR_CPUS];
  75 #define irq_work(__cpu, __pil)  &(__irq_work[(__cpu)].irq_worklists[(__pil)])
  76
  77 static struct irqaction *irq_action[NR_IRQS+1];
  78
  79 /* This only synchronizes entities which modify IRQ handler
  80  * state and some selected user-level spots that want to
  81  * read things in the table.  IRQ handler processing orders
  82  * its' accesses such that no locking is needed.
  83  */
  84 static DEFINE_SPINLOCK(irq_action_lock);
  85
  86 static void register_irq_proc (unsigned int irq);
  87
  88 /*
  89  * Upper 2b of irqaction->flags holds the ino.
  90  * irqaction->mask holds the smp affinity information.
  91  */
  92 #define put_ino_in_irqaction(action, irq) \
  93         action->flags &= 0xffffffffffffUL; \
  94         if (__bucket(irq) == &pil0_dummy_bucket) \
  95                 action->flags |= 0xdeadUL << 48;  \
  96         else \
  97                 action->flags |= __irq_ino(irq) << 48;
  98 #define get_ino_in_irqaction(action)    (action->flags >> 48)
  99
 100 #define put_smpaff_in_irqaction(action, smpaff) (action)->mask = (smpaff)
 101 #define get_smpaff_in_irqaction(action)         ((action)->mask)
 102
 103 int show_interrupts(struct seq_file *p, void *v)
 104 {
 105         unsigned long flags;
 106         int i = *(loff_t *) v;
 107         struct irqaction *action;
 108 #ifdef CONFIG_SMP
 109         int j;
 110 #endif
 111
 112         spin_lock_irqsave(&irq_action_lock, flags);
 113         if (i <= NR_IRQS) {
 114                 if (!(action = *(i + irq_action)))
 115                         goto out_unlock;
 116                 seq_printf(p, "%3d: ", i);
 117 #ifndef CONFIG_SMP
 118                 seq_printf(p, "%10u ", kstat_irqs(i));
 119 #else
 120                 for (j = 0; j < NR_CPUS; j++) {
 121                         if (!cpu_online(j))
 122                                 continue;
 123                         seq_printf(p, "%10u ",
 124                                    kstat_cpu(j).irqs[i]);
 125                 }
 126 #endif
 127                 seq_printf(p, " %s:%lx", action->name,
 128                            get_ino_in_irqaction(action));
 129                 for (action = action->next; action; action = action->next) {
 130                         seq_printf(p, ", %s:%lx", action->name,
 131                                    get_ino_in_irqaction(action));
 132                 }
 133                 seq_putc(p, '\n');
 134         }
 135 out_unlock:
 136         spin_unlock_irqrestore(&irq_action_lock, flags);
 137
 138         return 0;
 139 }
 140
 141 /* Now these are always passed a true fully specified sun4u INO. */
 142 void enable_irq(unsigned int irq)
 143 {
 144         struct ino_bucket *bucket = __bucket(irq);
 145         unsigned long imap;
 146
 147         imap = bucket->imap;
 148         if (imap == 0UL)
 149                 return;
 150
 151         preempt_disable();
 152
 153         if (tlb_type == hypervisor) {
 154                 unsigned int ino = __irq_ino(irq);
 155                 int cpu = hard_smp_processor_id();
 156                 int err;
 157
 158                 err = sun4v_intr_settarget(ino, cpu);
 159                 if (err != HV_EOK)
 160                         printk("sun4v_intr_settarget(%x,%d): err(%d)\n",
 161                                ino, cpu, err);
 162                 err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
 163                 if (err != HV_EOK)
 164                         printk("sun4v_intr_setenabled(%x): err(%d)\n",
 165                                ino, err);
 166         } else {
 167                 unsigned long tid;
 168
 169                 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 170                         unsigned long ver;
 171
 172                         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
 173                         if ((ver >> 32) == __JALAPENO_ID ||
 174                             (ver >> 32) == __SERRANO_ID) {
 175                                 /* We set it to our JBUS ID. */
 176                                 __asm__ __volatile__("ldxa [%%g0] %1, %0"
 177                                                      : "=r" (tid)
 178                                                      : "i" (ASI_JBUS_CONFIG));
 179                                 tid = ((tid & (0x1fUL<<17)) << 9);
 180                                 tid &= IMAP_TID_JBUS;
 181                         } else {
 182                                 /* We set it to our Safari AID. */
 183                                 __asm__ __volatile__("ldxa [%%g0] %1, %0"
 184                                                      : "=r" (tid)
 185                                                      : "i"(ASI_SAFARI_CONFIG));
 186                                 tid = ((tid & (0x3ffUL<<17)) << 9);
 187                                 tid &= IMAP_AID_SAFARI;
 188                         }
 189                 } else if (this_is_starfire == 0) {
 190                         /* We set it to our UPA MID. */
 191                         __asm__ __volatile__("ldxa [%%g0] %1, %0"
 192                                              : "=r" (tid)
 193                                              : "i" (ASI_UPA_CONFIG));
 194                         tid = ((tid & UPA_CONFIG_MID) << 9);
 195                         tid &= IMAP_TID_UPA;
 196                 } else {
 197                         tid = (starfire_translate(imap,
 198                                                   smp_processor_id()) << 26);
 199                         tid &= IMAP_TID_UPA;
 200                 }
 201
 202                 /* NOTE NOTE NOTE, IGN and INO are read-only, IGN is a product
 203                  * of this SYSIO's preconfigured IGN in the SYSIO Control
 204                  * Register, the hardware just mirrors that value here.
 205                  * However for Graphics and UPA Slave devices the full
 206                  * IMAP_INR field can be set by the programmer here.
 207                  *
 208                  * Things like FFB can now be handled via the new IRQ
 209                  * mechanism.
 210                  */
 211                 upa_writel(tid | IMAP_VALID, imap);
 212         }
 213
 214         preempt_enable();
 215 }
 216
 217 /* This now gets passed true ino's as well. */
 218 void disable_irq(unsigned int irq)
 219 {
 220         struct ino_bucket *bucket = __bucket(irq);
 221         unsigned long imap;
 222
 223         imap = bucket->imap;
 224         if (imap != 0UL) {
 225                 if (tlb_type == hypervisor) {
 226                         unsigned int ino = __irq_ino(irq);
 227                         int err;
 228
 229                         err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED);
 230                         if (err != HV_EOK)
 231                                 printk("sun4v_intr_setenabled(%x): "
 232                                        "err(%d)\n", ino, err);
 233                 } else {
 234                         u32 tmp;
 235
 236                         /* NOTE: We do not want to futz with the IRQ clear registers
 237                          *       and move the state to IDLE, the SCSI code does call
 238                          *       disable_irq() to assure atomicity in the queue cmd
 239                          *       SCSI adapter driver code.  Thus we'd lose interrupts.
 240                          */
 241                         tmp = upa_readl(imap);
 242                         tmp &= ~IMAP_VALID;
 243                         upa_writel(tmp, imap);
 244                 }
 245         }
 246 }
 247
 248 /* The timer is the one "weird" interrupt which is generated by
 249  * the CPU %tick register and not by some normal vectored interrupt
 250  * source.  To handle this special case, we use this dummy INO bucket.
 251  */
 252 static struct irq_desc pil0_dummy_desc;
 253 static struct ino_bucket pil0_dummy_bucket = {
 254         .irq_info       =       &pil0_dummy_desc,
 255 };
 256
 257 static void build_irq_error(const char *msg, unsigned int ino, int pil, int inofixup,
 258                             unsigned long iclr, unsigned long imap,
 259                             struct ino_bucket *bucket)
 260 {
 261         prom_printf("IRQ: INO %04x (%d:%016lx:%016lx) --> "
 262                     "(%d:%d:%016lx:%016lx), halting...\n",
 263                     ino, bucket->pil, bucket->iclr, bucket->imap,
 264                     pil, inofixup, iclr, imap);
 265         prom_halt();
 266 }
 267
 268 unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap)
 269 {
 270         struct ino_bucket *bucket;
 271         int ino;
 272
 273         if (pil == 0) {
 274                 if (iclr != 0UL || imap != 0UL) {
 275                         prom_printf("Invalid dummy bucket for PIL0 (%lx:%lx)\n",
 276                                     iclr, imap);
 277                         prom_halt();
 278                 }
 279                 return __irq(&pil0_dummy_bucket);
 280         }
 281
 282         BUG_ON(tlb_type == hypervisor);
 283
 284         /* RULE: Both must be specified in all other cases. */
 285         if (iclr == 0UL || imap == 0UL) {
 286                 prom_printf("Invalid build_irq %d %d %016lx %016lx\n",
 287                             pil, inofixup, iclr, imap);
 288                 prom_halt();
 289         }
 290
 291         ino = (upa_readl(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
 292         if (ino > NUM_IVECS) {
 293                 prom_printf("Invalid INO %04x (%d:%d:%016lx:%016lx)\n",
 294                             ino, pil, inofixup, iclr, imap);
 295                 prom_halt();
 296         }
 297
 298         bucket = &ivector_table[ino];
 299         if (bucket->flags & IBF_ACTIVE)
 300                 build_irq_error("IRQ: Trying to build active INO bucket.\n",
 301                                 ino, pil, inofixup, iclr, imap, bucket);
 302
 303         if (bucket->irq_info) {
 304                 if (bucket->imap != imap || bucket->iclr != iclr)
 305                         build_irq_error("IRQ: Trying to reinit INO bucket.\n",
 306                                         ino, pil, inofixup, iclr, imap, bucket);
 307
 308                 goto out;
 309         }
 310
 311         bucket->irq_info = kmalloc(sizeof(struct irq_desc), GFP_ATOMIC);
 312         if (!bucket->irq_info) {
 313                 prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n");
 314                 prom_halt();
 315         }
 316         memset(bucket->irq_info, 0, sizeof(struct irq_desc));
 317
 318         /* Ok, looks good, set it up.  Don't touch the irq_chain or
 319          * the pending flag.
 320          */
 321         bucket->imap  = imap;
 322         bucket->iclr  = iclr;
 323         bucket->pil   = pil;
 324         bucket->flags = 0;
 325
 326 out:
 327         return __irq(bucket);
 328 }
 329
 330 unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino, int pil, unsigned char flags)
 331 {
 332         struct ino_bucket *bucket;
 333         unsigned long sysino;
 334
 335         sysino = sun4v_devino_to_sysino(devhandle, devino);
 336
 337         bucket = &ivector_table[sysino];
 338
 339         /* Catch accidental accesses to these things.  IMAP/ICLR handling
 340          * is done by hypervisor calls on sun4v platforms, not by direct
 341          * register accesses.
 342          *
 343          * But we need to make them look unique for the disable_irq() logic
 344          * in free_irq().
 345          */
 346         bucket->imap = ~0UL - sysino;
 347         bucket->iclr = ~0UL - sysino;
 348
 349         bucket->pil = pil;
 350         bucket->flags = flags;
 351
 352         bucket->irq_info = kmalloc(sizeof(struct irq_desc), GFP_ATOMIC);
 353         if (!bucket->irq_info) {
 354                 prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n");
 355                 prom_halt();
 356         }
 357         memset(bucket->irq_info, 0, sizeof(struct irq_desc));
 358
 359         return __irq(bucket);
 360 }
 361
 362 static void atomic_bucket_insert(struct ino_bucket *bucket)
 363 {
 364         unsigned long pstate;
 365         unsigned int *ent;
 366
 367         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
 368         __asm__ __volatile__("wrpr %0, %1, %%pstate"
 369                              : : "r" (pstate), "i" (PSTATE_IE));
 370         ent = irq_work(smp_processor_id(), bucket->pil);
 371         bucket->irq_chain = *ent;
 372         *ent = __irq(bucket);
 373         __asm__ __volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate));
 374 }
 375
 376 static int check_irq_sharing(int pil, unsigned long irqflags)
 377 {
 378         struct irqaction *action, *tmp;
 379
 380         action = *(irq_action + pil);
 381         if (action) {
 382                 if ((action->flags & SA_SHIRQ) && (irqflags & SA_SHIRQ)) {
 383                         for (tmp = action; tmp->next; tmp = tmp->next)
 384                                 ;
 385                 } else {
 386                         return -EBUSY;
 387                 }
 388         }
 389         return 0;
 390 }
 391
 392 static void append_irq_action(int pil, struct irqaction *action)
 393 {
 394         struct irqaction **pp = irq_action + pil;
 395
 396         while (*pp)
 397                 pp = &((*pp)->next);
 398         *pp = action;
 399 }
 400
 401 static struct irqaction *get_action_slot(struct ino_bucket *bucket)
 402 {
 403         struct irq_desc *desc = bucket->irq_info;
 404         int max_irq, i;
 405
 406         max_irq = 1;
 407         if (bucket->flags & IBF_PCI)
 408                 max_irq = MAX_IRQ_DESC_ACTION;
 409         for (i = 0; i < max_irq; i++) {
 410                 struct irqaction *p = &desc->action[i];
 411                 u32 mask = (1 << i);
 412
 413                 if (desc->action_active_mask & mask)
 414                         continue;
 415
 416                 desc->action_active_mask |= mask;
 417                 return p;
 418         }
 419         return NULL;
 420 }
 421
 422 int request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_regs *),
 423                 unsigned long irqflags, const char *name, void *dev_id)
 424 {
 425         struct irqaction *action;
 426         struct ino_bucket *bucket = __bucket(irq);
 427         unsigned long flags;
 428         int pending = 0;
 429
 430         if (unlikely(!handler))
 431                 return -EINVAL;
 432
 433         if (unlikely(!bucket->irq_info))
 434                 return -ENODEV;
 435
 436         if ((bucket != &pil0_dummy_bucket) && (irqflags & SA_SAMPLE_RANDOM)) {
 437                 /*
 438                  * This function might sleep, we want to call it first,
 439                  * outside of the atomic block. In SA_STATIC_ALLOC case,
 440                  * random driver's kmalloc will fail, but it is safe.
 441                  * If already initialized, random driver will not reinit.
 442                  * Yes, this might clear the entropy pool if the wrong
 443                  * driver is attempted to be loaded, without actually
 444                  * installing a new handler, but is this really a problem,
 445                  * only the sysadmin is able to do this.
 446                  */
 447                 rand_initialize_irq(irq);
 448         }
 449
 450         spin_lock_irqsave(&irq_action_lock, flags);
 451
 452         if (check_irq_sharing(bucket->pil, irqflags)) {
 453                 spin_unlock_irqrestore(&irq_action_lock, flags);
 454                 return -EBUSY;
 455         }
 456
 457         action = get_action_slot(bucket);
 458         if (!action) {
 459                 spin_unlock_irqrestore(&irq_action_lock, flags);
 460                 return -ENOMEM;
 461         }
 462
 463         bucket->flags |= IBF_ACTIVE;
 464         pending = 0;
 465         if (bucket != &pil0_dummy_bucket) {
 466                 pending = bucket->pending;
 467                 if (pending)
 468                         bucket->pending = 0;
 469         }
 470
 471         action->handler = handler;
 472         action->flags = irqflags;
 473         action->name = name;
 474         action->next = NULL;
 475         action->dev_id = dev_id;
 476         put_ino_in_irqaction(action, irq);
 477         put_smpaff_in_irqaction(action, CPU_MASK_NONE);
 478
 479         append_irq_action(bucket->pil, action);
 480
 481         enable_irq(irq);
 482
 483         /* We ate the IVEC already, this makes sure it does not get lost. */
 484         if (pending) {
 485                 atomic_bucket_insert(bucket);
 486                 set_softint(1 << bucket->pil);
 487         }
 488
 489         spin_unlock_irqrestore(&irq_action_lock, flags);
 490
 491         if (bucket != &pil0_dummy_bucket)
 492                 register_irq_proc(__irq_ino(irq));
 493
 494 #ifdef CONFIG_SMP
 495         distribute_irqs();
 496 #endif
 497         return 0;
 498 }
 499
 500 EXPORT_SYMBOL(request_irq);
 501
 502 static struct irqaction *unlink_irq_action(unsigned int irq, void *dev_id)
 503 {
 504         struct ino_bucket *bucket = __bucket(irq);
 505         struct irqaction *action, **pp;
 506
 507         pp = irq_action + bucket->pil;
 508         action = *pp;
 509         if (unlikely(!action))
 510                 return NULL;
 511
 512         if (unlikely(!action->handler)) {
 513                 printk("Freeing free IRQ %d\n", bucket->pil);
 514                 return NULL;
 515         }
 516
 517         while (action && action->dev_id != dev_id) {
 518                 pp = &action->next;
 519                 action = *pp;
 520         }
 521
 522         if (likely(action))
 523                 *pp = action->next;
 524
 525         return action;
 526 }
 527
 528 void free_irq(unsigned int irq, void *dev_id)
 529 {
 530         struct irqaction *action;
 531         struct ino_bucket *bucket;
 532         unsigned long flags;
 533
 534         spin_lock_irqsave(&irq_action_lock, flags);
 535
 536         action = unlink_irq_action(irq, dev_id);
 537
 538         spin_unlock_irqrestore(&irq_action_lock, flags);
 539
 540         if (unlikely(!action))
 541                 return;
 542
 543         synchronize_irq(irq);
 544
 545         spin_lock_irqsave(&irq_action_lock, flags);
 546
 547         bucket = __bucket(irq);
 548         if (bucket != &pil0_dummy_bucket) {
 549                 struct irq_desc *desc = bucket->irq_info;
 550                 int ent, i;
 551
 552                 for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) {
 553                         struct irqaction *p = &desc->action[i];
 554
 555                         if (p == action) {
 556                                 desc->action_active_mask &= ~(1 << i);
 557                                 break;
 558                         }
 559                 }
 560
 561                 if (!desc->action_active_mask) {
 562                         unsigned long imap = bucket->imap;
 563
 564                         /* This unique interrupt source is now inactive. */
 565                         bucket->flags &= ~IBF_ACTIVE;
 566
 567                         /* See if any other buckets share this bucket's IMAP
 568                          * and are still active.
 569                          */
 570                         for (ent = 0; ent < NUM_IVECS; ent++) {
 571                                 struct ino_bucket *bp = &ivector_table[ent];
 572                                 if (bp != bucket        &&
 573                                     bp->imap == imap    &&
 574                                     (bp->flags & IBF_ACTIVE) != 0)
 575                                         break;
 576                         }
 577
 578                         /* Only disable when no other sub-irq levels of
 579                          * the same IMAP are active.
 580                          */
 581                         if (ent == NUM_IVECS)
 582                                 disable_irq(irq);
 583                 }
 584         }
 585
 586         spin_unlock_irqrestore(&irq_action_lock, flags);
 587 }
 588
 589 EXPORT_SYMBOL(free_irq);
 590
 591 #ifdef CONFIG_SMP
 592 void synchronize_irq(unsigned int irq)
 593 {
 594         struct ino_bucket *bucket = __bucket(irq);
 595
 596 #if 0
 597         /* The following is how I wish I could implement this.
 598          * Unfortunately the ICLR registers are read-only, you can
 599          * only write ICLR_foo values to them.  To get the current
 600          * IRQ status you would need to get at the IRQ diag registers
 601          * in the PCI/SBUS controller and the layout of those vary
 602          * from one controller to the next, sigh... -DaveM
 603          */
 604         unsigned long iclr = bucket->iclr;
 605
 606         while (1) {
 607                 u32 tmp = upa_readl(iclr);
 608
 609                 if (tmp == ICLR_TRANSMIT ||
 610                     tmp == ICLR_PENDING) {
 611                         cpu_relax();
 612                         continue;
 613                 }
 614                 break;
 615         }
 616 #else
 617         /* So we have to do this with a INPROGRESS bit just like x86.  */
 618         while (bucket->flags & IBF_INPROGRESS)
 619                 cpu_relax();
 620 #endif
 621 }
 622 #endif /* CONFIG_SMP */
 623
 624 static void process_bucket(int irq, struct ino_bucket *bp, struct pt_regs *regs)
 625 {
 626         struct irq_desc *desc = bp->irq_info;
 627         unsigned char flags = bp->flags;
 628         u32 action_mask, i;
 629         int random;
 630
 631         bp->flags |= IBF_INPROGRESS;
 632
 633         if (unlikely(!(flags & IBF_ACTIVE))) {
 634                 bp->pending = 1;
 635                 goto out;
 636         }
 637
 638         if (desc->pre_handler)
 639                 desc->pre_handler(bp,
 640                                   desc->pre_handler_arg1,
 641                                   desc->pre_handler_arg2);
 642
 643         action_mask = desc->action_active_mask;
 644         random = 0;
 645         for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) {
 646                 struct irqaction *p = &desc->action[i];
 647                 u32 mask = (1 << i);
 648
 649                 if (!(action_mask & mask))
 650                         continue;
 651
 652                 action_mask &= ~mask;
 653
 654                 if (p->handler(__irq(bp), p->dev_id, regs) == IRQ_HANDLED)
 655                         random |= p->flags;
 656
 657                 if (!action_mask)
 658                         break;
 659         }
 660         if (bp->pil != 0) {
 661                 if (tlb_type == hypervisor) {
 662                         unsigned int ino = __irq_ino(bp);
 663                         int err;
 664
 665                         err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
 666                         if (err != HV_EOK)
 667                                 printk("sun4v_intr_setstate(%x): "
 668                                        "err(%d)\n", ino, err);
 669                 } else {
 670                         upa_writel(ICLR_IDLE, bp->iclr);
 671                 }
 672
 673                 /* Test and add entropy */
 674                 if (random & SA_SAMPLE_RANDOM)
 675                         add_interrupt_randomness(irq);
 676         }
 677 out:
 678         bp->flags &= ~IBF_INPROGRESS;
 679 }
 680
 681 void handler_irq(int irq, struct pt_regs *regs)
 682 {
 683         struct ino_bucket *bp;
 684         int cpu = smp_processor_id();
 685
 686 #ifndef CONFIG_SMP
 687         /*
 688          * Check for TICK_INT on level 14 softint.
 689          */
 690         {
 691                 unsigned long clr_mask = 1 << irq;
 692                 unsigned long tick_mask = tick_ops->softint_mask;
 693
 694                 if ((irq == 14) && (get_softint() & tick_mask)) {
 695                         irq = 0;
 696                         clr_mask = tick_mask;
 697                 }
 698                 clear_softint(clr_mask);
 699         }
 700 #else
 701         clear_softint(1 << irq);
 702 #endif
 703
 704         irq_enter();
 705         kstat_this_cpu.irqs[irq]++;
 706
 707         /* Sliiiick... */
 708 #ifndef CONFIG_SMP
 709         bp = ((irq != 0) ?
 710               __bucket(xchg32(irq_work(cpu, irq), 0)) :
 711               &pil0_dummy_bucket);
 712 #else
 713         bp = __bucket(xchg32(irq_work(cpu, irq), 0));
 714 #endif
 715         while (bp) {
 716                 struct ino_bucket *nbp = __bucket(bp->irq_chain);
 717
 718                 bp->irq_chain = 0;
 719                 process_bucket(irq, bp, regs);
 720                 bp = nbp;
 721         }
 722         irq_exit();
 723 }
 724
 725 #ifdef CONFIG_BLK_DEV_FD
 726 extern irqreturn_t floppy_interrupt(int, void *, struct pt_regs *);;
 727
 728 /* XXX No easy way to include asm/floppy.h XXX */
 729 extern unsigned char *pdma_vaddr;
 730 extern unsigned long pdma_size;
 731 extern volatile int doing_pdma;
 732 extern unsigned long fdc_status;
 733
 734 irqreturn_t sparc_floppy_irq(int irq, void *dev_cookie, struct pt_regs *regs)
 735 {
 736         if (likely(doing_pdma)) {
 737                 void __iomem *stat = (void __iomem *) fdc_status;
 738                 unsigned char *vaddr = pdma_vaddr;
 739                 unsigned long size = pdma_size;
 740                 u8 val;
 741
 742                 while (size) {
 743                         val = readb(stat);
 744                         if (unlikely(!(val & 0x80))) {
 745                                 pdma_vaddr = vaddr;
 746                                 pdma_size = size;
 747                                 return IRQ_HANDLED;
 748                         }
 749                         if (unlikely(!(val & 0x20))) {
 750                                 pdma_vaddr = vaddr;
 751                                 pdma_size = size;
 752                                 doing_pdma = 0;
 753                                 goto main_interrupt;
 754                         }
 755                         if (val & 0x40) {
 756                                 /* read */
 757                                 *vaddr++ = readb(stat + 1);
 758                         } else {
 759                                 unsigned char data = *vaddr++;
 760
 761                                 /* write */
 762                                 writeb(data, stat + 1);
 763                         }
 764                         size--;
 765                 }
 766
 767                 pdma_vaddr = vaddr;
 768                 pdma_size = size;
 769
 770                 /* Send Terminal Count pulse to floppy controller. */
 771                 val = readb(auxio_register);
 772                 val |= AUXIO_AUX1_FTCNT;
 773                 writeb(val, auxio_register);
 774                 val &= ~AUXIO_AUX1_FTCNT;
 775                 writeb(val, auxio_register);
 776
 777                 doing_pdma = 0;
 778         }
 779
 780 main_interrupt:
 781         return floppy_interrupt(irq, dev_cookie, regs);
 782 }
 783 EXPORT_SYMBOL(sparc_floppy_irq);
 784 #endif
 785
 786 /* We really don't need these at all on the Sparc.  We only have
 787  * stubs here because they are exported to modules.
 788  */
 789 unsigned long probe_irq_on(void)
 790 {
 791         return 0;
 792 }
 793
 794 EXPORT_SYMBOL(probe_irq_on);
 795
 796 int probe_irq_off(unsigned long mask)
 797 {
 798         return 0;
 799 }
 800
 801 EXPORT_SYMBOL(probe_irq_off);
 802
 803 #ifdef CONFIG_SMP
 804 static int retarget_one_irq(struct irqaction *p, int goal_cpu)
 805 {
 806         struct ino_bucket *bucket = get_ino_in_irqaction(p) + ivector_table;
 807
 808         while (!cpu_online(goal_cpu)) {
 809                 if (++goal_cpu >= NR_CPUS)
 810                         goal_cpu = 0;
 811         }
 812
 813         if (tlb_type == hypervisor) {
 814                 unsigned int ino = __irq_ino(bucket);
 815
 816                 sun4v_intr_settarget(ino, goal_cpu);
 817                 sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
 818         } else {
 819                 unsigned long imap = bucket->imap;
 820                 unsigned int tid;
 821
 822                 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 823                         tid = goal_cpu << 26;
 824                         tid &= IMAP_AID_SAFARI;
 825                 } else if (this_is_starfire == 0) {
 826                         tid = goal_cpu << 26;
 827                         tid &= IMAP_TID_UPA;
 828                 } else {
 829                         tid = (starfire_translate(imap, goal_cpu) << 26);
 830                         tid &= IMAP_TID_UPA;
 831                 }
 832                 upa_writel(tid | IMAP_VALID, imap);
 833         }
 834
 835         do {
 836                 if (++goal_cpu >= NR_CPUS)
 837                         goal_cpu = 0;
 838         } while (!cpu_online(goal_cpu));
 839
 840         return goal_cpu;
 841 }
 842
 843 /* Called from request_irq. */
 844 static void distribute_irqs(void)
 845 {
 846         unsigned long flags;
 847         int cpu, level;
 848
 849         spin_lock_irqsave(&irq_action_lock, flags);
 850         cpu = 0;
 851
 852         /*
 853          * Skip the timer at [0], and very rare error/power intrs at [15].
 854          * Also level [12], it causes problems on Ex000 systems.
 855          */
 856         for (level = 1; level < NR_IRQS; level++) {
 857                 struct irqaction *p = irq_action[level];
 858
 859                 if (level == 12)
 860                         continue;
 861
 862                 while(p) {
 863                         cpu = retarget_one_irq(p, cpu);
 864                         p = p->next;
 865                 }
 866         }
 867         spin_unlock_irqrestore(&irq_action_lock, flags);
 868 }
 869 #endif
 870
 871 struct sun5_timer {
 872         u64     count0;
 873         u64     limit0;
 874         u64     count1;
 875         u64     limit1;
 876 };
 877
 878 static struct sun5_timer *prom_timers;
 879 static u64 prom_limit0, prom_limit1;
 880
 881 static void map_prom_timers(void)
 882 {
 883         unsigned int addr[3];
 884         int tnode, err;
 885
 886         /* PROM timer node hangs out in the top level of device siblings... */
 887         tnode = prom_finddevice("/counter-timer");
 888
 889         /* Assume if node is not present, PROM uses different tick mechanism
 890          * which we should not care about.
 891          */
 892         if (tnode == 0 || tnode == -1) {
 893                 prom_timers = (struct sun5_timer *) 0;
 894                 return;
 895         }
 896
 897         /* If PROM is really using this, it must be mapped by him. */
 898         err = prom_getproperty(tnode, "address", (char *)addr, sizeof(addr));
 899         if (err == -1) {
 900                 prom_printf("PROM does not have timer mapped, trying to continue.\n");
 901                 prom_timers = (struct sun5_timer *) 0;
 902                 return;
 903         }
 904         prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
 905 }
 906
 907 static void kill_prom_timer(void)
 908 {
 909         if (!prom_timers)
 910                 return;
 911
 912         /* Save them away for later. */
 913         prom_limit0 = prom_timers->limit0;
 914         prom_limit1 = prom_timers->limit1;
 915
 916         /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
 917          * We turn both off here just to be paranoid.
 918          */
 919         prom_timers->limit0 = 0;
 920         prom_timers->limit1 = 0;
 921
 922         /* Wheee, eat the interrupt packet too... */
 923         __asm__ __volatile__(
 924 "       mov     0x40, %%g2\n"
 925 "       ldxa    [%%g0] %0, %%g1\n"
 926 "       ldxa    [%%g2] %1, %%g1\n"
 927 "       stxa    %%g0, [%%g0] %0\n"
 928 "       membar  #Sync\n"
 929         : /* no outputs */
 930         : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
 931         : "g1", "g2");
 932 }
 933
 934 void init_irqwork_curcpu(void)
 935 {
 936         int cpu = hard_smp_processor_id();
 937
 938         memset(__irq_work + cpu, 0, sizeof(struct irq_work_struct));
 939 }
 940
 941 static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type)
 942 {
 943         unsigned long num_entries = 128;
 944         unsigned long status;
 945
 946         status = sun4v_cpu_qconf(type, paddr, num_entries);
 947         if (status != HV_EOK) {
 948                 prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
 949                             "err %lu\n", type, paddr, num_entries, status);
 950                 prom_halt();
 951         }
 952 }
 953
 954 static void __cpuinit sun4v_register_mondo_queues(int this_cpu)
 955 {
 956         struct trap_per_cpu *tb = &trap_block[this_cpu];
 957
 958         register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO);
 959         register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO);
 960         register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR);
 961         register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR);
 962 }
 963
 964 static void __cpuinit alloc_one_mondo(unsigned long *pa_ptr, int use_bootmem)
 965 {
 966         void *page;
 967
 968         if (use_bootmem)
 969                 page = alloc_bootmem_low_pages(PAGE_SIZE);
 970         else
 971                 page = (void *) get_zeroed_page(GFP_ATOMIC);
 972
 973         if (!page) {
 974                 prom_printf("SUN4V: Error, cannot allocate mondo queue.\n");
 975                 prom_halt();
 976         }
 977
 978         *pa_ptr = __pa(page);
 979 }
 980
 981 static void __cpuinit alloc_one_kbuf(unsigned long *pa_ptr, int use_bootmem)
 982 {
 983         void *page;
 984
 985         if (use_bootmem)
 986                 page = alloc_bootmem_low_pages(PAGE_SIZE);
 987         else
 988                 page = (void *) get_zeroed_page(GFP_ATOMIC);
 989
 990         if (!page) {
 991                 prom_printf("SUN4V: Error, cannot allocate kbuf page.\n");
 992                 prom_halt();
 993         }
 994
 995         *pa_ptr = __pa(page);
 996 }
 997
 998 static void __cpuinit init_cpu_send_mondo_info(struct trap_per_cpu *tb, int use_bootmem)
 999 {
1000 #ifdef CONFIG_SMP
1001         void *page;
1002
1003         BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64));
1004
1005         if (use_bootmem)
1006                 page = alloc_bootmem_low_pages(PAGE_SIZE);
1007         else
1008                 page = (void *) get_zeroed_page(GFP_ATOMIC);
1009
1010         if (!page) {
1011                 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
1012                 prom_halt();
1013         }
1014
1015         tb->cpu_mondo_block_pa = __pa(page);
1016         tb->cpu_list_pa = __pa(page + 64);
1017 #endif
1018 }
1019
1020 /* Allocate and register the mondo and error queues for this cpu.  */
1021 void __cpuinit sun4v_init_mondo_queues(int use_bootmem)
1022 {
1023         int cpu = hard_smp_processor_id();
1024         struct trap_per_cpu *tb = &trap_block[cpu];
1025
1026         alloc_one_mondo(&tb->cpu_mondo_pa, use_bootmem);
1027         alloc_one_mondo(&tb->dev_mondo_pa, use_bootmem);
1028         alloc_one_mondo(&tb->resum_mondo_pa, use_bootmem);
1029         alloc_one_kbuf(&tb->resum_kernel_buf_pa, use_bootmem);
1030         alloc_one_mondo(&tb->nonresum_mondo_pa, use_bootmem);
1031         alloc_one_kbuf(&tb->nonresum_kernel_buf_pa, use_bootmem);
1032
1033         init_cpu_send_mondo_info(tb, use_bootmem);
1034
1035         sun4v_register_mondo_queues(cpu);
1036 }
1037
1038 /* Only invoked on boot processor. */
1039 void __init init_IRQ(void)
1040 {
1041         map_prom_timers();
1042         kill_prom_timer();
1043         memset(&ivector_table[0], 0, sizeof(ivector_table));
1044
1045         if (tlb_type == hypervisor)
1046                 sun4v_init_mondo_queues(1);
1047
1048         /* We need to clear any IRQ's pending in the soft interrupt
1049          * registers, a spurious one could be left around from the
1050          * PROM timer which we just disabled.
1051          */
1052         clear_softint(get_softint());
1053
1054         /* Now that ivector table is initialized, it is safe
1055          * to receive IRQ vector traps.  We will normally take
1056          * one or two right now, in case some device PROM used
1057          * to boot us wants to speak to us.  We just ignore them.
1058          */
1059         __asm__ __volatile__("rdpr      %%pstate, %%g1\n\t"
1060                              "or        %%g1, %0, %%g1\n\t"
1061                              "wrpr      %%g1, 0x0, %%pstate"
1062                              : /* No outputs */
1063                              : "i" (PSTATE_IE)
1064                              : "g1");
1065 }
1066
1067 static struct proc_dir_entry * root_irq_dir;
1068 static struct proc_dir_entry * irq_dir [NUM_IVECS];
1069
1070 #ifdef CONFIG_SMP
1071
1072 static int irq_affinity_read_proc (char *page, char **start, off_t off,
1073                         int count, int *eof, void *data)
1074 {
1075         struct ino_bucket *bp = ivector_table + (long)data;
1076         struct irq_desc *desc = bp->irq_info;
1077         struct irqaction *ap = desc->action;
1078         cpumask_t mask;
1079         int len;
1080
1081         mask = get_smpaff_in_irqaction(ap);
1082         if (cpus_empty(mask))
1083                 mask = cpu_online_map;
1084
1085         len = cpumask_scnprintf(page, count, mask);
1086         if (count - len < 2)
1087                 return -EINVAL;
1088         len += sprintf(page + len, "\n");
1089         return len;
1090 }
1091
1092 static inline void set_intr_affinity(int irq, cpumask_t hw_aff)
1093 {
1094         struct ino_bucket *bp = ivector_table + irq;
1095         struct irq_desc *desc = bp->irq_info;
1096         struct irqaction *ap = desc->action;
1097
1098         /* Users specify affinity in terms of hw cpu ids.
1099          * As soon as we do this, handler_irq() might see and take action.
1100          */
1101         put_smpaff_in_irqaction(ap, hw_aff);
1102
1103         /* Migration is simply done by the next cpu to service this
1104          * interrupt.
1105          */
1106 }
1107
1108 static int irq_affinity_write_proc (struct file *file, const char __user *buffer,
1109                                         unsigned long count, void *data)
1110 {
1111         int irq = (long) data, full_count = count, err;
1112         cpumask_t new_value;
1113
1114         err = cpumask_parse(buffer, count, new_value);
1115
1116         /*
1117          * Do not allow disabling IRQs completely - it's a too easy
1118          * way to make the system unusable accidentally :-) At least
1119          * one online CPU still has to be targeted.
1120          */
1121         cpus_and(new_value, new_value, cpu_online_map);
1122         if (cpus_empty(new_value))
1123                 return -EINVAL;
1124
1125         set_intr_affinity(irq, new_value);
1126
1127         return full_count;
1128 }
1129
1130 #endif
1131
1132 #define MAX_NAMELEN 10
1133
1134 static void register_irq_proc (unsigned int irq)
1135 {
1136         char name [MAX_NAMELEN];
1137
1138         if (!root_irq_dir || irq_dir[irq])
1139                 return;
1140
1141         memset(name, 0, MAX_NAMELEN);
1142         sprintf(name, "%x", irq);
1143
1144         /* create /proc/irq/1234 */
1145         irq_dir[irq] = proc_mkdir(name, root_irq_dir);
1146
1147 #ifdef CONFIG_SMP
1148         /* XXX SMP affinity not supported on starfire yet. */
1149         if (this_is_starfire == 0) {
1150                 struct proc_dir_entry *entry;
1151
1152                 /* create /proc/irq/1234/smp_affinity */
1153                 entry = create_proc_entry("smp_affinity", 0600, irq_dir[irq]);
1154
1155                 if (entry) {
1156                         entry->nlink = 1;
1157                         entry->data = (void *)(long)irq;
1158                         entry->read_proc = irq_affinity_read_proc;
1159                         entry->write_proc = irq_affinity_write_proc;
1160                 }
1161         }
1162 #endif
1163 }
1164
1165 void init_irq_proc (void)
1166 {
1167         /* create /proc/irq */
1168         root_irq_dir = proc_mkdir("irq", NULL);
1169 }
1170