2 * 'traps.c' handles hardware traps and faults after we have saved some
5 * SuperH version: Copyright (C) 1999 Niibe Yutaka
6 * Copyright (C) 2000 Philipp Rumpf
7 * Copyright (C) 2000 David Howells
8 * Copyright (C) 2002 - 2007 Paul Mundt
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
14 #include <linux/kernel.h>
15 #include <linux/ptrace.h>
16 #include <linux/hardirq.h>
17 #include <linux/init.h>
18 #include <linux/spinlock.h>
19 #include <linux/module.h>
20 #include <linux/kallsyms.h>
22 #include <linux/bug.h>
23 #include <linux/debug_locks.h>
24 #include <linux/kdebug.h>
25 #include <linux/kexec.h>
26 #include <linux/limits.h>
27 #include <linux/sysfs.h>
28 #include <linux/uaccess.h>
29 #include <asm/system.h>
30 #include <asm/alignment.h>
32 #include <asm/kprobes.h>
33 #include <asm/sh_bios.h>
36 # define TRAP_RESERVED_INST 4
37 # define TRAP_ILLEGAL_SLOT_INST 6
38 # define TRAP_ADDRESS_ERROR 9
39 # ifdef CONFIG_CPU_SH2A
41 # define TRAP_FPU_ERROR 13
42 # define TRAP_DIVZERO_ERROR 17
43 # define TRAP_DIVOVF_ERROR 18
46 #define TRAP_RESERVED_INST 12
47 #define TRAP_ILLEGAL_SLOT_INST 13
50 static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
55 printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
57 for (p = bottom & ~31; p < top; ) {
58 printk("%04lx: ", p & 0xffff);
60 for (i = 0; i < 8; i++, p += 4) {
63 if (p < bottom || p >= top)
66 if (__get_user(val, (unsigned int __user *)p)) {
77 static DEFINE_SPINLOCK(die_lock);
79 void die(const char * str, struct pt_regs * regs, long err)
81 static int die_counter;
85 spin_lock_irq(&die_lock);
89 printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
90 sysfs_printk_last_file();
94 printk("Process: %s (pid: %d, stack limit = %p)\n", current->comm,
95 task_pid_nr(current), task_stack_page(current) + 1);
97 if (!user_mode(regs) || in_interrupt())
98 dump_mem("Stack: ", regs->regs[15], THREAD_SIZE +
99 (unsigned long)task_stack_page(current));
101 notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV);
104 add_taint(TAINT_DIE);
105 spin_unlock_irq(&die_lock);
108 if (kexec_should_crash(current))
112 panic("Fatal exception in interrupt");
115 panic("Fatal exception");
120 static inline void die_if_kernel(const char *str, struct pt_regs *regs,
123 if (!user_mode(regs))
128 * try and fix up kernelspace address errors
129 * - userspace errors just cause EFAULT to be returned, resulting in SEGV
130 * - kernel/userspace interfaces cause a jump to an appropriate handler
131 * - other kernel errors are bad
133 static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
135 if (!user_mode(regs)) {
136 const struct exception_table_entry *fixup;
137 fixup = search_exception_tables(regs->pc);
139 regs->pc = fixup->fixup;
147 static inline void sign_extend(unsigned int count, unsigned char *dst)
149 #ifdef __LITTLE_ENDIAN__
150 if ((count == 1) && dst[0] & 0x80) {
155 if ((count == 2) && dst[1] & 0x80) {
160 if ((count == 1) && dst[3] & 0x80) {
165 if ((count == 2) && dst[2] & 0x80) {
172 static struct mem_access user_mem_access = {
178 * handle an instruction that does an unaligned memory access by emulating the
180 * - note that PC _may not_ point to the faulting instruction
181 * (if that instruction is in a branch delay slot)
182 * - return 0 if emulation okay, -EFAULT on existential error
184 static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs,
185 struct mem_access *ma)
187 int ret, index, count;
188 unsigned long *rm, *rn;
189 unsigned char *src, *dst;
190 unsigned char __user *srcu, *dstu;
192 index = (instruction>>8)&15; /* 0x0F00 */
193 rn = ®s->regs[index];
195 index = (instruction>>4)&15; /* 0x00F0 */
196 rm = ®s->regs[index];
198 count = 1<<(instruction&3);
201 case 1: inc_unaligned_byte_access(); break;
202 case 2: inc_unaligned_word_access(); break;
203 case 4: inc_unaligned_dword_access(); break;
204 case 8: inc_unaligned_multi_access(); break;
208 switch (instruction>>12) {
209 case 0: /* mov.[bwl] to/from memory via r0+rn */
210 if (instruction & 8) {
212 srcu = (unsigned char __user *)*rm;
213 srcu += regs->regs[0];
214 dst = (unsigned char *)rn;
215 *(unsigned long *)dst = 0;
217 #if !defined(__LITTLE_ENDIAN__)
220 if (ma->from(dst, srcu, count))
223 sign_extend(count, dst);
226 src = (unsigned char *)rm;
227 #if !defined(__LITTLE_ENDIAN__)
230 dstu = (unsigned char __user *)*rn;
231 dstu += regs->regs[0];
233 if (ma->to(dstu, src, count))
239 case 1: /* mov.l Rm,@(disp,Rn) */
240 src = (unsigned char*) rm;
241 dstu = (unsigned char __user *)*rn;
242 dstu += (instruction&0x000F)<<2;
244 if (ma->to(dstu, src, 4))
249 case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
252 src = (unsigned char*) rm;
253 dstu = (unsigned char __user *)*rn;
254 #if !defined(__LITTLE_ENDIAN__)
257 if (ma->to(dstu, src, count))
262 case 5: /* mov.l @(disp,Rm),Rn */
263 srcu = (unsigned char __user *)*rm;
264 srcu += (instruction & 0x000F) << 2;
265 dst = (unsigned char *)rn;
266 *(unsigned long *)dst = 0;
268 if (ma->from(dst, srcu, 4))
273 case 6: /* mov.[bwl] from memory, possibly with post-increment */
274 srcu = (unsigned char __user *)*rm;
277 dst = (unsigned char*) rn;
278 *(unsigned long*)dst = 0;
280 #if !defined(__LITTLE_ENDIAN__)
283 if (ma->from(dst, srcu, count))
285 sign_extend(count, dst);
290 switch ((instruction&0xFF00)>>8) {
291 case 0x81: /* mov.w R0,@(disp,Rn) */
292 src = (unsigned char *) ®s->regs[0];
293 #if !defined(__LITTLE_ENDIAN__)
296 dstu = (unsigned char __user *)*rm; /* called Rn in the spec */
297 dstu += (instruction & 0x000F) << 1;
299 if (ma->to(dstu, src, 2))
304 case 0x85: /* mov.w @(disp,Rm),R0 */
305 srcu = (unsigned char __user *)*rm;
306 srcu += (instruction & 0x000F) << 1;
307 dst = (unsigned char *) ®s->regs[0];
308 *(unsigned long *)dst = 0;
310 #if !defined(__LITTLE_ENDIAN__)
313 if (ma->from(dst, srcu, 2))
324 /* Argh. Address not only misaligned but also non-existent.
325 * Raise an EFAULT and see if it's trapped
327 die_if_no_fixup("Fault in unaligned fixup", regs, 0);
332 * emulate the instruction in the delay slot
333 * - fetches the instruction from PC+2
335 static inline int handle_delayslot(struct pt_regs *regs,
336 insn_size_t old_instruction,
337 struct mem_access *ma)
339 insn_size_t instruction;
340 void __user *addr = (void __user *)(regs->pc +
341 instruction_size(old_instruction));
343 if (copy_from_user(&instruction, addr, sizeof(instruction))) {
344 /* the instruction-fetch faulted */
349 die("delay-slot-insn faulting in handle_unaligned_delayslot",
353 return handle_unaligned_ins(instruction, regs, ma);
357 * handle an instruction that does an unaligned memory access
358 * - have to be careful of branch delay-slot instructions that fault
360 * - if the branch would be taken PC points to the branch
361 * - if the branch would not be taken, PC points to delay-slot
363 * - PC always points to delayed branch
364 * - return 0 if handled, -EFAULT if failed (may not return if in kernel)
367 /* Macros to determine offset from current PC for branch instructions */
368 /* Explicit type coercion is used to force sign extension where needed */
369 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
370 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
372 int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
373 struct mem_access *ma, int expected)
379 * XXX: We can't handle mixed 16/32-bit instructions yet
381 if (instruction_size(instruction) != 2)
384 index = (instruction>>8)&15; /* 0x0F00 */
385 rm = regs->regs[index];
387 /* shout about fixups */
389 unaligned_fixups_notify(current, instruction, regs);
392 switch (instruction&0xF000) {
394 if (instruction==0x000B) {
396 ret = handle_delayslot(regs, instruction, ma);
400 else if ((instruction&0x00FF)==0x0023) {
402 ret = handle_delayslot(regs, instruction, ma);
406 else if ((instruction&0x00FF)==0x0003) {
408 ret = handle_delayslot(regs, instruction, ma);
410 regs->pr = regs->pc + 4;
415 /* mov.[bwl] to/from memory via r0+rn */
420 case 0x1000: /* mov.l Rm,@(disp,Rn) */
423 case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
427 if ((instruction&0x00FF)==0x002B) {
429 ret = handle_delayslot(regs, instruction, ma);
433 else if ((instruction&0x00FF)==0x000B) {
435 ret = handle_delayslot(regs, instruction, ma);
437 regs->pr = regs->pc + 4;
442 /* mov.[bwl] to/from memory via r0+rn */
447 case 0x5000: /* mov.l @(disp,Rm),Rn */
450 case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
453 case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
454 switch (instruction&0x0F00) {
455 case 0x0100: /* mov.w R0,@(disp,Rm) */
457 case 0x0500: /* mov.w @(disp,Rm),R0 */
459 case 0x0B00: /* bf lab - no delayslot*/
461 case 0x0F00: /* bf/s lab */
462 ret = handle_delayslot(regs, instruction, ma);
464 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
465 if ((regs->sr & 0x00000001) != 0)
466 regs->pc += 4; /* next after slot */
469 regs->pc += SH_PC_8BIT_OFFSET(instruction);
472 case 0x0900: /* bt lab - no delayslot */
474 case 0x0D00: /* bt/s lab */
475 ret = handle_delayslot(regs, instruction, ma);
477 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
478 if ((regs->sr & 0x00000001) == 0)
479 regs->pc += 4; /* next after slot */
482 regs->pc += SH_PC_8BIT_OFFSET(instruction);
488 case 0xA000: /* bra label */
489 ret = handle_delayslot(regs, instruction, ma);
491 regs->pc += SH_PC_12BIT_OFFSET(instruction);
494 case 0xB000: /* bsr label */
495 ret = handle_delayslot(regs, instruction, ma);
497 regs->pr = regs->pc + 4;
498 regs->pc += SH_PC_12BIT_OFFSET(instruction);
504 /* handle non-delay-slot instruction */
506 ret = handle_unaligned_ins(instruction, regs, ma);
508 regs->pc += instruction_size(instruction);
513 * Handle various address error exceptions:
514 * - instruction address error:
516 * PC >= 0x80000000 in user mode
517 * - data address error (read and write)
518 * misaligned data access
519 * access to >= 0x80000000 is user mode
520 * Unfortuntaly we can't distinguish between instruction address error
521 * and data address errors caused by read accesses.
523 asmlinkage void do_address_error(struct pt_regs *regs,
524 unsigned long writeaccess,
525 unsigned long address)
527 unsigned long error_code = 0;
530 insn_size_t instruction;
533 /* Intentional ifdef */
534 #ifdef CONFIG_CPU_HAS_SR_RB
535 error_code = lookup_exception_vector();
540 if (user_mode(regs)) {
541 int si_code = BUS_ADRERR;
542 unsigned int user_action;
545 inc_unaligned_user_access();
548 if (copy_from_user(&instruction, (insn_size_t *)(regs->pc & ~1),
549 sizeof(instruction))) {
555 /* shout about userspace fixups */
556 unaligned_fixups_notify(current, instruction, regs);
558 user_action = unaligned_user_action();
559 if (user_action & UM_FIXUP)
561 if (user_action & UM_SIGNAL)
565 regs->pc += instruction_size(instruction);
570 /* bad PC is not something we can fix */
572 si_code = BUS_ADRALN;
577 tmp = handle_unaligned_access(instruction, regs,
578 &user_mem_access, 0);
584 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned "
585 "access (PC %lx PR %lx)\n", current->comm, regs->pc,
588 info.si_signo = SIGBUS;
590 info.si_code = si_code;
591 info.si_addr = (void __user *)address;
592 force_sig_info(SIGBUS, &info, current);
594 inc_unaligned_kernel_access();
597 die("unaligned program counter", regs, error_code);
600 if (copy_from_user(&instruction, (void __user *)(regs->pc),
601 sizeof(instruction))) {
602 /* Argh. Fault on the instruction itself.
603 This should never happen non-SMP
606 die("insn faulting in do_address_error", regs, 0);
609 unaligned_fixups_notify(current, instruction, regs);
611 handle_unaligned_access(instruction, regs,
612 &user_mem_access, 0);
619 * SH-DSP support gerg@snapgear.com.
621 int is_dsp_inst(struct pt_regs *regs)
623 unsigned short inst = 0;
626 * Safe guard if DSP mode is already enabled or we're lacking
627 * the DSP altogether.
629 if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
632 get_user(inst, ((unsigned short *) regs->pc));
636 /* Check for any type of DSP or support instruction */
637 if ((inst == 0xf000) || (inst == 0x4000))
643 #define is_dsp_inst(regs) (0)
644 #endif /* CONFIG_SH_DSP */
646 #ifdef CONFIG_CPU_SH2A
647 asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
648 unsigned long r6, unsigned long r7,
649 struct pt_regs __regs)
654 case TRAP_DIVZERO_ERROR:
655 info.si_code = FPE_INTDIV;
657 case TRAP_DIVOVF_ERROR:
658 info.si_code = FPE_INTOVF;
662 force_sig_info(SIGFPE, &info, current);
666 asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
667 unsigned long r6, unsigned long r7,
668 struct pt_regs __regs)
670 struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
671 unsigned long error_code;
672 struct task_struct *tsk = current;
674 #ifdef CONFIG_SH_FPU_EMU
675 unsigned short inst = 0;
678 get_user(inst, (unsigned short*)regs->pc);
680 err = do_fpu_inst(inst, regs);
682 regs->pc += instruction_size(inst);
685 /* not a FPU inst. */
689 /* Check if it's a DSP instruction */
690 if (is_dsp_inst(regs)) {
691 /* Enable DSP mode, and restart instruction. */
694 tsk->thread.dsp_status.status |= SR_DSP;
699 error_code = lookup_exception_vector();
702 force_sig(SIGILL, tsk);
703 die_if_no_fixup("reserved instruction", regs, error_code);
706 #ifdef CONFIG_SH_FPU_EMU
707 static int emulate_branch(unsigned short inst, struct pt_regs *regs)
710 * bfs: 8fxx: PC+=d*2+4;
711 * bts: 8dxx: PC+=d*2+4;
712 * bra: axxx: PC+=D*2+4;
713 * bsr: bxxx: PC+=D*2+4 after PR=PC+4;
714 * braf:0x23: PC+=Rn*2+4;
715 * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
717 * jsr: 4x0b: PC=Rn after PR=PC+4;
720 if (((inst & 0xf000) == 0xb000) || /* bsr */
721 ((inst & 0xf0ff) == 0x0003) || /* bsrf */
722 ((inst & 0xf0ff) == 0x400b)) /* jsr */
723 regs->pr = regs->pc + 4;
725 if ((inst & 0xfd00) == 0x8d00) { /* bfs, bts */
726 regs->pc += SH_PC_8BIT_OFFSET(inst);
730 if ((inst & 0xe000) == 0xa000) { /* bra, bsr */
731 regs->pc += SH_PC_12BIT_OFFSET(inst);
735 if ((inst & 0xf0df) == 0x0003) { /* braf, bsrf */
736 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
740 if ((inst & 0xf0df) == 0x400b) { /* jmp, jsr */
741 regs->pc = regs->regs[(inst & 0x0f00) >> 8];
745 if ((inst & 0xffff) == 0x000b) { /* rts */
754 asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
755 unsigned long r6, unsigned long r7,
756 struct pt_regs __regs)
758 struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
760 struct task_struct *tsk = current;
762 if (kprobe_handle_illslot(regs->pc) == 0)
765 #ifdef CONFIG_SH_FPU_EMU
766 get_user(inst, (unsigned short *)regs->pc + 1);
767 if (!do_fpu_inst(inst, regs)) {
768 get_user(inst, (unsigned short *)regs->pc);
769 if (!emulate_branch(inst, regs))
771 /* fault in branch.*/
773 /* not a FPU inst. */
776 inst = lookup_exception_vector();
779 force_sig(SIGILL, tsk);
780 die_if_no_fixup("illegal slot instruction", regs, inst);
783 asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
784 unsigned long r6, unsigned long r7,
785 struct pt_regs __regs)
787 struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
790 ex = lookup_exception_vector();
791 die_if_kernel("exception", regs, ex);
794 void __cpuinit per_cpu_trap_init(void)
796 extern void *vbr_base;
798 /* NOTE: The VBR value should be at P1
799 (or P2, virtural "fixed" address space).
800 It's definitely should not in physical address. */
802 asm volatile("ldc %0, vbr"
808 void *set_exception_table_vec(unsigned int vec, void *handler)
810 extern void *exception_handling_table[];
813 old_handler = exception_handling_table[vec];
814 exception_handling_table[vec] = handler;
818 void __init trap_init(void)
820 set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
821 set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
823 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
824 defined(CONFIG_SH_FPU_EMU)
826 * For SH-4 lacking an FPU, treat floating point instructions as
827 * reserved. They'll be handled in the math-emu case, or faulted on
830 set_exception_table_evt(0x800, do_reserved_inst);
831 set_exception_table_evt(0x820, do_illegal_slot_inst);
832 #elif defined(CONFIG_SH_FPU)
833 set_exception_table_evt(0x800, fpu_state_restore_trap_handler);
834 set_exception_table_evt(0x820, fpu_state_restore_trap_handler);
837 #ifdef CONFIG_CPU_SH2
838 set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler);
840 #ifdef CONFIG_CPU_SH2A
841 set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error);
842 set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error);
844 set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler);
849 set_exception_table_vec(TRAP_UBC, breakpoint_trap_handler);
852 /* Save off the BIOS VBR, if there is one */
855 /* Setup VBR for boot cpu */
859 void show_stack(struct task_struct *tsk, unsigned long *sp)
866 sp = (unsigned long *)current_stack_pointer;
868 sp = (unsigned long *)tsk->thread.sp;
870 stack = (unsigned long)sp;
871 dump_mem("Stack: ", stack, THREAD_SIZE +
872 (unsigned long)task_stack_page(tsk));
873 show_trace(tsk, sp, NULL);
876 void dump_stack(void)
878 show_stack(NULL, NULL);
880 EXPORT_SYMBOL(dump_stack);