2 * 'traps.c' handles hardware traps and faults after we have saved some
5 * SuperH version: Copyright (C) 1999 Niibe Yutaka
6 * Copyright (C) 2000 Philipp Rumpf
7 * Copyright (C) 2000 David Howells
8 * Copyright (C) 2002 - 2007 Paul Mundt
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
14 #include <linux/kernel.h>
15 #include <linux/ptrace.h>
16 #include <linux/hardirq.h>
17 #include <linux/init.h>
18 #include <linux/spinlock.h>
19 #include <linux/module.h>
20 #include <linux/kallsyms.h>
22 #include <linux/bug.h>
23 #include <linux/debug_locks.h>
24 #include <linux/kdebug.h>
25 #include <linux/kexec.h>
26 #include <linux/limits.h>
27 #include <linux/proc_fs.h>
28 #include <linux/sysfs.h>
29 #include <asm/system.h>
30 #include <asm/uaccess.h>
32 #include <asm/kprobes.h>
35 # define TRAP_RESERVED_INST 4
36 # define TRAP_ILLEGAL_SLOT_INST 6
37 # define TRAP_ADDRESS_ERROR 9
38 # ifdef CONFIG_CPU_SH2A
40 # define TRAP_FPU_ERROR 13
41 # define TRAP_DIVZERO_ERROR 17
42 # define TRAP_DIVOVF_ERROR 18
45 #define TRAP_RESERVED_INST 12
46 #define TRAP_ILLEGAL_SLOT_INST 13
49 static unsigned long se_user;
50 static unsigned long se_sys;
51 static unsigned long se_half;
52 static unsigned long se_word;
53 static unsigned long se_dword;
54 static unsigned long se_multi;
55 /* bitfield: 1: warn 2: fixup 4: signal -> combinations 2|4 && 1|2|4 are not
57 static int se_usermode = 3;
58 /* 0: no warning 1: print a warning message, disabled by default */
59 static int se_kernmode_warn;
62 static const char *se_usermode_action[] = {
72 proc_alignment_read(char *page, char **start, off_t off, int count, int *eof,
78 p += sprintf(p, "User:\t\t%lu\n", se_user);
79 p += sprintf(p, "System:\t\t%lu\n", se_sys);
80 p += sprintf(p, "Half:\t\t%lu\n", se_half);
81 p += sprintf(p, "Word:\t\t%lu\n", se_word);
82 p += sprintf(p, "DWord:\t\t%lu\n", se_dword);
83 p += sprintf(p, "Multi:\t\t%lu\n", se_multi);
84 p += sprintf(p, "User faults:\t%i (%s)\n", se_usermode,
85 se_usermode_action[se_usermode]);
86 p += sprintf(p, "Kernel faults:\t%i (fixup%s)\n", se_kernmode_warn,
87 se_kernmode_warn ? "+warn" : "");
89 len = (p - page) - off;
93 *eof = (len <= count) ? 1 : 0;
99 static int proc_alignment_write(struct file *file, const char __user *buffer,
100 unsigned long count, void *data)
105 if (get_user(mode, buffer))
107 if (mode >= '0' && mode <= '5')
108 se_usermode = mode - '0';
113 static int proc_alignment_kern_write(struct file *file, const char __user *buffer,
114 unsigned long count, void *data)
119 if (get_user(mode, buffer))
121 if (mode >= '0' && mode <= '1')
122 se_kernmode_warn = mode - '0';
128 static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
133 printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
135 for (p = bottom & ~31; p < top; ) {
136 printk("%04lx: ", p & 0xffff);
138 for (i = 0; i < 8; i++, p += 4) {
141 if (p < bottom || p >= top)
144 if (__get_user(val, (unsigned int __user *)p)) {
148 printk("%08x ", val);
155 static DEFINE_SPINLOCK(die_lock);
157 void die(const char * str, struct pt_regs * regs, long err)
159 static int die_counter;
163 spin_lock_irq(&die_lock);
167 printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
168 sysfs_printk_last_file();
172 printk("Process: %s (pid: %d, stack limit = %p)\n", current->comm,
173 task_pid_nr(current), task_stack_page(current) + 1);
175 if (!user_mode(regs) || in_interrupt())
176 dump_mem("Stack: ", regs->regs[15], THREAD_SIZE +
177 (unsigned long)task_stack_page(current));
179 notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV);
182 add_taint(TAINT_DIE);
183 spin_unlock_irq(&die_lock);
186 if (kexec_should_crash(current))
190 panic("Fatal exception in interrupt");
193 panic("Fatal exception");
198 static inline void die_if_kernel(const char *str, struct pt_regs *regs,
201 if (!user_mode(regs))
206 * try and fix up kernelspace address errors
207 * - userspace errors just cause EFAULT to be returned, resulting in SEGV
208 * - kernel/userspace interfaces cause a jump to an appropriate handler
209 * - other kernel errors are bad
211 static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
213 if (!user_mode(regs)) {
214 const struct exception_table_entry *fixup;
215 fixup = search_exception_tables(regs->pc);
217 regs->pc = fixup->fixup;
225 static inline void sign_extend(unsigned int count, unsigned char *dst)
227 #ifdef __LITTLE_ENDIAN__
228 if ((count == 1) && dst[0] & 0x80) {
233 if ((count == 2) && dst[1] & 0x80) {
238 if ((count == 1) && dst[3] & 0x80) {
243 if ((count == 2) && dst[2] & 0x80) {
250 static struct mem_access user_mem_access = {
256 * handle an instruction that does an unaligned memory access by emulating the
258 * - note that PC _may not_ point to the faulting instruction
259 * (if that instruction is in a branch delay slot)
260 * - return 0 if emulation okay, -EFAULT on existential error
262 static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs,
263 struct mem_access *ma)
265 int ret, index, count;
266 unsigned long *rm, *rn;
267 unsigned char *src, *dst;
268 unsigned char __user *srcu, *dstu;
270 index = (instruction>>8)&15; /* 0x0F00 */
271 rn = ®s->regs[index];
273 index = (instruction>>4)&15; /* 0x00F0 */
274 rm = ®s->regs[index];
276 count = 1<<(instruction&3);
279 case 1: se_half += 1; break;
280 case 2: se_word += 1; break;
281 case 4: se_dword += 1; break;
282 case 8: se_multi += 1; break; /* ??? */
286 switch (instruction>>12) {
287 case 0: /* mov.[bwl] to/from memory via r0+rn */
288 if (instruction & 8) {
290 srcu = (unsigned char __user *)*rm;
291 srcu += regs->regs[0];
292 dst = (unsigned char *)rn;
293 *(unsigned long *)dst = 0;
295 #if !defined(__LITTLE_ENDIAN__)
298 if (ma->from(dst, srcu, count))
301 sign_extend(count, dst);
304 src = (unsigned char *)rm;
305 #if !defined(__LITTLE_ENDIAN__)
308 dstu = (unsigned char __user *)*rn;
309 dstu += regs->regs[0];
311 if (ma->to(dstu, src, count))
317 case 1: /* mov.l Rm,@(disp,Rn) */
318 src = (unsigned char*) rm;
319 dstu = (unsigned char __user *)*rn;
320 dstu += (instruction&0x000F)<<2;
322 if (ma->to(dstu, src, 4))
327 case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
330 src = (unsigned char*) rm;
331 dstu = (unsigned char __user *)*rn;
332 #if !defined(__LITTLE_ENDIAN__)
335 if (ma->to(dstu, src, count))
340 case 5: /* mov.l @(disp,Rm),Rn */
341 srcu = (unsigned char __user *)*rm;
342 srcu += (instruction & 0x000F) << 2;
343 dst = (unsigned char *)rn;
344 *(unsigned long *)dst = 0;
346 if (ma->from(dst, srcu, 4))
351 case 6: /* mov.[bwl] from memory, possibly with post-increment */
352 srcu = (unsigned char __user *)*rm;
355 dst = (unsigned char*) rn;
356 *(unsigned long*)dst = 0;
358 #if !defined(__LITTLE_ENDIAN__)
361 if (ma->from(dst, srcu, count))
363 sign_extend(count, dst);
368 switch ((instruction&0xFF00)>>8) {
369 case 0x81: /* mov.w R0,@(disp,Rn) */
370 src = (unsigned char *) ®s->regs[0];
371 #if !defined(__LITTLE_ENDIAN__)
374 dstu = (unsigned char __user *)*rm; /* called Rn in the spec */
375 dstu += (instruction & 0x000F) << 1;
377 if (ma->to(dstu, src, 2))
382 case 0x85: /* mov.w @(disp,Rm),R0 */
383 srcu = (unsigned char __user *)*rm;
384 srcu += (instruction & 0x000F) << 1;
385 dst = (unsigned char *) ®s->regs[0];
386 *(unsigned long *)dst = 0;
388 #if !defined(__LITTLE_ENDIAN__)
391 if (ma->from(dst, srcu, 2))
402 /* Argh. Address not only misaligned but also non-existent.
403 * Raise an EFAULT and see if it's trapped
405 die_if_no_fixup("Fault in unaligned fixup", regs, 0);
410 * emulate the instruction in the delay slot
411 * - fetches the instruction from PC+2
413 static inline int handle_delayslot(struct pt_regs *regs,
414 insn_size_t old_instruction,
415 struct mem_access *ma)
417 insn_size_t instruction;
418 void __user *addr = (void __user *)(regs->pc +
419 instruction_size(old_instruction));
421 if (copy_from_user(&instruction, addr, sizeof(instruction))) {
422 /* the instruction-fetch faulted */
427 die("delay-slot-insn faulting in handle_unaligned_delayslot",
431 return handle_unaligned_ins(instruction, regs, ma);
435 * handle an instruction that does an unaligned memory access
436 * - have to be careful of branch delay-slot instructions that fault
438 * - if the branch would be taken PC points to the branch
439 * - if the branch would not be taken, PC points to delay-slot
441 * - PC always points to delayed branch
442 * - return 0 if handled, -EFAULT if failed (may not return if in kernel)
445 /* Macros to determine offset from current PC for branch instructions */
446 /* Explicit type coercion is used to force sign extension where needed */
447 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
448 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
450 int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
451 struct mem_access *ma, int expected)
457 * XXX: We can't handle mixed 16/32-bit instructions yet
459 if (instruction_size(instruction) != 2)
462 index = (instruction>>8)&15; /* 0x0F00 */
463 rm = regs->regs[index];
465 /* shout about fixups */
466 if (!expected && printk_ratelimit())
467 printk(KERN_NOTICE "Fixing up unaligned %s access "
468 "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
469 user_mode(regs) ? "userspace" : "kernel",
470 current->comm, task_pid_nr(current),
471 (void *)regs->pc, instruction);
474 switch (instruction&0xF000) {
476 if (instruction==0x000B) {
478 ret = handle_delayslot(regs, instruction, ma);
482 else if ((instruction&0x00FF)==0x0023) {
484 ret = handle_delayslot(regs, instruction, ma);
488 else if ((instruction&0x00FF)==0x0003) {
490 ret = handle_delayslot(regs, instruction, ma);
492 regs->pr = regs->pc + 4;
497 /* mov.[bwl] to/from memory via r0+rn */
502 case 0x1000: /* mov.l Rm,@(disp,Rn) */
505 case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
509 if ((instruction&0x00FF)==0x002B) {
511 ret = handle_delayslot(regs, instruction, ma);
515 else if ((instruction&0x00FF)==0x000B) {
517 ret = handle_delayslot(regs, instruction, ma);
519 regs->pr = regs->pc + 4;
524 /* mov.[bwl] to/from memory via r0+rn */
529 case 0x5000: /* mov.l @(disp,Rm),Rn */
532 case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
535 case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
536 switch (instruction&0x0F00) {
537 case 0x0100: /* mov.w R0,@(disp,Rm) */
539 case 0x0500: /* mov.w @(disp,Rm),R0 */
541 case 0x0B00: /* bf lab - no delayslot*/
543 case 0x0F00: /* bf/s lab */
544 ret = handle_delayslot(regs, instruction, ma);
546 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
547 if ((regs->sr & 0x00000001) != 0)
548 regs->pc += 4; /* next after slot */
551 regs->pc += SH_PC_8BIT_OFFSET(instruction);
554 case 0x0900: /* bt lab - no delayslot */
556 case 0x0D00: /* bt/s lab */
557 ret = handle_delayslot(regs, instruction, ma);
559 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
560 if ((regs->sr & 0x00000001) == 0)
561 regs->pc += 4; /* next after slot */
564 regs->pc += SH_PC_8BIT_OFFSET(instruction);
570 case 0xA000: /* bra label */
571 ret = handle_delayslot(regs, instruction, ma);
573 regs->pc += SH_PC_12BIT_OFFSET(instruction);
576 case 0xB000: /* bsr label */
577 ret = handle_delayslot(regs, instruction, ma);
579 regs->pr = regs->pc + 4;
580 regs->pc += SH_PC_12BIT_OFFSET(instruction);
586 /* handle non-delay-slot instruction */
588 ret = handle_unaligned_ins(instruction, regs, ma);
590 regs->pc += instruction_size(instruction);
595 * Handle various address error exceptions:
596 * - instruction address error:
598 * PC >= 0x80000000 in user mode
599 * - data address error (read and write)
600 * misaligned data access
601 * access to >= 0x80000000 is user mode
602 * Unfortuntaly we can't distinguish between instruction address error
603 * and data address errors caused by read accesses.
605 asmlinkage void do_address_error(struct pt_regs *regs,
606 unsigned long writeaccess,
607 unsigned long address)
609 unsigned long error_code = 0;
612 insn_size_t instruction;
615 /* Intentional ifdef */
616 #ifdef CONFIG_CPU_HAS_SR_RB
617 error_code = lookup_exception_vector();
622 if (user_mode(regs)) {
623 int si_code = BUS_ADRERR;
630 if (copy_from_user(&instruction, (insn_size_t *)(regs->pc & ~1),
631 sizeof(instruction))) {
637 /* shout about userspace fixups */
639 printk(KERN_NOTICE "Unaligned userspace access "
640 "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
641 current->comm, current->pid, (void *)regs->pc,
651 regs->pc += instruction_size(instruction);
656 /* bad PC is not something we can fix */
658 si_code = BUS_ADRALN;
663 tmp = handle_unaligned_access(instruction, regs,
664 &user_mem_access, 0);
670 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned "
671 "access (PC %lx PR %lx)\n", current->comm, regs->pc,
674 info.si_signo = SIGBUS;
676 info.si_code = si_code;
677 info.si_addr = (void __user *)address;
678 force_sig_info(SIGBUS, &info, current);
683 die("unaligned program counter", regs, error_code);
686 if (copy_from_user(&instruction, (void __user *)(regs->pc),
687 sizeof(instruction))) {
688 /* Argh. Fault on the instruction itself.
689 This should never happen non-SMP
692 die("insn faulting in do_address_error", regs, 0);
695 if (se_kernmode_warn)
696 printk(KERN_NOTICE "Unaligned kernel access "
697 "on behalf of \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
698 current->comm, current->pid, (void *)regs->pc,
701 handle_unaligned_access(instruction, regs,
702 &user_mem_access, 0);
709 * SH-DSP support gerg@snapgear.com.
711 int is_dsp_inst(struct pt_regs *regs)
713 unsigned short inst = 0;
716 * Safe guard if DSP mode is already enabled or we're lacking
717 * the DSP altogether.
719 if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
722 get_user(inst, ((unsigned short *) regs->pc));
726 /* Check for any type of DSP or support instruction */
727 if ((inst == 0xf000) || (inst == 0x4000))
733 #define is_dsp_inst(regs) (0)
734 #endif /* CONFIG_SH_DSP */
736 #ifdef CONFIG_CPU_SH2A
737 asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
738 unsigned long r6, unsigned long r7,
739 struct pt_regs __regs)
744 case TRAP_DIVZERO_ERROR:
745 info.si_code = FPE_INTDIV;
747 case TRAP_DIVOVF_ERROR:
748 info.si_code = FPE_INTOVF;
752 force_sig_info(SIGFPE, &info, current);
756 asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
757 unsigned long r6, unsigned long r7,
758 struct pt_regs __regs)
760 struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
761 unsigned long error_code;
762 struct task_struct *tsk = current;
764 #ifdef CONFIG_SH_FPU_EMU
765 unsigned short inst = 0;
768 get_user(inst, (unsigned short*)regs->pc);
770 err = do_fpu_inst(inst, regs);
772 regs->pc += instruction_size(inst);
775 /* not a FPU inst. */
779 /* Check if it's a DSP instruction */
780 if (is_dsp_inst(regs)) {
781 /* Enable DSP mode, and restart instruction. */
784 tsk->thread.dsp_status.status |= SR_DSP;
789 error_code = lookup_exception_vector();
792 force_sig(SIGILL, tsk);
793 die_if_no_fixup("reserved instruction", regs, error_code);
796 #ifdef CONFIG_SH_FPU_EMU
797 static int emulate_branch(unsigned short inst, struct pt_regs *regs)
800 * bfs: 8fxx: PC+=d*2+4;
801 * bts: 8dxx: PC+=d*2+4;
802 * bra: axxx: PC+=D*2+4;
803 * bsr: bxxx: PC+=D*2+4 after PR=PC+4;
804 * braf:0x23: PC+=Rn*2+4;
805 * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
807 * jsr: 4x0b: PC=Rn after PR=PC+4;
810 if (((inst & 0xf000) == 0xb000) || /* bsr */
811 ((inst & 0xf0ff) == 0x0003) || /* bsrf */
812 ((inst & 0xf0ff) == 0x400b)) /* jsr */
813 regs->pr = regs->pc + 4;
815 if ((inst & 0xfd00) == 0x8d00) { /* bfs, bts */
816 regs->pc += SH_PC_8BIT_OFFSET(inst);
820 if ((inst & 0xe000) == 0xa000) { /* bra, bsr */
821 regs->pc += SH_PC_12BIT_OFFSET(inst);
825 if ((inst & 0xf0df) == 0x0003) { /* braf, bsrf */
826 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
830 if ((inst & 0xf0df) == 0x400b) { /* jmp, jsr */
831 regs->pc = regs->regs[(inst & 0x0f00) >> 8];
835 if ((inst & 0xffff) == 0x000b) { /* rts */
844 asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
845 unsigned long r6, unsigned long r7,
846 struct pt_regs __regs)
848 struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
850 struct task_struct *tsk = current;
852 if (kprobe_handle_illslot(regs->pc) == 0)
855 #ifdef CONFIG_SH_FPU_EMU
856 get_user(inst, (unsigned short *)regs->pc + 1);
857 if (!do_fpu_inst(inst, regs)) {
858 get_user(inst, (unsigned short *)regs->pc);
859 if (!emulate_branch(inst, regs))
861 /* fault in branch.*/
863 /* not a FPU inst. */
866 inst = lookup_exception_vector();
869 force_sig(SIGILL, tsk);
870 die_if_no_fixup("illegal slot instruction", regs, inst);
873 asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
874 unsigned long r6, unsigned long r7,
875 struct pt_regs __regs)
877 struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
880 ex = lookup_exception_vector();
881 die_if_kernel("exception", regs, ex);
884 #if defined(CONFIG_SH_STANDARD_BIOS)
885 void *gdb_vbr_vector;
887 static inline void __init gdb_vbr_init(void)
889 register unsigned long vbr;
892 * Read the old value of the VBR register to initialise
893 * the vector through which debug and BIOS traps are
894 * delegated by the Linux trap handler.
896 asm volatile("stc vbr, %0" : "=r" (vbr));
898 gdb_vbr_vector = (void *)(vbr + 0x100);
899 printk("Setting GDB trap vector to 0x%08lx\n",
900 (unsigned long)gdb_vbr_vector);
904 void __cpuinit per_cpu_trap_init(void)
906 extern void *vbr_base;
908 #ifdef CONFIG_SH_STANDARD_BIOS
909 if (raw_smp_processor_id() == 0)
913 /* NOTE: The VBR value should be at P1
914 (or P2, virtural "fixed" address space).
915 It's definitely should not in physical address. */
917 asm volatile("ldc %0, vbr"
923 void *set_exception_table_vec(unsigned int vec, void *handler)
925 extern void *exception_handling_table[];
928 old_handler = exception_handling_table[vec];
929 exception_handling_table[vec] = handler;
933 void __init trap_init(void)
935 set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
936 set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
938 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
939 defined(CONFIG_SH_FPU_EMU)
941 * For SH-4 lacking an FPU, treat floating point instructions as
942 * reserved. They'll be handled in the math-emu case, or faulted on
945 set_exception_table_evt(0x800, do_reserved_inst);
946 set_exception_table_evt(0x820, do_illegal_slot_inst);
947 #elif defined(CONFIG_SH_FPU)
948 #ifdef CONFIG_CPU_SUBTYPE_SHX3
949 set_exception_table_evt(0xd80, fpu_state_restore_trap_handler);
950 set_exception_table_evt(0xda0, fpu_state_restore_trap_handler);
952 set_exception_table_evt(0x800, fpu_state_restore_trap_handler);
953 set_exception_table_evt(0x820, fpu_state_restore_trap_handler);
957 #ifdef CONFIG_CPU_SH2
958 set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler);
960 #ifdef CONFIG_CPU_SH2A
961 set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error);
962 set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error);
964 set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler);
969 set_exception_table_vec(TRAP_UBC, break_point_trap);
972 /* Setup VBR for boot cpu */
976 void show_stack(struct task_struct *tsk, unsigned long *sp)
983 sp = (unsigned long *)current_stack_pointer;
985 sp = (unsigned long *)tsk->thread.sp;
987 stack = (unsigned long)sp;
988 dump_mem("Stack: ", stack, THREAD_SIZE +
989 (unsigned long)task_stack_page(tsk));
990 show_trace(tsk, sp, NULL);
993 void dump_stack(void)
995 show_stack(NULL, NULL);
997 EXPORT_SYMBOL(dump_stack);
999 #ifdef CONFIG_PROC_FS
1001 * This needs to be done after sysctl_init, otherwise sys/ will be
1002 * overwritten. Actually, this shouldn't be in sys/ at all since
1003 * it isn't a sysctl, and it doesn't contain sysctl information.
1004 * We now locate it in /proc/cpu/alignment instead.
1006 static int __init alignment_init(void)
1008 struct proc_dir_entry *dir, *res;
1010 dir = proc_mkdir("cpu", NULL);
1014 res = create_proc_entry("alignment", S_IWUSR | S_IRUGO, dir);
1018 res->read_proc = proc_alignment_read;
1019 res->write_proc = proc_alignment_write;
1021 res = create_proc_entry("kernel_alignment", S_IWUSR | S_IRUGO, dir);
1025 res->read_proc = proc_alignment_read;
1026 res->write_proc = proc_alignment_kern_write;
1031 fs_initcall(alignment_init);