4 * Copyright (C) 2009 Renesas Solutions Corp.
6 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
8 * Based on SH7723 Setup
9 * Copyright (C) 2008 Paul Mundt
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
15 #include <linux/platform_device.h>
16 #include <linux/init.h>
17 #include <linux/serial.h>
19 #include <linux/serial_sci.h>
20 #include <linux/uio_driver.h>
21 #include <linux/sh_timer.h>
23 #include <asm/clock.h>
24 #include <asm/mmzone.h>
27 static struct plat_sci_port sci_platform_data[] = {
29 .mapbase = 0xffe00000,
30 .flags = UPF_BOOT_AUTOCONF,
32 .irqs = { 80, 80, 80, 80 },
34 .mapbase = 0xffe10000,
35 .flags = UPF_BOOT_AUTOCONF,
37 .irqs = { 81, 81, 81, 81 },
39 .mapbase = 0xffe20000,
40 .flags = UPF_BOOT_AUTOCONF,
42 .irqs = { 82, 82, 82, 82 },
44 .mapbase = 0xa4e30000,
45 .flags = UPF_BOOT_AUTOCONF,
47 .irqs = { 56, 56, 56, 56 },
49 .mapbase = 0xa4e40000,
50 .flags = UPF_BOOT_AUTOCONF,
52 .irqs = { 88, 88, 88, 88 },
54 .mapbase = 0xa4e50000,
55 .flags = UPF_BOOT_AUTOCONF,
57 .irqs = { 109, 109, 109, 109 },
63 static struct platform_device sci_device = {
67 .platform_data = sci_platform_data,
72 static struct resource rtc_resources[] = {
75 .end = 0xa465fec0 + 0x58 - 1,
76 .flags = IORESOURCE_IO,
81 .flags = IORESOURCE_IRQ,
86 .flags = IORESOURCE_IRQ,
91 .flags = IORESOURCE_IRQ,
95 static struct platform_device rtc_device = {
98 .num_resources = ARRAY_SIZE(rtc_resources),
99 .resource = rtc_resources,
103 static struct resource iic0_resources[] = {
107 .end = 0x04470018 - 1,
108 .flags = IORESOURCE_MEM,
113 .flags = IORESOURCE_IRQ,
117 static struct platform_device iic0_device = {
118 .name = "i2c-sh_mobile",
119 .id = 0, /* "i2c0" clock */
120 .num_resources = ARRAY_SIZE(iic0_resources),
121 .resource = iic0_resources,
125 static struct resource iic1_resources[] = {
129 .end = 0x04750018 - 1,
130 .flags = IORESOURCE_MEM,
135 .flags = IORESOURCE_IRQ,
139 static struct platform_device iic1_device = {
140 .name = "i2c-sh_mobile",
141 .id = 1, /* "i2c1" clock */
142 .num_resources = ARRAY_SIZE(iic1_resources),
143 .resource = iic1_resources,
147 static struct uio_info vpu_platform_data = {
153 static struct resource vpu_resources[] = {
158 .flags = IORESOURCE_MEM,
161 /* place holder for contiguous memory */
165 static struct platform_device vpu_device = {
166 .name = "uio_pdrv_genirq",
169 .platform_data = &vpu_platform_data,
171 .resource = vpu_resources,
172 .num_resources = ARRAY_SIZE(vpu_resources),
176 static struct uio_info veu0_platform_data = {
182 static struct resource veu0_resources[] = {
186 .end = 0xfe9200cb - 1,
187 .flags = IORESOURCE_MEM,
190 /* place holder for contiguous memory */
194 static struct platform_device veu0_device = {
195 .name = "uio_pdrv_genirq",
198 .platform_data = &veu0_platform_data,
200 .resource = veu0_resources,
201 .num_resources = ARRAY_SIZE(veu0_resources),
205 static struct uio_info veu1_platform_data = {
211 static struct resource veu1_resources[] = {
215 .end = 0xfe9240cb - 1,
216 .flags = IORESOURCE_MEM,
219 /* place holder for contiguous memory */
223 static struct platform_device veu1_device = {
224 .name = "uio_pdrv_genirq",
227 .platform_data = &veu1_platform_data,
229 .resource = veu1_resources,
230 .num_resources = ARRAY_SIZE(veu1_resources),
233 static struct sh_timer_config cmt_platform_data = {
235 .channel_offset = 0x60,
238 .clockevent_rating = 125,
239 .clocksource_rating = 200,
242 static struct resource cmt_resources[] = {
247 .flags = IORESOURCE_MEM,
251 .flags = IORESOURCE_IRQ,
255 static struct platform_device cmt_device = {
259 .platform_data = &cmt_platform_data,
261 .resource = cmt_resources,
262 .num_resources = ARRAY_SIZE(cmt_resources),
265 static struct platform_device *sh7724_devices[] __initdata = {
276 static int __init sh7724_devices_setup(void)
278 clk_always_enable("vpu0"); /* VPU */
279 clk_always_enable("veu1"); /* VEU3F1 */
280 clk_always_enable("veu0"); /* VEU3F0 */
282 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
283 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
284 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
286 return platform_add_devices(sh7724_devices,
287 ARRAY_SIZE(sh7724_devices));
289 device_initcall(sh7724_devices_setup);
291 static struct platform_device *sh7724_early_devices[] __initdata = {
295 void __init plat_early_device_setup(void)
297 early_platform_add_devices(sh7724_early_devices,
298 ARRAY_SIZE(sh7724_early_devices));
304 /* interrupt sources */
305 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
307 DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3,
308 _2DG_TRI, _2DG_INI, _2DG_CEI, _2DG_BRK,
309 DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3,
310 VIO_CEU20I, VIO_BEU20I, VIO_VEU3F1, VIO_VOUI,
318 RTC_ATI, RTC_PRI, RTC_CUI,
319 DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR,
320 DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR,
322 SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,
324 MSIOF_MSIOFI0, MSIOF_MSIOFI1,
325 SPU_SPUI0, SPU_SPUI1,
329 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
330 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
331 SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2,
337 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
339 SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2,
341 MMC_MMCI0, MMC_MMCI1, MMC_MMCI2,
343 TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
345 /* interrupt groups */
346 DMAC1A, _2DG, DMAC0A, VIO, RTC,
347 DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMC,
350 static struct intc_vect vectors[] __initdata = {
351 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
352 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
353 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
354 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
356 INTC_VECT(DMAC1A_DEI0, 0x700),
357 INTC_VECT(DMAC1A_DEI1, 0x720),
358 INTC_VECT(DMAC1A_DEI2, 0x740),
359 INTC_VECT(DMAC1A_DEI3, 0x760),
361 INTC_VECT(_2DG_TRI, 0x780),
362 INTC_VECT(_2DG_INI, 0x7A0),
363 INTC_VECT(_2DG_CEI, 0x7C0),
364 INTC_VECT(_2DG_BRK, 0x7E0),
366 INTC_VECT(DMAC0A_DEI0, 0x800),
367 INTC_VECT(DMAC0A_DEI1, 0x820),
368 INTC_VECT(DMAC0A_DEI2, 0x840),
369 INTC_VECT(DMAC0A_DEI3, 0x860),
371 INTC_VECT(VIO_CEU20I, 0x880),
372 INTC_VECT(VIO_BEU20I, 0x8A0),
373 INTC_VECT(VIO_VEU3F1, 0x8C0),
374 INTC_VECT(VIO_VOUI, 0x8E0),
376 INTC_VECT(SCIFA_SCIFA0, 0x900),
377 INTC_VECT(VPU_VPUI, 0x980),
378 INTC_VECT(TPU_TPUI, 0x9A0),
379 INTC_VECT(CEU21I, 0x9E0),
380 INTC_VECT(BEU21I, 0xA00),
381 INTC_VECT(USB_USI0, 0xA20),
382 INTC_VECT(ATAPI, 0xA60),
384 INTC_VECT(RTC_ATI, 0xA80),
385 INTC_VECT(RTC_PRI, 0xAA0),
386 INTC_VECT(RTC_CUI, 0xAC0),
388 INTC_VECT(DMAC1B_DEI4, 0xB00),
389 INTC_VECT(DMAC1B_DEI5, 0xB20),
390 INTC_VECT(DMAC1B_DADERR, 0xB40),
392 INTC_VECT(DMAC0B_DEI4, 0xB80),
393 INTC_VECT(DMAC0B_DEI5, 0xBA0),
394 INTC_VECT(DMAC0B_DADERR, 0xBC0),
396 INTC_VECT(KEYSC_KEYI, 0xBE0),
397 INTC_VECT(SCIF_SCIF0, 0xC00),
398 INTC_VECT(SCIF_SCIF1, 0xC20),
399 INTC_VECT(SCIF_SCIF2, 0xC40),
400 INTC_VECT(VEU3F0I, 0xC60),
401 INTC_VECT(MSIOF_MSIOFI0, 0xC80),
402 INTC_VECT(MSIOF_MSIOFI1, 0xCA0),
403 INTC_VECT(SPU_SPUI0, 0xCC0),
404 INTC_VECT(SPU_SPUI1, 0xCE0),
405 INTC_VECT(SCIFA_SCIFA1, 0xD00),
407 /* INTC_VECT(ICB_ICBI, 0xD20), */
408 INTC_VECT(ETHI, 0xD60),
410 INTC_VECT(I2C1_ALI, 0xD80),
411 INTC_VECT(I2C1_TACKI, 0xDA0),
412 INTC_VECT(I2C1_WAITI, 0xDC0),
413 INTC_VECT(I2C1_DTEI, 0xDE0),
415 INTC_VECT(I2C0_ALI, 0xE00),
416 INTC_VECT(I2C0_TACKI, 0xE20),
417 INTC_VECT(I2C0_WAITI, 0xE40),
418 INTC_VECT(I2C0_DTEI, 0xE60),
420 INTC_VECT(SDHI0_SDHII0, 0xE80),
421 INTC_VECT(SDHI0_SDHII1, 0xEA0),
422 INTC_VECT(SDHI0_SDHII2, 0xEC0),
424 INTC_VECT(CMT_CMTI, 0xF00),
425 INTC_VECT(TSIF_TSIFI, 0xF20),
426 /* INTC_VECT(ICB_LMBI, 0xF60), */
427 INTC_VECT(FSI_FSI, 0xF80),
428 INTC_VECT(SCIFA_SCIFA2, 0xFA0),
430 INTC_VECT(TMU0_TUNI0, 0x400),
431 INTC_VECT(TMU0_TUNI1, 0x420),
432 INTC_VECT(TMU0_TUNI2, 0x440),
434 INTC_VECT(IRDA_IRDAI, 0x480),
436 INTC_VECT(SDHI1_SDHII0, 0x4E0),
437 INTC_VECT(SDHI1_SDHII1, 0x500),
438 INTC_VECT(SDHI1_SDHII2, 0x520),
440 INTC_VECT(JPU_JPUI, 0x560),
442 INTC_VECT(MMC_MMCI0, 0x580),
443 INTC_VECT(MMC_MMCI1, 0x5A0),
444 INTC_VECT(MMC_MMCI2, 0x5C0),
446 INTC_VECT(LCDC_LCDCI, 0xF40),
448 INTC_VECT(TMU1_TUNI0, 0x920),
449 INTC_VECT(TMU1_TUNI1, 0x940),
450 INTC_VECT(TMU1_TUNI2, 0x960),
453 static struct intc_group groups[] __initdata = {
454 INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3),
455 INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI, _2DG_BRK),
456 INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3),
457 INTC_GROUP(VIO, VIO_CEU20I, VIO_BEU20I, VIO_VEU3F1, VIO_VOUI),
458 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
459 INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR),
460 INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR),
461 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
462 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
463 INTC_GROUP(SDHI0, SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2),
464 INTC_GROUP(SDHI1, SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2),
465 INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1),
466 INTC_GROUP(MMC, MMC_MMCI0, MMC_MMCI1, MMC_MMCI2),
469 /* FIXMEEEEEEEEEEEEEEEEEEE !!!!! */
470 /* very bad manual !! */
471 static struct intc_mask_reg mask_registers[] __initdata = {
472 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
473 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
474 /*SDHII3?*/0, SDHI1_SDHII2, SDHI1_SDHII1, SDHI1_SDHII0 } },
475 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
476 { VIO_VOUI, VIO_VEU3F1, VIO_BEU20I, VIO_CEU20I,
477 DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } },
478 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
479 { 0, 0, 0, VPU_VPUI, ATAPI, ETHI, 0, /*SCIFA3*/SCIFA_SCIFA0 } },
480 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
481 { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0,
482 SPU_SPUI1, SPU_SPUI0, BEU21I, IRDA_IRDAI } },
483 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
484 { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0,
485 JPU_JPUI, 0, 0, LCDC_LCDCI } },
486 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
487 { KEYSC_KEYI, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4,
488 VEU3F0I, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } },
489 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
490 { 0, 0, /*ICB_ICBI*/0, /*SCIFA4*/SCIFA_SCIFA1,
491 CEU21I, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } },
492 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
493 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
494 I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } },
495 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
496 { /*SDHII3*/0, SDHI0_SDHII2, SDHI0_SDHII1, SDHI0_SDHII0,
497 0, 0, /*SCIFA5*/SCIFA_SCIFA2, FSI_FSI } },
498 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
499 { 0, 0, 0, CMT_CMTI, 0, /*USB1*/0, USB_USI0, 0 } },
500 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
501 { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4,
502 0, RTC_ATI, RTC_PRI, RTC_CUI } },
503 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
504 { _2DG_BRK, _2DG_CEI, _2DG_INI, _2DG_TRI,
505 0, TPU_TPUI, /*ICB_LMBI*/0, TSIF_TSIFI } },
506 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
507 { 0, 0, 0, 0, 0, 0, 0, 0/*2DDMAC*/ } },
508 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
509 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
512 static struct intc_prio_reg prio_registers[] __initdata = {
513 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1,
514 TMU0_TUNI2, IRDA_IRDAI } },
515 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU_JPUI, LCDC_LCDCI,
517 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1,
519 { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMC, 0, ATAPI } },
520 { 0xa4080010, 0, 16, 4, /* IPRE */
521 { DMAC0A, /*BEU?VEU?*/VIO, /*SCIFA3*/SCIFA_SCIFA0, /*VPU5F*/
523 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B,
524 USB_USI0, CMT_CMTI } },
525 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1,
526 SCIF_SCIF2, VEU3F0I } },
527 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1,
529 { 0xa4080020, 0, 16, 4, /* IPRI */ { /*SCIFA4*/SCIFA_SCIFA1, /*ICB*/0,
530 TSIF_TSIFI, _2DG/*ICB?*/ } },
531 { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU21I, ETHI, FSI_FSI, SDHI1 } },
532 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, /*ICB?*/0, SDHI0 } },
533 { 0xa408002c, 0, 16, 4, /* IPRL */ { /*SCIFA5*/SCIFA_SCIFA2, 0,
534 TPU_TPUI, /*2DDMAC*/0 } },
535 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
536 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
539 static struct intc_sense_reg sense_registers[] __initdata = {
540 { 0xa414001c, 16, 2, /* ICR1 */
541 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
544 static struct intc_mask_reg ack_registers[] __initdata = {
545 { 0xa4140024, 0, 8, /* INTREQ00 */
546 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
549 static DECLARE_INTC_DESC_ACK(intc_desc, "sh7724", vectors, groups,
550 mask_registers, prio_registers, sense_registers,
553 void __init plat_irq_setup(void)
555 register_intc_controller(&intc_desc);