4 * Copyright (C) 2006 - 2008 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/serial_sci.h>
15 #include <linux/uio_driver.h>
16 #include <linux/usb/m66592.h>
17 #include <linux/sh_timer.h>
18 #include <asm/clock.h>
19 #include <asm/mmzone.h>
20 #include <asm/dma-sh.h>
21 #include <cpu/sh7722.h>
24 static struct plat_sci_port scif0_platform_data = {
25 .mapbase = 0xffe00000,
26 .flags = UPF_BOOT_AUTOCONF,
28 .irqs = { 80, 80, 80, 80 },
32 static struct platform_device scif0_device = {
36 .platform_data = &scif0_platform_data,
40 static struct plat_sci_port scif1_platform_data = {
41 .mapbase = 0xffe10000,
42 .flags = UPF_BOOT_AUTOCONF,
44 .irqs = { 81, 81, 81, 81 },
48 static struct platform_device scif1_device = {
52 .platform_data = &scif1_platform_data,
56 static struct plat_sci_port scif2_platform_data = {
57 .mapbase = 0xffe20000,
58 .flags = UPF_BOOT_AUTOCONF,
60 .irqs = { 82, 82, 82, 82 },
64 static struct platform_device scif2_device = {
68 .platform_data = &scif2_platform_data,
72 static struct resource rtc_resources[] = {
75 .end = 0xa465fec0 + 0x58 - 1,
76 .flags = IORESOURCE_IO,
81 .flags = IORESOURCE_IRQ,
86 .flags = IORESOURCE_IRQ,
91 .flags = IORESOURCE_IRQ,
95 static struct platform_device rtc_device = {
98 .num_resources = ARRAY_SIZE(rtc_resources),
99 .resource = rtc_resources,
101 .hwblk_id = HWBLK_RTC,
105 static struct m66592_platdata usbf_platdata = {
109 static struct resource usbf_resources[] = {
114 .flags = IORESOURCE_MEM,
119 .flags = IORESOURCE_IRQ,
123 static struct platform_device usbf_device = {
124 .name = "m66592_udc",
125 .id = 0, /* "usbf0" clock */
128 .coherent_dma_mask = 0xffffffff,
129 .platform_data = &usbf_platdata,
131 .num_resources = ARRAY_SIZE(usbf_resources),
132 .resource = usbf_resources,
134 .hwblk_id = HWBLK_USBF,
138 static struct resource iic_resources[] = {
143 .flags = IORESOURCE_MEM,
148 .flags = IORESOURCE_IRQ,
152 static struct platform_device iic_device = {
153 .name = "i2c-sh_mobile",
154 .id = 0, /* "i2c0" clock */
155 .num_resources = ARRAY_SIZE(iic_resources),
156 .resource = iic_resources,
158 .hwblk_id = HWBLK_IIC,
162 static struct uio_info vpu_platform_data = {
168 static struct resource vpu_resources[] = {
173 .flags = IORESOURCE_MEM,
176 /* place holder for contiguous memory */
180 static struct platform_device vpu_device = {
181 .name = "uio_pdrv_genirq",
184 .platform_data = &vpu_platform_data,
186 .resource = vpu_resources,
187 .num_resources = ARRAY_SIZE(vpu_resources),
189 .hwblk_id = HWBLK_VPU,
193 static struct uio_info veu_platform_data = {
199 static struct resource veu_resources[] = {
204 .flags = IORESOURCE_MEM,
207 /* place holder for contiguous memory */
211 static struct platform_device veu_device = {
212 .name = "uio_pdrv_genirq",
215 .platform_data = &veu_platform_data,
217 .resource = veu_resources,
218 .num_resources = ARRAY_SIZE(veu_resources),
220 .hwblk_id = HWBLK_VEU,
224 static struct uio_info jpu_platform_data = {
230 static struct resource jpu_resources[] = {
235 .flags = IORESOURCE_MEM,
238 /* place holder for contiguous memory */
242 static struct platform_device jpu_device = {
243 .name = "uio_pdrv_genirq",
246 .platform_data = &jpu_platform_data,
248 .resource = jpu_resources,
249 .num_resources = ARRAY_SIZE(jpu_resources),
251 .hwblk_id = HWBLK_JPU,
255 static struct sh_timer_config cmt_platform_data = {
257 .channel_offset = 0x60,
260 .clockevent_rating = 125,
261 .clocksource_rating = 125,
264 static struct resource cmt_resources[] = {
269 .flags = IORESOURCE_MEM,
273 .flags = IORESOURCE_IRQ,
277 static struct platform_device cmt_device = {
281 .platform_data = &cmt_platform_data,
283 .resource = cmt_resources,
284 .num_resources = ARRAY_SIZE(cmt_resources),
286 .hwblk_id = HWBLK_CMT,
290 static struct sh_timer_config tmu0_platform_data = {
292 .channel_offset = 0x04,
295 .clockevent_rating = 200,
298 static struct resource tmu0_resources[] = {
303 .flags = IORESOURCE_MEM,
307 .flags = IORESOURCE_IRQ,
311 static struct platform_device tmu0_device = {
315 .platform_data = &tmu0_platform_data,
317 .resource = tmu0_resources,
318 .num_resources = ARRAY_SIZE(tmu0_resources),
320 .hwblk_id = HWBLK_TMU,
324 static struct sh_timer_config tmu1_platform_data = {
326 .channel_offset = 0x10,
329 .clocksource_rating = 200,
332 static struct resource tmu1_resources[] = {
337 .flags = IORESOURCE_MEM,
341 .flags = IORESOURCE_IRQ,
345 static struct platform_device tmu1_device = {
349 .platform_data = &tmu1_platform_data,
351 .resource = tmu1_resources,
352 .num_resources = ARRAY_SIZE(tmu1_resources),
354 .hwblk_id = HWBLK_TMU,
358 static struct sh_timer_config tmu2_platform_data = {
360 .channel_offset = 0x1c,
365 static struct resource tmu2_resources[] = {
370 .flags = IORESOURCE_MEM,
374 .flags = IORESOURCE_IRQ,
378 static struct platform_device tmu2_device = {
382 .platform_data = &tmu2_platform_data,
384 .resource = tmu2_resources,
385 .num_resources = ARRAY_SIZE(tmu2_resources),
387 .hwblk_id = HWBLK_TMU,
391 static struct sh_dmae_pdata dma_platform_data = {
395 static struct platform_device dma_device = {
396 .name = "sh-dma-engine",
399 .platform_data = &dma_platform_data,
403 static struct platform_device *sh7722_devices[] __initdata = {
420 static int __init sh7722_devices_setup(void)
422 platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
423 platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
424 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
426 return platform_add_devices(sh7722_devices,
427 ARRAY_SIZE(sh7722_devices));
429 arch_initcall(sh7722_devices_setup);
431 static struct platform_device *sh7722_early_devices[] __initdata = {
441 void __init plat_early_device_setup(void)
443 early_platform_add_devices(sh7722_early_devices,
444 ARRAY_SIZE(sh7722_early_devices));
451 /* interrupt sources */
452 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
454 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
455 RTC_ATI, RTC_PRI, RTC_CUI,
456 DMAC0, DMAC1, DMAC2, DMAC3,
457 VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
459 USB_USBI0, USB_USBI1,
460 DMAC4, DMAC5, DMAC_DADERR,
462 SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
463 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
464 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
465 CMT, TSIF, SIU, TWODG,
469 /* interrupt groups */
470 SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
473 static struct intc_vect vectors[] __initdata = {
474 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
475 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
476 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
477 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
478 INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720),
479 INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760),
480 INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0),
481 INTC_VECT(RTC_CUI, 0x7c0),
482 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
483 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
484 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
485 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
486 INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),
487 INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40),
488 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
489 INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
490 INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20),
491 INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80),
492 INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00),
493 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
494 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
495 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
496 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
497 INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
498 INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
499 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
500 INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
501 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
502 INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480),
503 INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
506 static struct intc_group groups[] __initdata = {
507 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
508 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
509 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
510 INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
511 INTC_GROUP(USB, USB_USBI0, USB_USBI1),
512 INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
513 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
514 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
515 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
518 static struct intc_mask_reg mask_registers[] __initdata = {
519 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
521 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
522 { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
523 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
525 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
526 { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
527 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
528 { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
529 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
530 { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } },
531 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
532 { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } },
533 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
534 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
535 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
536 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
537 { 0, 0, ENABLED, ENABLED, 0, 0, TWODG, SIU } },
538 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
539 { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
540 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
542 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
543 { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },
544 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
545 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
548 static struct intc_prio_reg prio_registers[] __initdata = {
549 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
550 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
551 { 0xa4080008, 0, 16, 4, /* IPRC */ { } },
552 { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
553 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
554 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
555 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
556 { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
557 { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
558 { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
559 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
560 { 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
561 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
562 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
565 static struct intc_sense_reg sense_registers[] __initdata = {
566 { 0xa414001c, 16, 2, /* ICR1 */
567 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
570 static struct intc_mask_reg ack_registers[] __initdata = {
571 { 0xa4140024, 0, 8, /* INTREQ00 */
572 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
575 static struct intc_desc intc_desc __initdata = {
577 .force_enable = ENABLED,
578 .hw = INTC_HW_DESC(vectors, groups, mask_registers,
579 prio_registers, sense_registers, ack_registers),
582 void __init plat_irq_setup(void)
584 register_intc_controller(&intc_desc);
587 void __init plat_mem_setup(void)
589 /* Register the URAM space as Node 1 */
590 setup_bootmem_node(1, 0x055f0000, 0x05610000);