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   1 /*
   2  * arch/sh/kernel/cpu/sh4/probe.c
   3  *
   4  * CPU Subtype Probing for SH-4.
   5  *
   6  * Copyright (C) 2001 - 2007  Paul Mundt
   7  * Copyright (C) 2003  Richard Curnow
   8  *
   9  * This file is subject to the terms and conditions of the GNU General Public
  10  * License.  See the file "COPYING" in the main directory of this archive
  11  * for more details.
  12  */
  13 #include <linux/init.h>
  14 #include <linux/io.h>
  15 #include <asm/processor.h>
  16 #include <asm/cache.h>
  17
  18 int __init detect_cpu_and_cache_system(void)
  19 {
  20         unsigned long pvr, prr, cvr;
  21         unsigned long size;
  22
  23         static unsigned long sizes[16] = {
  24                 [1] = (1 << 12),
  25                 [2] = (1 << 13),
  26                 [4] = (1 << 14),
  27                 [8] = (1 << 15),
  28                 [9] = (1 << 16)
  29         };
  30
  31         pvr = (ctrl_inl(CCN_PVR) >> 8) & 0xffffff;
  32         prr = (ctrl_inl(CCN_PRR) >> 4) & 0xff;
  33         cvr = (ctrl_inl(CCN_CVR));
  34
  35         /*
  36          * Setup some sane SH-4 defaults for the icache
  37          */
  38         boot_cpu_data.icache.way_incr           = (1 << 13);
  39         boot_cpu_data.icache.entry_shift        = 5;
  40         boot_cpu_data.icache.sets               = 256;
  41         boot_cpu_data.icache.ways               = 1;
  42         boot_cpu_data.icache.linesz             = L1_CACHE_BYTES;
  43
  44         /*
  45          * And again for the dcache ..
  46          */
  47         boot_cpu_data.dcache.way_incr           = (1 << 14);
  48         boot_cpu_data.dcache.entry_shift        = 5;
  49         boot_cpu_data.dcache.sets               = 512;
  50         boot_cpu_data.dcache.ways               = 1;
  51         boot_cpu_data.dcache.linesz             = L1_CACHE_BYTES;
  52
  53         /* We don't know the chip cut */
  54         boot_cpu_data.cut_major = boot_cpu_data.cut_minor = -1;
  55
  56         /*
  57          * Setup some generic flags we can probe on SH-4A parts
  58          */
  59         if (((pvr >> 16) & 0xff) == 0x10) {
  60                 if ((cvr & 0x10000000) == 0)
  61                         boot_cpu_data.flags |= CPU_HAS_DSP;
  62
  63                 boot_cpu_data.flags |= CPU_HAS_LLSC;
  64                 boot_cpu_data.cut_major = pvr & 0x7f;
  65         }
  66
  67         /* FPU detection works for everyone */
  68         if ((cvr & 0x20000000) == 1)
  69                 boot_cpu_data.flags |= CPU_HAS_FPU;
  70
  71         /* Mask off the upper chip ID */
  72         pvr &= 0xffff;
  73
  74         /*
  75          * Probe the underlying processor version/revision and
  76          * adjust cpu_data setup accordingly.
  77          */
  78         switch (pvr) {
  79         case 0x205:
  80                 boot_cpu_data.type = CPU_SH7750;
  81                 boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
  82                                    CPU_HAS_PERF_COUNTER;
  83                 break;
  84         case 0x206:
  85                 boot_cpu_data.type = CPU_SH7750S;
  86                 boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
  87                                    CPU_HAS_PERF_COUNTER;
  88                 break;
  89         case 0x1100:
  90                 boot_cpu_data.type = CPU_SH7751;
  91                 boot_cpu_data.flags |= CPU_HAS_FPU;
  92                 break;
  93         case 0x2001:
  94         case 0x2004:
  95                 boot_cpu_data.type = CPU_SH7770;
  96                 boot_cpu_data.icache.ways = 4;
  97                 boot_cpu_data.dcache.ways = 4;
  98
  99                 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_LLSC;
 100                 break;
 101         case 0x2006:
 102         case 0x200A:
 103                 if (prr == 0x61)
 104                         boot_cpu_data.type = CPU_SH7781;
 105                 else if (prr == 0xa1)
 106                         boot_cpu_data.type = CPU_SH7763;
 107                 else
 108                         boot_cpu_data.type = CPU_SH7780;
 109
 110                 boot_cpu_data.icache.ways = 4;
 111                 boot_cpu_data.dcache.ways = 4;
 112
 113                 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
 114                                    CPU_HAS_LLSC;
 115                 break;
 116         case 0x3000:
 117         case 0x3003:
 118         case 0x3009:
 119                 boot_cpu_data.type = CPU_SH7343;
 120                 boot_cpu_data.icache.ways = 4;
 121                 boot_cpu_data.dcache.ways = 4;
 122                 boot_cpu_data.flags |= CPU_HAS_LLSC;
 123                 break;
 124         case 0x3004:
 125         case 0x3007:
 126                 boot_cpu_data.type = CPU_SH7785;
 127                 boot_cpu_data.icache.ways = 4;
 128                 boot_cpu_data.dcache.ways = 4;
 129                 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
 130                                           CPU_HAS_LLSC;
 131                 break;
 132         case 0x4004:
 133                 boot_cpu_data.type = CPU_SH7786;
 134                 boot_cpu_data.icache.ways = 4;
 135                 boot_cpu_data.dcache.ways = 4;
 136                 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
 137                         CPU_HAS_LLSC | CPU_HAS_PTEAEX | CPU_HAS_L2_CACHE;
 138                 break;
 139         case 0x3008:
 140                 boot_cpu_data.icache.ways = 4;
 141                 boot_cpu_data.dcache.ways = 4;
 142                 boot_cpu_data.flags |= CPU_HAS_LLSC;
 143
 144                 switch (prr) {
 145                 case 0x50:
 146                 case 0x51:
 147                         boot_cpu_data.type = CPU_SH7723;
 148                         boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_L2_CACHE;
 149                         break;
 150                 case 0x70:
 151                         boot_cpu_data.type = CPU_SH7366;
 152                         break;
 153                 case 0xa0:
 154                 case 0xa1:
 155                         boot_cpu_data.type = CPU_SH7722;
 156                         break;
 157                 }
 158                 break;
 159         case 0x300b:
 160                 boot_cpu_data.type = CPU_SH7724;
 161                 boot_cpu_data.icache.ways = 4;
 162                 boot_cpu_data.dcache.ways = 4;
 163                 boot_cpu_data.flags |= CPU_HAS_LLSC | CPU_HAS_FPU | CPU_HAS_L2_CACHE;
 164                 break;
 165         case 0x4000:    /* 1st cut */
 166         case 0x4001:    /* 2nd cut */
 167                 boot_cpu_data.type = CPU_SHX3;
 168                 boot_cpu_data.icache.ways = 4;
 169                 boot_cpu_data.dcache.ways = 4;
 170                 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
 171                                           CPU_HAS_LLSC;
 172                 break;
 173         case 0x700:
 174                 boot_cpu_data.type = CPU_SH4_501;
 175                 boot_cpu_data.icache.ways = 2;
 176                 boot_cpu_data.dcache.ways = 2;
 177                 break;
 178         case 0x600:
 179                 boot_cpu_data.type = CPU_SH4_202;
 180                 boot_cpu_data.icache.ways = 2;
 181                 boot_cpu_data.dcache.ways = 2;
 182                 boot_cpu_data.flags |= CPU_HAS_FPU;
 183                 break;
 184         case 0x500 ... 0x501:
 185                 switch (prr) {
 186                 case 0x10:
 187                         boot_cpu_data.type = CPU_SH7750R;
 188                         break;
 189                 case 0x11:
 190                         boot_cpu_data.type = CPU_SH7751R;
 191                         break;
 192                 case 0x50 ... 0x5f:
 193                         boot_cpu_data.type = CPU_SH7760;
 194                         break;
 195                 }
 196
 197                 boot_cpu_data.icache.ways = 2;
 198                 boot_cpu_data.dcache.ways = 2;
 199
 200                 boot_cpu_data.flags |= CPU_HAS_FPU;
 201
 202                 break;
 203         default:
 204                 boot_cpu_data.type = CPU_SH_NONE;
 205                 break;
 206         }
 207
 208 #ifdef CONFIG_CPU_HAS_PTEA
 209         boot_cpu_data.flags |= CPU_HAS_PTEA;
 210 #endif
 211
 212         /*
 213          * On anything that's not a direct-mapped cache, look to the CVR
 214          * for I/D-cache specifics.
 215          */
 216         if (boot_cpu_data.icache.ways > 1) {
 217                 size = sizes[(cvr >> 20) & 0xf];
 218                 boot_cpu_data.icache.way_incr   = (size >> 1);
 219                 boot_cpu_data.icache.sets       = (size >> 6);
 220
 221         }
 222
 223         /* And the rest of the D-cache */
 224         if (boot_cpu_data.dcache.ways > 1) {
 225                 size = sizes[(cvr >> 16) & 0xf];
 226                 boot_cpu_data.dcache.way_incr   = (size >> 1);
 227                 boot_cpu_data.dcache.sets       = (size >> 6);
 228         }
 229
 230         /*
 231          * SH-4A's have an optional PIPT L2.
 232          */
 233         if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
 234                 /*
 235                  * Verify that it really has something hooked up, this
 236                  * is the safety net for CPUs that have optional L2
 237                  * support yet do not implement it.
 238                  */
 239                 if ((cvr & 0xf) == 0)
 240                         boot_cpu_data.flags &= ~CPU_HAS_L2_CACHE;
 241                 else {
 242                         /*
 243                          * Silicon and specifications have clearly never
 244                          * met..
 245                          */
 246                         cvr ^= 0xf;
 247
 248                         /*
 249                          * Size calculation is much more sensible
 250                          * than it is for the L1.
 251                          *
 252                          * Sizes are 128KB, 258KB, 512KB, and 1MB.
 253                          */
 254                         size = (cvr & 0xf) << 17;
 255
 256                         boot_cpu_data.scache.way_incr           = (1 << 16);
 257                         boot_cpu_data.scache.entry_shift        = 5;
 258                         boot_cpu_data.scache.ways               = 4;
 259                         boot_cpu_data.scache.linesz             = L1_CACHE_BYTES;
 260
 261                         boot_cpu_data.scache.entry_mask =
 262                                 (boot_cpu_data.scache.way_incr -
 263                                  boot_cpu_data.scache.linesz);
 264
 265                         boot_cpu_data.scache.sets       = size /
 266                                 (boot_cpu_data.scache.linesz *
 267                                  boot_cpu_data.scache.ways);
 268
 269                         boot_cpu_data.scache.way_size   =
 270                                 (boot_cpu_data.scache.sets *
 271                                  boot_cpu_data.scache.linesz);
 272                 }
 273         }
 274
 275         return 0;
 276 }