2 * arch/sh/kernel/cpu/sh3/entry.S
4 * Copyright (C) 1999, 2000, 2002 Niibe Yutaka
5 * Copyright (C) 2003 - 2006 Paul Mundt
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
11 #include <linux/sys.h>
12 #include <linux/errno.h>
13 #include <linux/linkage.h>
14 #include <asm/asm-offsets.h>
15 #include <asm/thread_info.h>
16 #include <asm/unistd.h>
17 #include <cpu/mmu_context.h>
19 #include <asm/cache.h>
22 ! GNU as (as of 2.9.1) changes bf/s into bt/s and bra, when the address
23 ! to be jumped is too far, but it causes illegal slot exception.
26 * entry.S contains the system-call and fault low-level handling routines.
27 * This also contains the timer-interrupt handler, as well as all interrupts
28 * and faults that can result in a task-switch.
30 * NOTE: This code handles signal-recognition, which happens every time
31 * after a timer-interrupt and after each system call.
33 * NOTE: This code uses a convention that instructions in the delay slot
34 * of a transfer-control instruction are indented by an extra space, thus:
36 * jmp @k0 ! control-transfer instruction
37 * ldc k1, ssr ! delay slot
39 * Stack layout in 'ret_from_syscall':
40 * ptrace needs to have all regs on the stack.
41 * if the order here is changed, it needs to be
42 * updated in ptrace.c and ptrace.h
56 #if defined(CONFIG_KGDB)
57 NMI_VEC = 0x1c0 ! Must catch early for debounce
60 /* Offsets to the stack */
61 OFF_R0 = 0 /* Return value. New ABI also arg4 */
62 OFF_R1 = 4 /* New ABI: arg5 */
63 OFF_R2 = 8 /* New ABI: arg6 */
64 OFF_R3 = 12 /* New ABI: syscall_nr */
65 OFF_R4 = 16 /* New ABI: arg0 */
66 OFF_R5 = 20 /* New ABI: arg1 */
67 OFF_R6 = 24 /* New ABI: arg2 */
68 OFF_R7 = 28 /* New ABI: arg3 */
81 #define g_imask r6 /* r6_bank1 */
82 #define k_g_imask r6_bank /* r6_bank1 */
83 #define current r7 /* r7_bank1 */
85 #include <asm/entry-macros.S>
88 * Kernel mode register usage:
91 * k2 scratch (Exception code)
92 * k3 scratch (Return address)
95 * k6 Global Interrupt Mask (0--15 << 4)
96 * k7 CURRENT_THREAD_INFO (pointer to current thread info)
100 ! TLB Miss / Initial Page write exception handling
102 ! TLB hits, but the access violate the protection.
103 ! It can be valid access, such as stack grow and/or C-O-W.
106 ! Find the pmd/pte entry and loadtlb
107 ! If it's not found, cause address error (SEGV)
109 ! Although this could be written in assembly language (and it'd be faster),
110 ! this first version depends *much* on C implementation.
113 #if defined(CONFIG_MMU)
116 bra call_handle_tlbmiss
120 ENTRY(tlb_miss_store)
121 bra call_handle_tlbmiss
125 ENTRY(initial_page_write)
126 bra call_handle_tlbmiss
130 ENTRY(tlb_protection_violation_load)
131 bra call_do_page_fault
135 ENTRY(tlb_protection_violation_store)
136 bra call_do_page_fault
169 2: .long handle_tlbmiss
170 3: .long do_page_fault
171 4: .long ret_from_exception
174 ENTRY(address_error_load)
176 mov #0,r5 ! writeaccess = 0
179 ENTRY(address_error_store)
181 mov #1,r5 ! writeaccess = 1
186 mov.l @r0, r6 ! address
193 2: .long do_address_error
194 #endif /* CONFIG_MMU */
196 #if defined(CONFIG_SH_STANDARD_BIOS)
197 /* Unwind the stack and jmp to the debug entry */
198 ENTRY(sh_bios_handler)
203 lds k2, pr ! restore pr
212 2: .long gdb_vbr_vector
213 #endif /* CONFIG_SH_STANDARD_BIOS */
216 ! - restore r0, r1, r2, r3, r4, r5, r6, r7 from the stack
218 ! - restore r8, r9, r10, r11, r12, r13, r14, r15 from the stack
219 ! - restore spc, pr*, ssr, gbr, mach, macl, skip default tra
220 ! k2 returns original pr
221 ! k3 returns original sr
222 ! k4 returns original stack pointer
223 ! r8 passes SR bitmask, overwritten with restored data on return
225 ! BL=0 on entry, on exit BL=1 (depending on r8).
248 mov.l @r15+, k4 ! original stack pointer
250 mov.l @r15+, k2 ! original PR
251 mov.l @r15+, k3 ! original SR
256 add #4, r15 ! Skip syscall number
263 lds k2, pr ! restore pr
265 ! Calculate new SR value
266 mov k3, k2 ! original SR value
270 and k1, k2 ! Mask original SR value
272 mov k3, k0 ! Calculate IMASK-bits
280 6: or k0, k2 ! Set the IMASK-bits
283 #if defined(CONFIG_KGDB)
294 5: .long 0x00001000 ! DSP
300 ! common exception handler
301 #include "../../entry-common.S"
303 ! Exception Vector Base
305 ! Should be aligned page boundary.
311 ! 0x100: General exception vector
315 #ifndef CONFIG_CPU_SUBTYPE_SHX3
317 sts pr, k3 ! save original pr value in k3
322 ! Is EXPEVT larger than 0x800?
328 ! then add 0x580 (k2 is 0xd80 or 0xda0)
334 ! Setup stack and save DSP context (k0 contains original r15 on return)
338 ! Save registers / Switch to bank 0
339 mov k4, k2 ! keep vector in k2
340 mov.l 1f, k4 ! SR bits to clear in k4
341 bsr save_regs ! needs original pr value in k3
344 bra handle_exception_special
353 ! - switch to kernel stack
354 ! k0 returns original sp (after roll back)
360 ! Check for roll back gRB (User and Kernel)
368 cmp/hs k0, k1 ! test k1 (saved PC) >= k0 (saved r0)
374 ldc k0, spc ! PC = saved r0 + r15 - 2
375 2: mov k1, r15 ! SP = r1
378 ! Switch to kernel stack if needed
379 stc ssr, k0 ! Is it from kernel space?
380 shll k0 ! Check MD bit (bit30) by shifting it into...
381 shll k0 ! ...the T bit
382 bt/s 1f ! It's a kernel to kernel transition.
383 mov r15, k0 ! save original stack to k0
384 /* User space to kernel */
385 mov #(THREAD_SIZE >> 10), k1
386 shll8 k1 ! k1 := THREAD_SIZE
389 mov k1, r15 ! change to kernel stack
396 ! 0x400: Instruction and Data TLB miss exception vector
400 sts pr, k3 ! save original pr value in k3
403 mova exception_data, k0
405 ! Setup stack and save DSP context (k0 contains original r15 on return)
409 ! Save registers / Switch to bank 0
410 mov.l 5f, k2 ! vector register address
411 mov.l 1f, k4 ! SR bits to clear in k4
412 bsr save_regs ! needs original pr value in k3
413 mov.l @k2, k2 ! read out vector and keep in k2
415 handle_exception_special:
416 ! Setup return address and jump to exception handler
417 mov.l 7f, r9 ! fetch return address
418 stc r2_bank, r0 ! k2 (vector)
422 mov.l @(r0, r10), r10
424 lds r9, pr ! put return address in pr
426 .align L1_CACHE_SHIFT
429 ! - save default tra, macl, mach, gbr, ssr, pr* and spc on the stack
430 ! - save r15*, r14, r13, r12, r11, r10, r9, r8 on the stack
432 ! - save r7, r6, r5, r4, r3, r2, r1, r0 on the stack
433 ! k0 contains original stack pointer*
435 ! k3 passes original pr*
436 ! k4 passes SR bitmask
437 ! BL=1 on entry, on exit BL=0.
441 mov.l k1, @-r15 ! set TRA (default: -1)
446 mov.l k3, @-r15 ! original pr in k3
449 mov.l k0, @-r15 ! original stack pointer in k0
458 mov.l 0f, k3 ! SR bits to set in k3
463 ! - modify SR for bank switch
464 ! - save r7, r6, r5, r4, r3, r2, r1, r0 on the stack
465 ! k3 passes bits to set in SR
466 ! k4 passes bits to clear in SR
485 ! 0x600: Interrupt / NMI vector
488 ENTRY(handle_interrupt)
489 #if defined(CONFIG_KGDB)
491 ! Debounce (filter nested NMI)
505 #endif /* defined(CONFIG_KGDB) */
506 sts pr, k3 ! save original pr value in k3
507 mova exception_data, k0
509 ! Setup stack and save DSP context (k0 contains original r15 on return)
513 ! Save registers / Switch to bank 0
514 mov.l 1f, k4 ! SR bits to clear in k4
515 bsr save_regs ! needs original pr value in k3
516 mov #-1, k2 ! default vector kept in k2
518 ! Setup return address and jump to do_IRQ
519 mov.l 4f, r9 ! fetch return address
520 lds r9, pr ! put return address in pr
523 mov.l @r4, r4 ! pass INTEVT vector as arg0
525 mov r15, r5 ! pass saved registers as arg1
527 ENTRY(exception_none)
531 .align L1_CACHE_SHIFT
533 0: .long 0x000080f0 ! FD=1, IMASK=15
534 1: .long 0xcfffffff ! RB=0, BL=0
537 4: .long ret_from_irq
539 6: .long exception_handling_table
540 7: .long ret_from_exception