2 #include <linux/compiler.h>
3 #include <linux/slab.h>
5 #include <asm/clkdev.h>
8 static int sh_clk_mstp32_enable(struct clk *clk)
10 __raw_writel(__raw_readl(clk->enable_reg) & ~(1 << clk->enable_bit),
15 static void sh_clk_mstp32_disable(struct clk *clk)
17 __raw_writel(__raw_readl(clk->enable_reg) | (1 << clk->enable_bit),
21 static struct clk_ops sh_clk_mstp32_clk_ops = {
22 .enable = sh_clk_mstp32_enable,
23 .disable = sh_clk_mstp32_disable,
24 .recalc = followparent_recalc,
27 int __init sh_clk_mstp32_register(struct clk *clks, int nr)
33 for (k = 0; !ret && (k < nr); k++) {
35 clkp->ops = &sh_clk_mstp32_clk_ops;
36 ret |= clk_register(clkp);
42 static long sh_clk_div_round_rate(struct clk *clk, unsigned long rate)
44 return clk_rate_table_round(clk, clk->freq_table, rate);
47 static int sh_clk_div6_divisors[64] = {
48 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
49 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
50 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
51 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
54 static struct clk_div_mult_table sh_clk_div6_table = {
55 .divisors = sh_clk_div6_divisors,
56 .nr_divisors = ARRAY_SIZE(sh_clk_div6_divisors),
59 static unsigned long sh_clk_div6_recalc(struct clk *clk)
61 struct clk_div_mult_table *table = &sh_clk_div6_table;
64 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
67 idx = __raw_readl(clk->enable_reg) & 0x003f;
69 return clk->freq_table[idx].frequency;
72 static int sh_clk_div6_set_rate(struct clk *clk,
73 unsigned long rate, int algo_id)
78 idx = clk_rate_table_find(clk, clk->freq_table, rate);
82 value = __raw_readl(clk->enable_reg);
85 __raw_writel(value, clk->enable_reg);
89 static int sh_clk_div6_enable(struct clk *clk)
94 ret = sh_clk_div6_set_rate(clk, clk->rate, 0);
96 value = __raw_readl(clk->enable_reg);
97 value &= ~0x100; /* clear stop bit to enable clock */
98 __raw_writel(value, clk->enable_reg);
103 static void sh_clk_div6_disable(struct clk *clk)
107 value = __raw_readl(clk->enable_reg);
108 value |= 0x100; /* stop clock */
109 value |= 0x3f; /* VDIV bits must be non-zero, overwrite divider */
110 __raw_writel(value, clk->enable_reg);
113 static struct clk_ops sh_clk_div6_clk_ops = {
114 .recalc = sh_clk_div6_recalc,
115 .round_rate = sh_clk_div_round_rate,
116 .set_rate = sh_clk_div6_set_rate,
117 .enable = sh_clk_div6_enable,
118 .disable = sh_clk_div6_disable,
121 int __init sh_clk_div6_register(struct clk *clks, int nr)
125 int nr_divs = sh_clk_div6_table.nr_divisors;
126 int freq_table_size = sizeof(struct cpufreq_frequency_table);
130 freq_table_size *= (nr_divs + 1);
131 freq_table = kzalloc(freq_table_size * nr, GFP_KERNEL);
133 pr_err("sh_clk_div6_register: unable to alloc memory\n");
137 for (k = 0; !ret && (k < nr); k++) {
140 clkp->ops = &sh_clk_div6_clk_ops;
142 clkp->freq_table = freq_table + (k * freq_table_size);
143 clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
145 ret = clk_register(clkp);
151 static unsigned long sh_clk_div4_recalc(struct clk *clk)
153 struct clk_div4_table *d4t = clk->priv;
154 struct clk_div_mult_table *table = d4t->div_mult_table;
157 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
158 table, &clk->arch_flags);
160 idx = (__raw_readl(clk->enable_reg) >> clk->enable_bit) & 0x000f;
162 return clk->freq_table[idx].frequency;
165 static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)
167 struct clk_div4_table *d4t = clk->priv;
168 struct clk_div_mult_table *table = d4t->div_mult_table;
172 /* we really need a better way to determine parent index, but for
173 * now assume internal parent comes with CLK_ENABLE_ON_INIT set,
174 * no CLK_ENABLE_ON_INIT means external clock...
177 if (parent->flags & CLK_ENABLE_ON_INIT)
178 value = __raw_readl(clk->enable_reg) & ~(1 << 7);
180 value = __raw_readl(clk->enable_reg) | (1 << 7);
182 ret = clk_reparent(clk, parent);
186 __raw_writel(value, clk->enable_reg);
188 /* Rebiuld the frequency table */
189 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
190 table, &clk->arch_flags);
195 static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate, int algo_id)
197 struct clk_div4_table *d4t = clk->priv;
199 int idx = clk_rate_table_find(clk, clk->freq_table, rate);
203 value = __raw_readl(clk->enable_reg);
204 value &= ~(0xf << clk->enable_bit);
205 value |= (idx << clk->enable_bit);
206 __raw_writel(value, clk->enable_reg);
214 static int sh_clk_div4_enable(struct clk *clk)
216 __raw_writel(__raw_readl(clk->enable_reg) & ~(1 << 8), clk->enable_reg);
220 static void sh_clk_div4_disable(struct clk *clk)
222 __raw_writel(__raw_readl(clk->enable_reg) | (1 << 8), clk->enable_reg);
225 static struct clk_ops sh_clk_div4_clk_ops = {
226 .recalc = sh_clk_div4_recalc,
227 .set_rate = sh_clk_div4_set_rate,
228 .round_rate = sh_clk_div_round_rate,
231 static struct clk_ops sh_clk_div4_enable_clk_ops = {
232 .recalc = sh_clk_div4_recalc,
233 .set_rate = sh_clk_div4_set_rate,
234 .round_rate = sh_clk_div_round_rate,
235 .enable = sh_clk_div4_enable,
236 .disable = sh_clk_div4_disable,
239 static struct clk_ops sh_clk_div4_reparent_clk_ops = {
240 .recalc = sh_clk_div4_recalc,
241 .set_rate = sh_clk_div4_set_rate,
242 .round_rate = sh_clk_div_round_rate,
243 .enable = sh_clk_div4_enable,
244 .disable = sh_clk_div4_disable,
245 .set_parent = sh_clk_div4_set_parent,
248 static int __init sh_clk_div4_register_ops(struct clk *clks, int nr,
249 struct clk_div4_table *table, struct clk_ops *ops)
253 int nr_divs = table->div_mult_table->nr_divisors;
254 int freq_table_size = sizeof(struct cpufreq_frequency_table);
258 freq_table_size *= (nr_divs + 1);
259 freq_table = kzalloc(freq_table_size * nr, GFP_KERNEL);
261 pr_err("sh_clk_div4_register: unable to alloc memory\n");
265 for (k = 0; !ret && (k < nr); k++) {
272 clkp->freq_table = freq_table + (k * freq_table_size);
273 clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
275 ret = clk_register(clkp);
281 int __init sh_clk_div4_register(struct clk *clks, int nr,
282 struct clk_div4_table *table)
284 return sh_clk_div4_register_ops(clks, nr, table, &sh_clk_div4_clk_ops);
287 int __init sh_clk_div4_enable_register(struct clk *clks, int nr,
288 struct clk_div4_table *table)
290 return sh_clk_div4_register_ops(clks, nr, table,
291 &sh_clk_div4_enable_clk_ops);
294 int __init sh_clk_div4_reparent_register(struct clk *clks, int nr,
295 struct clk_div4_table *table)
297 return sh_clk_div4_register_ops(clks, nr, table,
298 &sh_clk_div4_reparent_clk_ops);
301 #ifdef CONFIG_SH_CLK_CPG_LEGACY
302 static struct clk master_clk = {
303 .flags = CLK_ENABLE_ON_INIT,
304 .rate = CONFIG_SH_PCLK_FREQ,
307 static struct clk peripheral_clk = {
308 .parent = &master_clk,
309 .flags = CLK_ENABLE_ON_INIT,
312 static struct clk bus_clk = {
313 .parent = &master_clk,
314 .flags = CLK_ENABLE_ON_INIT,
317 static struct clk cpu_clk = {
318 .parent = &master_clk,
319 .flags = CLK_ENABLE_ON_INIT,
323 * The ordering of these clocks matters, do not change it.
325 static struct clk *onchip_clocks[] = {
332 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
334 static struct clk_lookup lookups[] = {
336 CLKDEV_CON_ID("master_clk", &master_clk),
337 CLKDEV_CON_ID("peripheral_clk", &peripheral_clk),
338 CLKDEV_CON_ID("bus_clk", &bus_clk),
339 CLKDEV_CON_ID("cpu_clk", &cpu_clk),
342 int __init __deprecated cpg_clk_init(void)
346 for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) {
347 struct clk *clk = onchip_clocks[i];
348 arch_init_clk_ops(&clk->ops, i);
350 ret |= clk_register(clk);
353 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
355 clk_add_alias("tmu_fck", NULL, "peripheral_clk", NULL);
356 clk_add_alias("mtu2_fck", NULL, "peripheral_clk", NULL);
357 clk_add_alias("cmt_fck", NULL, "peripheral_clk", NULL);
358 clk_add_alias("sci_ick", NULL, "peripheral_clk", NULL);
364 * Placeholder for compatability, until the lazy CPUs do this
367 int __init __weak arch_clk_init(void)
369 return cpg_clk_init();
371 #endif /* CONFIG_SH_CPG_CLK_LEGACY */