2 * SH4 CPU-specific DMA definitions, used by both DMA drivers
4 * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #ifndef CPU_DMA_REGISTER_H
11 #define CPU_DMA_REGISTER_H
13 /* SH7751/7760/7780 DMA IRQ sources */
15 #ifdef CONFIG_CPU_SH4A
17 #define DMAOR_INIT DMAOR_DME
19 #if defined(CONFIG_CPU_SUBTYPE_SH7343) || \
20 defined(CONFIG_CPU_SUBTYPE_SH7730)
21 #define CHCR_TS_LOW_MASK 0x00000018
22 #define CHCR_TS_LOW_SHIFT 3
23 #define CHCR_TS_HIGH_MASK 0
24 #define CHCR_TS_HIGH_SHIFT 0
25 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
26 #define CHCR_TS_LOW_MASK 0x00000018
27 #define CHCR_TS_LOW_SHIFT 3
28 #define CHCR_TS_HIGH_MASK 0x00300000
29 #define CHCR_TS_HIGH_SHIFT (20 - 2) /* 2 bits for shifted low TS */
30 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
31 defined(CONFIG_CPU_SUBTYPE_SH7764)
32 #define CHCR_TS_LOW_MASK 0x00000018
33 #define CHCR_TS_LOW_SHIFT 3
34 #define CHCR_TS_HIGH_MASK 0
35 #define CHCR_TS_HIGH_SHIFT 0
36 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
37 #define CHCR_TS_LOW_MASK 0x00000018
38 #define CHCR_TS_LOW_SHIFT 3
39 #define CHCR_TS_HIGH_MASK 0
40 #define CHCR_TS_HIGH_SHIFT 0
41 #elif defined(CONFIG_CPU_SUBTYPE_SH7724)
42 #define CHCR_TS_LOW_MASK 0x00000018
43 #define CHCR_TS_LOW_SHIFT 3
44 #define CHCR_TS_HIGH_MASK 0x00600000
45 #define CHCR_TS_HIGH_SHIFT (20 - 2) /* 2 bits for shifted low TS */
46 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
47 #define CHCR_TS_LOW_MASK 0x00000018
48 #define CHCR_TS_LOW_SHIFT 3
49 #define CHCR_TS_HIGH_MASK 0
50 #define CHCR_TS_HIGH_SHIFT 0
52 #define CHCR_TS_LOW_MASK 0x00000018
53 #define CHCR_TS_LOW_SHIFT 3
54 #define CHCR_TS_HIGH_MASK 0
55 #define CHCR_TS_HIGH_SHIFT 0
58 /* Transmit sizes and respective CHCR register values */
66 XMIT_SZ_128BIT_BLK = 0xb,
67 XMIT_SZ_256BIT_BLK = 0xc,
70 /* log2(size / 8) - used to calculate number of transfers */
73 [XMIT_SZ_16BIT] = 1, \
74 [XMIT_SZ_32BIT] = 2, \
75 [XMIT_SZ_64BIT] = 3, \
76 [XMIT_SZ_128BIT] = 4, \
77 [XMIT_SZ_256BIT] = 5, \
78 [XMIT_SZ_128BIT_BLK] = 4, \
79 [XMIT_SZ_256BIT_BLK] = 5, \
82 #define TS_INDEX2VAL(i) ((((i) & 3) << CHCR_TS_LOW_SHIFT) | \
83 ((((i) >> 2) & 3) << CHCR_TS_HIGH_SHIFT))
85 #else /* CONFIG_CPU_SH4A */
87 #define DMAOR_INIT (0x8000 | DMAOR_DME)
89 #define CHCR_TS_LOW_MASK 0x70
90 #define CHCR_TS_LOW_SHIFT 4
91 #define CHCR_TS_HIGH_MASK 0
92 #define CHCR_TS_HIGH_SHIFT 0
94 /* Transmit sizes and respective CHCR register values */
103 /* log2(size / 8) - used to calculate number of transfers */
105 [XMIT_SZ_8BIT] = 0, \
106 [XMIT_SZ_16BIT] = 1, \
107 [XMIT_SZ_32BIT] = 2, \
108 [XMIT_SZ_64BIT] = 3, \
109 [XMIT_SZ_256BIT] = 5, \
112 #define TS_INDEX2VAL(i) (((i) & 7) << CHCR_TS_LOW_SHIFT)
114 #endif /* CONFIG_CPU_SH4A */