6 /* Can be used to override the logic in pci_scan_bus for skipping
7 already-configured bus numbers - to be used for buggy BIOSes
8 or architectures with incomplete PCI setup by the loader */
10 #define pcibios_assign_all_busses() 1
13 * A board can define one or more PCI channels that represent built-in (or
14 * external) PCI controllers.
17 struct pci_channel *next;
20 struct pci_ops *pci_ops;
21 struct resource *io_resource;
22 struct resource *mem_resource;
24 unsigned long io_offset;
25 unsigned long mem_offset;
27 unsigned long reg_base;
28 unsigned long io_map_base;
31 unsigned int need_domain_info;
34 extern void register_pci_controller(struct pci_channel *hose);
36 extern unsigned long PCIBIOS_MIN_IO, PCIBIOS_MIN_MEM;
41 extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
42 enum pci_mmap_state mmap_state, int write_combine);
43 extern void pcibios_set_master(struct pci_dev *dev);
45 static inline void pcibios_penalize_isa_irq(int irq, int active)
47 /* We don't do dynamic PCI IRQ allocation */
50 /* Dynamic DMA mapping stuff.
51 * SuperH has everything mapped statically like x86.
54 /* The PCI address space does equal the physical memory
55 * address space. The networking and block device layers use
56 * this boolean for bounce buffer decisions.
58 #define PCI_DMA_BUS_IS_PHYS (dma_ops->is_phys)
60 /* pci_unmap_{single,page} being a nop depends upon the
63 #ifdef CONFIG_DMA_NONCOHERENT
64 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) dma_addr_t ADDR_NAME;
65 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) __u32 LEN_NAME;
66 #define pci_unmap_addr(PTR, ADDR_NAME) ((PTR)->ADDR_NAME)
67 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) (((PTR)->ADDR_NAME) = (VAL))
68 #define pci_unmap_len(PTR, LEN_NAME) ((PTR)->LEN_NAME)
69 #define pci_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL))
71 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
72 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
73 #define pci_unmap_addr(PTR, ADDR_NAME) (0)
74 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
75 #define pci_unmap_len(PTR, LEN_NAME) (0)
76 #define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0)
81 * None of the SH PCI controllers support MWI, it is always treated as a
82 * direct memory write.
84 #define PCI_DISABLE_MWI
86 static inline void pci_dma_burst_advice(struct pci_dev *pdev,
87 enum pci_dma_burst_strategy *strat,
88 unsigned long *strategy_parameter)
90 unsigned long cacheline_size;
93 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
96 cacheline_size = L1_CACHE_BYTES;
98 cacheline_size = byte << 2;
100 *strat = PCI_DMA_BURST_MULTIPLE;
101 *strategy_parameter = cacheline_size;
105 /* Board-specific fixup routines. */
106 int pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin);
108 extern void pcibios_resource_to_bus(struct pci_dev *dev,
109 struct pci_bus_region *region, struct resource *res);
111 extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
112 struct pci_bus_region *region);
114 #define pci_domain_nr(bus) ((struct pci_channel *)(bus)->sysdata)->index
116 static inline int pci_proc_domain(struct pci_bus *bus)
118 struct pci_channel *hose = bus->sysdata;
119 return hose->need_domain_info;
122 /* Chances are this interrupt is wired PC-style ... */
123 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
125 return channel ? 15 : 14;
128 /* generic DMA-mapping stuff */
129 #include <asm-generic/pci-dma-compat.h>
131 #endif /* __KERNEL__ */
132 #endif /* __ASM_SH_PCI_H */