2 * Copyright (C) 2001 Ian da Silva, Jeremy Siegel
3 * Based largely on io_se.c.
5 * I/O routine for Renesas Solutions Highlander R7780RP-1
7 * Initial version only to support LAN access; some
8 * placeholder code from io_r7780rp.c left in with the
9 * expectation of later SuperIO and PCMCIA access.
11 #include <linux/pci.h>
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <asm/r7780rp.h>
15 #include <asm/addrspace.h>
18 static inline unsigned long port2adr(unsigned int port)
20 if ((0x1f0 <= port && port < 0x1f8) || port == 0x3f6)
22 return (PA_AREA5_IO + 0x80c);
24 return (PA_AREA5_IO + 0x1000 + ((port-0x1f0) << 1));
26 maybebadio((unsigned long)port);
31 static inline unsigned long port88796l(unsigned int port, int flag)
36 addr = PA_AX88796L + ((port - AX88796L_IO_BASE) << 1);
38 addr = PA_AX88796L + ((port - AX88796L_IO_BASE) << 1) + 0x1000;
43 /* The 7780 R7780RP-1 seems to have everything hooked */
44 /* up pretty normally (nothing on high-bytes only...) so this */
45 /* shouldn't be needed */
46 static inline int shifted_port(unsigned long port)
48 /* For IDE registers, value is not shifted */
49 if ((0x1f0 <= port && port < 0x1f8) || port == 0x3f6)
55 #if defined(CONFIG_NE2000) || defined(CONFIG_NE2000_MODULE)
56 #define CHECK_AX88796L_PORT(port) \
57 ((port >= AX88796L_IO_BASE) && (port < (AX88796L_IO_BASE+0x20)))
59 #define CHECK_AX88796L_PORT(port) (0)
63 * General outline: remap really low stuff [eventually] to SuperIO,
64 * stuff in PCI IO space (at or above window at pci.h:PCIBIOS_MIN_IO)
65 * is mapped through the PCI IO window. Stuff with high bits (PXSEG)
66 * should be way beyond the window, and is used w/o translation for
69 u8 r7780rp_inb(unsigned long port)
71 if (CHECK_AX88796L_PORT(port))
72 return ctrl_inw(port88796l(port, 0)) & 0xff;
74 return ctrl_inb(port);
75 else if (is_pci_ioaddr(port) || shifted_port(port))
76 return ctrl_inb(pci_ioaddr(port));
78 return ctrl_inw(port2adr(port)) & 0xff;
81 u8 r7780rp_inb_p(unsigned long port)
85 if (CHECK_AX88796L_PORT(port))
86 v = ctrl_inw(port88796l(port, 0)) & 0xff;
89 else if (is_pci_ioaddr(port) || shifted_port(port))
90 v = ctrl_inb(pci_ioaddr(port));
92 v = ctrl_inw(port2adr(port)) & 0xff;
99 u16 r7780rp_inw(unsigned long port)
101 if (CHECK_AX88796L_PORT(port))
103 else if (PXSEG(port))
104 return ctrl_inw(port);
105 else if (is_pci_ioaddr(port) || shifted_port(port))
106 return ctrl_inw(pci_ioaddr(port));
113 u32 r7780rp_inl(unsigned long port)
115 if (CHECK_AX88796L_PORT(port))
117 else if (PXSEG(port))
118 return ctrl_inl(port);
119 else if (is_pci_ioaddr(port) || shifted_port(port))
120 return ctrl_inl(pci_ioaddr(port));
127 void r7780rp_outb(u8 value, unsigned long port)
129 if (CHECK_AX88796L_PORT(port))
130 ctrl_outw(value, port88796l(port, 0));
131 else if (PXSEG(port))
132 ctrl_outb(value, port);
133 else if (is_pci_ioaddr(port) || shifted_port(port))
134 ctrl_outb(value, pci_ioaddr(port));
136 ctrl_outw(value, port2adr(port));
139 void r7780rp_outb_p(u8 value, unsigned long port)
141 if (CHECK_AX88796L_PORT(port))
142 ctrl_outw(value, port88796l(port, 0));
143 else if (PXSEG(port))
144 ctrl_outb(value, port);
145 else if (is_pci_ioaddr(port) || shifted_port(port))
146 ctrl_outb(value, pci_ioaddr(port));
148 ctrl_outw(value, port2adr(port));
153 void r7780rp_outw(u16 value, unsigned long port)
155 if (CHECK_AX88796L_PORT(port))
157 else if (PXSEG(port))
158 ctrl_outw(value, port);
159 else if (is_pci_ioaddr(port) || shifted_port(port))
160 ctrl_outw(value, pci_ioaddr(port));
165 void r7780rp_outl(u32 value, unsigned long port)
167 if (CHECK_AX88796L_PORT(port))
169 else if (PXSEG(port))
170 ctrl_outl(value, port);
171 else if (is_pci_ioaddr(port) || shifted_port(port))
172 ctrl_outl(value, pci_ioaddr(port));
177 void r7780rp_insb(unsigned long port, void *dst, unsigned long count)
182 if (CHECK_AX88796L_PORT(port)) {
183 p = (volatile u16 *)port88796l(port, 0);
186 } else if (PXSEG(port)) {
188 *buf++ = *(volatile u8 *)port;
189 } else if (is_pci_ioaddr(port) || shifted_port(port)) {
190 volatile u8 *bp = (volatile u8 *)pci_ioaddr(port);
195 p = (volatile u16 *)port2adr(port);
201 void r7780rp_insw(unsigned long port, void *dst, unsigned long count)
206 if (CHECK_AX88796L_PORT(port))
207 p = (volatile u16 *)port88796l(port, 1);
208 else if (PXSEG(port))
209 p = (volatile u16 *)port;
210 else if (is_pci_ioaddr(port) || shifted_port(port))
211 p = (volatile u16 *)pci_ioaddr(port);
213 p = (volatile u16 *)port2adr(port);
219 void r7780rp_insl(unsigned long port, void *dst, unsigned long count)
223 if (CHECK_AX88796L_PORT(port))
225 else if (is_pci_ioaddr(port) || shifted_port(port)) {
226 volatile u32 *p = (volatile u32 *)pci_ioaddr(port);
234 void r7780rp_outsb(unsigned long port, const void *src, unsigned long count)
239 if (CHECK_AX88796L_PORT(port)) {
240 p = (volatile u16 *)port88796l(port, 0);
243 } else if (PXSEG(port))
245 ctrl_outb(*buf++, port);
246 else if (is_pci_ioaddr(port) || shifted_port(port)) {
247 volatile u8 *bp = (volatile u8 *)pci_ioaddr(port);
252 p = (volatile u16 *)port2adr(port);
258 void r7780rp_outsw(unsigned long port, const void *src, unsigned long count)
261 const u16 *buf = src;
263 if (CHECK_AX88796L_PORT(port))
264 p = (volatile u16 *)port88796l(port, 1);
265 else if (PXSEG(port))
266 p = (volatile u16 *)port;
267 else if (is_pci_ioaddr(port) || shifted_port(port))
268 p = (volatile u16 *)pci_ioaddr(port);
270 p = (volatile u16 *)port2adr(port);
276 void r7780rp_outsl(unsigned long port, const void *src, unsigned long count)
278 const u32 *buf = src;
280 if (CHECK_AX88796L_PORT(port))
282 else if (is_pci_ioaddr(port) || shifted_port(port)) {
283 volatile u32 *p = (volatile u32 *)pci_ioaddr(port);
291 void __iomem *r7780rp_ioport_map(unsigned long port, unsigned int size)
293 if (CHECK_AX88796L_PORT(port))
294 return (void __iomem *)port88796l(port, size > 1);
295 else if (PXSEG(port))
296 return (void __iomem *)port;
297 else if (is_pci_ioaddr(port) || shifted_port(port))
298 return (void __iomem *)pci_ioaddr(port);
300 return (void __iomem *)port2adr(port);