2 * Renesas Technology Corp. R0P7785LC0011RL Support.
4 * Copyright (C) 2008 Yoshihiro Shimoda
5 * Copyright (C) 2009 Paul Mundt
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
11 #include <linux/init.h>
12 #include <linux/platform_device.h>
13 #include <linux/sm501.h>
14 #include <linux/sm501-regs.h>
16 #include <linux/mtd/physmap.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/i2c.h>
20 #include <linux/i2c-pca-platform.h>
21 #include <linux/i2c-algo-pca.h>
22 #include <linux/usb/r8a66597.h>
23 #include <linux/irq.h>
24 #include <linux/clk.h>
25 #include <linux/errno.h>
26 #include <mach/sh7785lcr.h>
27 #include <cpu/sh7785.h>
28 #include <asm/heartbeat.h>
29 #include <asm/clock.h>
32 * NOTE: This board has 2 physical memory maps.
33 * Please look at include/asm-sh/sh7785lcr.h or hardware manual.
35 static struct resource heartbeat_resources[] = {
39 .flags = IORESOURCE_MEM,
43 static struct heartbeat_data heartbeat_data = {
47 static struct platform_device heartbeat_device = {
51 .platform_data = &heartbeat_data,
53 .num_resources = ARRAY_SIZE(heartbeat_resources),
54 .resource = heartbeat_resources,
57 static struct mtd_partition nor_flash_partitions[] = {
65 .offset = MTDPART_OFS_APPEND,
70 .offset = MTDPART_OFS_APPEND,
71 .size = 4 * 1024 * 1024,
75 .offset = MTDPART_OFS_APPEND,
76 .size = MTDPART_SIZ_FULL,
80 static struct physmap_flash_data nor_flash_data = {
82 .parts = nor_flash_partitions,
83 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
86 static struct resource nor_flash_resources[] = {
88 .start = NOR_FLASH_ADDR,
89 .end = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1,
90 .flags = IORESOURCE_MEM,
94 static struct platform_device nor_flash_device = {
95 .name = "physmap-flash",
97 .platform_data = &nor_flash_data,
99 .num_resources = ARRAY_SIZE(nor_flash_resources),
100 .resource = nor_flash_resources,
103 static struct r8a66597_platdata r8a66597_data = {
104 .xtal = R8A66597_PLATDATA_XTAL_12MHZ,
108 static struct resource r8a66597_usb_host_resources[] = {
110 .start = R8A66597_ADDR,
111 .end = R8A66597_ADDR + R8A66597_SIZE - 1,
112 .flags = IORESOURCE_MEM,
117 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
121 static struct platform_device r8a66597_usb_host_device = {
122 .name = "r8a66597_hcd",
126 .coherent_dma_mask = 0xffffffff,
127 .platform_data = &r8a66597_data,
129 .num_resources = ARRAY_SIZE(r8a66597_usb_host_resources),
130 .resource = r8a66597_usb_host_resources,
133 static struct resource sm501_resources[] = {
135 .start = SM107_MEM_ADDR,
136 .end = SM107_MEM_ADDR + SM107_MEM_SIZE - 1,
137 .flags = IORESOURCE_MEM,
140 .start = SM107_REG_ADDR,
141 .end = SM107_REG_ADDR + SM107_REG_SIZE - 1,
142 .flags = IORESOURCE_MEM,
146 .flags = IORESOURCE_IRQ,
150 static struct fb_videomode sm501_default_mode_crt = {
151 .pixclock = 35714, /* 28MHz */
160 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
163 static struct fb_videomode sm501_default_mode_pnl = {
164 .pixclock = 40000, /* 25MHz */
176 static struct sm501_platdata_fbsub sm501_pdata_fbsub_pnl = {
178 .def_mode = &sm501_default_mode_pnl,
179 .flags = SM501FB_FLAG_USE_INIT_MODE |
180 SM501FB_FLAG_USE_HWCURSOR |
181 SM501FB_FLAG_USE_HWACCEL |
182 SM501FB_FLAG_DISABLE_AT_EXIT |
183 SM501FB_FLAG_PANEL_NO_VBIASEN,
186 static struct sm501_platdata_fbsub sm501_pdata_fbsub_crt = {
188 .def_mode = &sm501_default_mode_crt,
189 .flags = SM501FB_FLAG_USE_INIT_MODE |
190 SM501FB_FLAG_USE_HWCURSOR |
191 SM501FB_FLAG_USE_HWACCEL |
192 SM501FB_FLAG_DISABLE_AT_EXIT,
195 static struct sm501_platdata_fb sm501_fb_pdata = {
196 .fb_route = SM501_FB_OWN,
197 .fb_crt = &sm501_pdata_fbsub_crt,
198 .fb_pnl = &sm501_pdata_fbsub_pnl,
201 static struct sm501_initdata sm501_initdata = {
207 .mclk = 84 * 1000000,
208 .m1xclk = 112 * 1000000,
211 static struct sm501_platdata sm501_platform_data = {
212 .init = &sm501_initdata,
213 .fb = &sm501_fb_pdata,
216 static struct platform_device sm501_device = {
220 .platform_data = &sm501_platform_data,
222 .num_resources = ARRAY_SIZE(sm501_resources),
223 .resource = sm501_resources,
226 static struct resource i2c_proto_resources[] = {
228 .start = PCA9564_PROTO_32BIT_ADDR,
229 .end = PCA9564_PROTO_32BIT_ADDR + PCA9564_SIZE - 1,
230 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
235 .flags = IORESOURCE_IRQ,
239 static struct resource i2c_resources[] = {
241 .start = PCA9564_ADDR,
242 .end = PCA9564_ADDR + PCA9564_SIZE - 1,
243 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
248 .flags = IORESOURCE_IRQ,
252 static struct i2c_pca9564_pf_platform_data i2c_platform_data = {
254 .i2c_clock_speed = I2C_PCA_CON_330kHz,
258 static struct platform_device i2c_device = {
259 .name = "i2c-pca-platform",
262 .platform_data = &i2c_platform_data,
264 .num_resources = ARRAY_SIZE(i2c_resources),
265 .resource = i2c_resources,
268 static struct platform_device *sh7785lcr_devices[] __initdata = {
271 &r8a66597_usb_host_device,
276 static struct i2c_board_info __initdata sh7785lcr_i2c_devices[] = {
278 I2C_BOARD_INFO("r2025sd", 0x32),
282 static int __init sh7785lcr_devices_setup(void)
284 i2c_register_board_info(0, sh7785lcr_i2c_devices,
285 ARRAY_SIZE(sh7785lcr_i2c_devices));
287 if (mach_is_sh7785lcr_pt()) {
288 i2c_device.resource = i2c_proto_resources;
289 i2c_device.num_resources = ARRAY_SIZE(i2c_proto_resources);
292 return platform_add_devices(sh7785lcr_devices,
293 ARRAY_SIZE(sh7785lcr_devices));
295 __initcall(sh7785lcr_devices_setup);
297 /* Initialize IRQ setting */
298 void __init init_sh7785lcr_IRQ(void)
300 plat_irq_setup_pins(IRQ_MODE_IRQ7654);
301 plat_irq_setup_pins(IRQ_MODE_IRQ3210);
304 static int sh7785lcr_clk_init(void)
309 clk = clk_get(NULL, "extal");
310 if (!clk || IS_ERR(clk))
312 ret = clk_set_rate(clk, 33333333);
318 static void sh7785lcr_power_off(void)
322 p = ioremap(PLD_POFCR, PLD_POFCR + 1);
324 printk(KERN_ERR "%s: ioremap error.\n", __func__);
334 /* Initialize the board */
335 static void __init sh7785lcr_setup(char **cmdline_p)
337 void __iomem *sm501_reg;
339 printk(KERN_INFO "Renesas Technology Corp. R0P7785LC0011RL support.\n");
341 pm_power_off = sh7785lcr_power_off;
343 /* sm501 DRAM configuration */
344 sm501_reg = (void __iomem *)0xb3e00000 + SM501_DRAM_CONTROL;
345 writel(0x000307c2, sm501_reg);
348 /* Return the board specific boot mode pin configuration */
349 static int sh7785lcr_mode_pins(void)
353 /* These are the factory default settings of S1 and S2.
354 * If you change these dip switches then you will need to
355 * adjust the values below as well.
357 value |= MODE_PIN4; /* Clock Mode 16 */
358 value |= MODE_PIN5; /* 32-bit Area0 bus width */
359 value |= MODE_PIN6; /* 32-bit Area0 bus width */
360 value |= MODE_PIN7; /* Area 0 SRAM interface [fixed] */
361 value |= MODE_PIN8; /* Little Endian */
362 value |= MODE_PIN9; /* Master Mode */
363 value |= MODE_PIN14; /* No PLL step-up */
371 static struct sh_machine_vector mv_sh7785lcr __initmv = {
372 .mv_name = "SH7785LCR",
373 .mv_setup = sh7785lcr_setup,
374 .mv_clk_init = sh7785lcr_clk_init,
375 .mv_init_irq = init_sh7785lcr_IRQ,
376 .mv_mode_pins = sh7785lcr_mode_pins,