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   1 /*
   2  *  arch/powerpc/kernel/mpic.c
   3  *
   4  *  Driver for interrupt controllers following the OpenPIC standard, the
   5  *  common implementation beeing IBM's MPIC. This driver also can deal
   6  *  with various broken implementations of this HW.
   7  *
   8  *  Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
   9  *
  10  *  This file is subject to the terms and conditions of the GNU General Public
  11  *  License.  See the file COPYING in the main directory of this archive
  12  *  for more details.
  13  */
  14
  15 #undef DEBUG
  16 #undef DEBUG_IPI
  17 #undef DEBUG_IRQ
  18 #undef DEBUG_LOW
  19
  20 #include <linux/types.h>
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/irq.h>
  24 #include <linux/smp.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/bootmem.h>
  27 #include <linux/spinlock.h>
  28 #include <linux/pci.h>
  29
  30 #include <asm/ptrace.h>
  31 #include <asm/signal.h>
  32 #include <asm/io.h>
  33 #include <asm/pgtable.h>
  34 #include <asm/irq.h>
  35 #include <asm/machdep.h>
  36 #include <asm/mpic.h>
  37 #include <asm/smp.h>
  38
  39 #include "mpic.h"
  40
  41 #ifdef DEBUG
  42 #define DBG(fmt...) printk(fmt)
  43 #else
  44 #define DBG(fmt...)
  45 #endif
  46
  47 static struct mpic *mpics;
  48 static struct mpic *mpic_primary;
  49 static DEFINE_SPINLOCK(mpic_lock);
  50
  51 #ifdef CONFIG_PPC32     /* XXX for now */
  52 #ifdef CONFIG_IRQ_ALL_CPUS
  53 #define distribute_irqs (1)
  54 #else
  55 #define distribute_irqs (0)
  56 #endif
  57 #endif
  58
  59 #ifdef CONFIG_MPIC_WEIRD
  60 static u32 mpic_infos[][MPIC_IDX_END] = {
  61         [0] = { /* Original OpenPIC compatible MPIC */
  62                 MPIC_GREG_BASE,
  63                 MPIC_GREG_FEATURE_0,
  64                 MPIC_GREG_GLOBAL_CONF_0,
  65                 MPIC_GREG_VENDOR_ID,
  66                 MPIC_GREG_IPI_VECTOR_PRI_0,
  67                 MPIC_GREG_IPI_STRIDE,
  68                 MPIC_GREG_SPURIOUS,
  69                 MPIC_GREG_TIMER_FREQ,
  70
  71                 MPIC_TIMER_BASE,
  72                 MPIC_TIMER_STRIDE,
  73                 MPIC_TIMER_CURRENT_CNT,
  74                 MPIC_TIMER_BASE_CNT,
  75                 MPIC_TIMER_VECTOR_PRI,
  76                 MPIC_TIMER_DESTINATION,
  77
  78                 MPIC_CPU_BASE,
  79                 MPIC_CPU_STRIDE,
  80                 MPIC_CPU_IPI_DISPATCH_0,
  81                 MPIC_CPU_IPI_DISPATCH_STRIDE,
  82                 MPIC_CPU_CURRENT_TASK_PRI,
  83                 MPIC_CPU_WHOAMI,
  84                 MPIC_CPU_INTACK,
  85                 MPIC_CPU_EOI,
  86                 MPIC_CPU_MCACK,
  87
  88                 MPIC_IRQ_BASE,
  89                 MPIC_IRQ_STRIDE,
  90                 MPIC_IRQ_VECTOR_PRI,
  91                 MPIC_VECPRI_VECTOR_MASK,
  92                 MPIC_VECPRI_POLARITY_POSITIVE,
  93                 MPIC_VECPRI_POLARITY_NEGATIVE,
  94                 MPIC_VECPRI_SENSE_LEVEL,
  95                 MPIC_VECPRI_SENSE_EDGE,
  96                 MPIC_VECPRI_POLARITY_MASK,
  97                 MPIC_VECPRI_SENSE_MASK,
  98                 MPIC_IRQ_DESTINATION
  99         },
 100         [1] = { /* Tsi108/109 PIC */
 101                 TSI108_GREG_BASE,
 102                 TSI108_GREG_FEATURE_0,
 103                 TSI108_GREG_GLOBAL_CONF_0,
 104                 TSI108_GREG_VENDOR_ID,
 105                 TSI108_GREG_IPI_VECTOR_PRI_0,
 106                 TSI108_GREG_IPI_STRIDE,
 107                 TSI108_GREG_SPURIOUS,
 108                 TSI108_GREG_TIMER_FREQ,
 109
 110                 TSI108_TIMER_BASE,
 111                 TSI108_TIMER_STRIDE,
 112                 TSI108_TIMER_CURRENT_CNT,
 113                 TSI108_TIMER_BASE_CNT,
 114                 TSI108_TIMER_VECTOR_PRI,
 115                 TSI108_TIMER_DESTINATION,
 116
 117                 TSI108_CPU_BASE,
 118                 TSI108_CPU_STRIDE,
 119                 TSI108_CPU_IPI_DISPATCH_0,
 120                 TSI108_CPU_IPI_DISPATCH_STRIDE,
 121                 TSI108_CPU_CURRENT_TASK_PRI,
 122                 TSI108_CPU_WHOAMI,
 123                 TSI108_CPU_INTACK,
 124                 TSI108_CPU_EOI,
 125                 TSI108_CPU_MCACK,
 126
 127                 TSI108_IRQ_BASE,
 128                 TSI108_IRQ_STRIDE,
 129                 TSI108_IRQ_VECTOR_PRI,
 130                 TSI108_VECPRI_VECTOR_MASK,
 131                 TSI108_VECPRI_POLARITY_POSITIVE,
 132                 TSI108_VECPRI_POLARITY_NEGATIVE,
 133                 TSI108_VECPRI_SENSE_LEVEL,
 134                 TSI108_VECPRI_SENSE_EDGE,
 135                 TSI108_VECPRI_POLARITY_MASK,
 136                 TSI108_VECPRI_SENSE_MASK,
 137                 TSI108_IRQ_DESTINATION
 138         },
 139 };
 140
 141 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
 142
 143 #else /* CONFIG_MPIC_WEIRD */
 144
 145 #define MPIC_INFO(name) MPIC_##name
 146
 147 #endif /* CONFIG_MPIC_WEIRD */
 148
 149 /*
 150  * Register accessor functions
 151  */
 152
 153
 154 static inline u32 _mpic_read(enum mpic_reg_type type,
 155                              struct mpic_reg_bank *rb,
 156                              unsigned int reg)
 157 {
 158         switch(type) {
 159 #ifdef CONFIG_PPC_DCR
 160         case mpic_access_dcr:
 161                 return dcr_read(rb->dhost, reg);
 162 #endif
 163         case mpic_access_mmio_be:
 164                 return in_be32(rb->base + (reg >> 2));
 165         case mpic_access_mmio_le:
 166         default:
 167                 return in_le32(rb->base + (reg >> 2));
 168         }
 169 }
 170
 171 static inline void _mpic_write(enum mpic_reg_type type,
 172                                struct mpic_reg_bank *rb,
 173                                unsigned int reg, u32 value)
 174 {
 175         switch(type) {
 176 #ifdef CONFIG_PPC_DCR
 177         case mpic_access_dcr:
 178                 dcr_write(rb->dhost, reg, value);
 179                 break;
 180 #endif
 181         case mpic_access_mmio_be:
 182                 out_be32(rb->base + (reg >> 2), value);
 183                 break;
 184         case mpic_access_mmio_le:
 185         default:
 186                 out_le32(rb->base + (reg >> 2), value);
 187                 break;
 188         }
 189 }
 190
 191 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
 192 {
 193         enum mpic_reg_type type = mpic->reg_type;
 194         unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
 195                               (ipi * MPIC_INFO(GREG_IPI_STRIDE));
 196
 197         if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
 198                 type = mpic_access_mmio_be;
 199         return _mpic_read(type, &mpic->gregs, offset);
 200 }
 201
 202 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
 203 {
 204         unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
 205                               (ipi * MPIC_INFO(GREG_IPI_STRIDE));
 206
 207         _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
 208 }
 209
 210 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
 211 {
 212         unsigned int cpu = 0;
 213
 214         if (mpic->flags & MPIC_PRIMARY)
 215                 cpu = hard_smp_processor_id();
 216         return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
 217 }
 218
 219 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
 220 {
 221         unsigned int cpu = 0;
 222
 223         if (mpic->flags & MPIC_PRIMARY)
 224                 cpu = hard_smp_processor_id();
 225
 226         _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
 227 }
 228
 229 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
 230 {
 231         unsigned int    isu = src_no >> mpic->isu_shift;
 232         unsigned int    idx = src_no & mpic->isu_mask;
 233         unsigned int    val;
 234
 235         val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
 236                          reg + (idx * MPIC_INFO(IRQ_STRIDE)));
 237 #ifdef CONFIG_MPIC_BROKEN_REGREAD
 238         if (reg == 0)
 239                 val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |
 240                         mpic->isu_reg0_shadow[src_no];
 241 #endif
 242         return val;
 243 }
 244
 245 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
 246                                    unsigned int reg, u32 value)
 247 {
 248         unsigned int    isu = src_no >> mpic->isu_shift;
 249         unsigned int    idx = src_no & mpic->isu_mask;
 250
 251         _mpic_write(mpic->reg_type, &mpic->isus[isu],
 252                     reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
 253
 254 #ifdef CONFIG_MPIC_BROKEN_REGREAD
 255         if (reg == 0)
 256                 mpic->isu_reg0_shadow[src_no] =
 257                         value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);
 258 #endif
 259 }
 260
 261 #define mpic_read(b,r)          _mpic_read(mpic->reg_type,&(b),(r))
 262 #define mpic_write(b,r,v)       _mpic_write(mpic->reg_type,&(b),(r),(v))
 263 #define mpic_ipi_read(i)        _mpic_ipi_read(mpic,(i))
 264 #define mpic_ipi_write(i,v)     _mpic_ipi_write(mpic,(i),(v))
 265 #define mpic_cpu_read(i)        _mpic_cpu_read(mpic,(i))
 266 #define mpic_cpu_write(i,v)     _mpic_cpu_write(mpic,(i),(v))
 267 #define mpic_irq_read(s,r)      _mpic_irq_read(mpic,(s),(r))
 268 #define mpic_irq_write(s,r,v)   _mpic_irq_write(mpic,(s),(r),(v))
 269
 270
 271 /*
 272  * Low level utility functions
 273  */
 274
 275
 276 static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
 277                            struct mpic_reg_bank *rb, unsigned int offset,
 278                            unsigned int size)
 279 {
 280         rb->base = ioremap(phys_addr + offset, size);
 281         BUG_ON(rb->base == NULL);
 282 }
 283
 284 #ifdef CONFIG_PPC_DCR
 285 static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node,
 286                           struct mpic_reg_bank *rb,
 287                           unsigned int offset, unsigned int size)
 288 {
 289         const u32 *dbasep;
 290
 291         dbasep = of_get_property(node, "dcr-reg", NULL);
 292
 293         rb->dhost = dcr_map(node, *dbasep + offset, size);
 294         BUG_ON(!DCR_MAP_OK(rb->dhost));
 295 }
 296
 297 static inline void mpic_map(struct mpic *mpic, struct device_node *node,
 298                             phys_addr_t phys_addr, struct mpic_reg_bank *rb,
 299                             unsigned int offset, unsigned int size)
 300 {
 301         if (mpic->flags & MPIC_USES_DCR)
 302                 _mpic_map_dcr(mpic, node, rb, offset, size);
 303         else
 304                 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
 305 }
 306 #else /* CONFIG_PPC_DCR */
 307 #define mpic_map(m,n,p,b,o,s)   _mpic_map_mmio(m,p,b,o,s)
 308 #endif /* !CONFIG_PPC_DCR */
 309
 310
 311
 312 /* Check if we have one of those nice broken MPICs with a flipped endian on
 313  * reads from IPI registers
 314  */
 315 static void __init mpic_test_broken_ipi(struct mpic *mpic)
 316 {
 317         u32 r;
 318
 319         mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
 320         r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
 321
 322         if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
 323                 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
 324                 mpic->flags |= MPIC_BROKEN_IPI;
 325         }
 326 }
 327
 328 #ifdef CONFIG_MPIC_U3_HT_IRQS
 329
 330 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
 331  * to force the edge setting on the MPIC and do the ack workaround.
 332  */
 333 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
 334 {
 335         if (source >= 128 || !mpic->fixups)
 336                 return 0;
 337         return mpic->fixups[source].base != NULL;
 338 }
 339
 340
 341 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
 342 {
 343         struct mpic_irq_fixup *fixup = &mpic->fixups[source];
 344
 345         if (fixup->applebase) {
 346                 unsigned int soff = (fixup->index >> 3) & ~3;
 347                 unsigned int mask = 1U << (fixup->index & 0x1f);
 348                 writel(mask, fixup->applebase + soff);
 349         } else {
 350                 spin_lock(&mpic->fixup_lock);
 351                 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
 352                 writel(fixup->data, fixup->base + 4);
 353                 spin_unlock(&mpic->fixup_lock);
 354         }
 355 }
 356
 357 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
 358                                       unsigned int irqflags)
 359 {
 360         struct mpic_irq_fixup *fixup = &mpic->fixups[source];
 361         unsigned long flags;
 362         u32 tmp;
 363
 364         if (fixup->base == NULL)
 365                 return;
 366
 367         DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n",
 368             source, irqflags, fixup->index);
 369         spin_lock_irqsave(&mpic->fixup_lock, flags);
 370         /* Enable and configure */
 371         writeb(0x10 + 2 * fixup->index, fixup->base + 2);
 372         tmp = readl(fixup->base + 4);
 373         tmp &= ~(0x23U);
 374         if (irqflags & IRQ_LEVEL)
 375                 tmp |= 0x22;
 376         writel(tmp, fixup->base + 4);
 377         spin_unlock_irqrestore(&mpic->fixup_lock, flags);
 378
 379 #ifdef CONFIG_PM
 380         /* use the lowest bit inverted to the actual HW,
 381          * set if this fixup was enabled, clear otherwise */
 382         mpic->save_data[source].fixup_data = tmp | 1;
 383 #endif
 384 }
 385
 386 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source,
 387                                        unsigned int irqflags)
 388 {
 389         struct mpic_irq_fixup *fixup = &mpic->fixups[source];
 390         unsigned long flags;
 391         u32 tmp;
 392
 393         if (fixup->base == NULL)
 394                 return;
 395
 396         DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags);
 397
 398         /* Disable */
 399         spin_lock_irqsave(&mpic->fixup_lock, flags);
 400         writeb(0x10 + 2 * fixup->index, fixup->base + 2);
 401         tmp = readl(fixup->base + 4);
 402         tmp |= 1;
 403         writel(tmp, fixup->base + 4);
 404         spin_unlock_irqrestore(&mpic->fixup_lock, flags);
 405
 406 #ifdef CONFIG_PM
 407         /* use the lowest bit inverted to the actual HW,
 408          * set if this fixup was enabled, clear otherwise */
 409         mpic->save_data[source].fixup_data = tmp & ~1;
 410 #endif
 411 }
 412
 413 #ifdef CONFIG_PCI_MSI
 414 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
 415                                     unsigned int devfn)
 416 {
 417         u8 __iomem *base;
 418         u8 pos, flags;
 419         u64 addr = 0;
 420
 421         for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
 422              pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
 423                 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
 424                 if (id == PCI_CAP_ID_HT) {
 425                         id = readb(devbase + pos + 3);
 426                         if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
 427                                 break;
 428                 }
 429         }
 430
 431         if (pos == 0)
 432                 return;
 433
 434         base = devbase + pos;
 435
 436         flags = readb(base + HT_MSI_FLAGS);
 437         if (!(flags & HT_MSI_FLAGS_FIXED)) {
 438                 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
 439                 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
 440         }
 441
 442         printk(KERN_DEBUG "mpic:   - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
 443                 PCI_SLOT(devfn), PCI_FUNC(devfn),
 444                 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
 445
 446         if (!(flags & HT_MSI_FLAGS_ENABLE))
 447                 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
 448 }
 449 #else
 450 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
 451                                     unsigned int devfn)
 452 {
 453         return;
 454 }
 455 #endif
 456
 457 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
 458                                     unsigned int devfn, u32 vdid)
 459 {
 460         int i, irq, n;
 461         u8 __iomem *base;
 462         u32 tmp;
 463         u8 pos;
 464
 465         for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
 466              pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
 467                 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
 468                 if (id == PCI_CAP_ID_HT) {
 469                         id = readb(devbase + pos + 3);
 470                         if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
 471                                 break;
 472                 }
 473         }
 474         if (pos == 0)
 475                 return;
 476
 477         base = devbase + pos;
 478         writeb(0x01, base + 2);
 479         n = (readl(base + 4) >> 16) & 0xff;
 480
 481         printk(KERN_INFO "mpic:   - HT:%02x.%x [0x%02x] vendor %04x device %04x"
 482                " has %d irqs\n",
 483                devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
 484
 485         for (i = 0; i <= n; i++) {
 486                 writeb(0x10 + 2 * i, base + 2);
 487                 tmp = readl(base + 4);
 488                 irq = (tmp >> 16) & 0xff;
 489                 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
 490                 /* mask it , will be unmasked later */
 491                 tmp |= 0x1;
 492                 writel(tmp, base + 4);
 493                 mpic->fixups[irq].index = i;
 494                 mpic->fixups[irq].base = base;
 495                 /* Apple HT PIC has a non-standard way of doing EOIs */
 496                 if ((vdid & 0xffff) == 0x106b)
 497                         mpic->fixups[irq].applebase = devbase + 0x60;
 498                 else
 499                         mpic->fixups[irq].applebase = NULL;
 500                 writeb(0x11 + 2 * i, base + 2);
 501                 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
 502         }
 503 }
 504
 505
 506 static void __init mpic_scan_ht_pics(struct mpic *mpic)
 507 {
 508         unsigned int devfn;
 509         u8 __iomem *cfgspace;
 510
 511         printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
 512
 513         /* Allocate fixups array */
 514         mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL);
 515         BUG_ON(mpic->fixups == NULL);
 516
 517         /* Init spinlock */
 518         spin_lock_init(&mpic->fixup_lock);
 519
 520         /* Map U3 config space. We assume all IO-APICs are on the primary bus
 521          * so we only need to map 64kB.
 522          */
 523         cfgspace = ioremap(0xf2000000, 0x10000);
 524         BUG_ON(cfgspace == NULL);
 525
 526         /* Now we scan all slots. We do a very quick scan, we read the header
 527          * type, vendor ID and device ID only, that's plenty enough
 528          */
 529         for (devfn = 0; devfn < 0x100; devfn++) {
 530                 u8 __iomem *devbase = cfgspace + (devfn << 8);
 531                 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
 532                 u32 l = readl(devbase + PCI_VENDOR_ID);
 533                 u16 s;
 534
 535                 DBG("devfn %x, l: %x\n", devfn, l);
 536
 537                 /* If no device, skip */
 538                 if (l == 0xffffffff || l == 0x00000000 ||
 539                     l == 0x0000ffff || l == 0xffff0000)
 540                         goto next;
 541                 /* Check if is supports capability lists */
 542                 s = readw(devbase + PCI_STATUS);
 543                 if (!(s & PCI_STATUS_CAP_LIST))
 544                         goto next;
 545
 546                 mpic_scan_ht_pic(mpic, devbase, devfn, l);
 547                 mpic_scan_ht_msi(mpic, devbase, devfn);
 548
 549         next:
 550                 /* next device, if function 0 */
 551                 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
 552                         devfn += 7;
 553         }
 554 }
 555
 556 #else /* CONFIG_MPIC_U3_HT_IRQS */
 557
 558 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
 559 {
 560         return 0;
 561 }
 562
 563 static void __init mpic_scan_ht_pics(struct mpic *mpic)
 564 {
 565 }
 566
 567 #endif /* CONFIG_MPIC_U3_HT_IRQS */
 568
 569 #ifdef CONFIG_SMP
 570 static int irq_choose_cpu(unsigned int virt_irq)
 571 {
 572         cpumask_t mask;
 573         int cpuid;
 574
 575         cpumask_copy(&mask, irq_desc[virt_irq].affinity);
 576         if (cpus_equal(mask, CPU_MASK_ALL)) {
 577                 static int irq_rover;
 578                 static DEFINE_SPINLOCK(irq_rover_lock);
 579                 unsigned long flags;
 580
 581                 /* Round-robin distribution... */
 582         do_round_robin:
 583                 spin_lock_irqsave(&irq_rover_lock, flags);
 584
 585                 while (!cpu_online(irq_rover)) {
 586                         if (++irq_rover >= NR_CPUS)
 587                                 irq_rover = 0;
 588                 }
 589                 cpuid = irq_rover;
 590                 do {
 591                         if (++irq_rover >= NR_CPUS)
 592                                 irq_rover = 0;
 593                 } while (!cpu_online(irq_rover));
 594
 595                 spin_unlock_irqrestore(&irq_rover_lock, flags);
 596         } else {
 597                 cpumask_t tmp;
 598
 599                 cpus_and(tmp, cpu_online_map, mask);
 600
 601                 if (cpus_empty(tmp))
 602                         goto do_round_robin;
 603
 604                 cpuid = first_cpu(tmp);
 605         }
 606
 607         return get_hard_smp_processor_id(cpuid);
 608 }
 609 #else
 610 static int irq_choose_cpu(unsigned int virt_irq)
 611 {
 612         return hard_smp_processor_id();
 613 }
 614 #endif
 615
 616 #define mpic_irq_to_hw(virq)    ((unsigned int)irq_map[virq].hwirq)
 617
 618 /* Find an mpic associated with a given linux interrupt */
 619 static struct mpic *mpic_find(unsigned int irq)
 620 {
 621         if (irq < NUM_ISA_INTERRUPTS)
 622                 return NULL;
 623
 624         return irq_desc[irq].chip_data;
 625 }
 626
 627 /* Determine if the linux irq is an IPI */
 628 static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)
 629 {
 630         unsigned int src = mpic_irq_to_hw(irq);
 631
 632         return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
 633 }
 634
 635
 636 /* Convert a cpu mask from logical to physical cpu numbers. */
 637 static inline u32 mpic_physmask(u32 cpumask)
 638 {
 639         int i;
 640         u32 mask = 0;
 641
 642         for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)
 643                 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
 644         return mask;
 645 }
 646
 647 #ifdef CONFIG_SMP
 648 /* Get the mpic structure from the IPI number */
 649 static inline struct mpic * mpic_from_ipi(unsigned int ipi)
 650 {
 651         return irq_desc[ipi].chip_data;
 652 }
 653 #endif
 654
 655 /* Get the mpic structure from the irq number */
 656 static inline struct mpic * mpic_from_irq(unsigned int irq)
 657 {
 658         return irq_desc[irq].chip_data;
 659 }
 660
 661 /* Send an EOI */
 662 static inline void mpic_eoi(struct mpic *mpic)
 663 {
 664         mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
 665         (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
 666 }
 667
 668 /*
 669  * Linux descriptor level callbacks
 670  */
 671
 672
 673 void mpic_unmask_irq(unsigned int irq)
 674 {
 675         unsigned int loops = 100000;
 676         struct mpic *mpic = mpic_from_irq(irq);
 677         unsigned int src = mpic_irq_to_hw(irq);
 678
 679         DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);
 680
 681         mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
 682                        mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
 683                        ~MPIC_VECPRI_MASK);
 684         /* make sure mask gets to controller before we return to user */
 685         do {
 686                 if (!loops--) {
 687                         printk(KERN_ERR "mpic_enable_irq timeout\n");
 688                         break;
 689                 }
 690         } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
 691 }
 692
 693 void mpic_mask_irq(unsigned int irq)
 694 {
 695         unsigned int loops = 100000;
 696         struct mpic *mpic = mpic_from_irq(irq);
 697         unsigned int src = mpic_irq_to_hw(irq);
 698
 699         DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
 700
 701         mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
 702                        mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
 703                        MPIC_VECPRI_MASK);
 704
 705         /* make sure mask gets to controller before we return to user */
 706         do {
 707                 if (!loops--) {
 708                         printk(KERN_ERR "mpic_enable_irq timeout\n");
 709                         break;
 710                 }
 711         } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
 712 }
 713
 714 void mpic_end_irq(unsigned int irq)
 715 {
 716         struct mpic *mpic = mpic_from_irq(irq);
 717
 718 #ifdef DEBUG_IRQ
 719         DBG("%s: end_irq: %d\n", mpic->name, irq);
 720 #endif
 721         /* We always EOI on end_irq() even for edge interrupts since that
 722          * should only lower the priority, the MPIC should have properly
 723          * latched another edge interrupt coming in anyway
 724          */
 725
 726         mpic_eoi(mpic);
 727 }
 728
 729 #ifdef CONFIG_MPIC_U3_HT_IRQS
 730
 731 static void mpic_unmask_ht_irq(unsigned int irq)
 732 {
 733         struct mpic *mpic = mpic_from_irq(irq);
 734         unsigned int src = mpic_irq_to_hw(irq);
 735
 736         mpic_unmask_irq(irq);
 737
 738         if (irq_desc[irq].status & IRQ_LEVEL)
 739                 mpic_ht_end_irq(mpic, src);
 740 }
 741
 742 static unsigned int mpic_startup_ht_irq(unsigned int irq)
 743 {
 744         struct mpic *mpic = mpic_from_irq(irq);
 745         unsigned int src = mpic_irq_to_hw(irq);
 746
 747         mpic_unmask_irq(irq);
 748         mpic_startup_ht_interrupt(mpic, src, irq_desc[irq].status);
 749
 750         return 0;
 751 }
 752
 753 static void mpic_shutdown_ht_irq(unsigned int irq)
 754 {
 755         struct mpic *mpic = mpic_from_irq(irq);
 756         unsigned int src = mpic_irq_to_hw(irq);
 757
 758         mpic_shutdown_ht_interrupt(mpic, src, irq_desc[irq].status);
 759         mpic_mask_irq(irq);
 760 }
 761
 762 static void mpic_end_ht_irq(unsigned int irq)
 763 {
 764         struct mpic *mpic = mpic_from_irq(irq);
 765         unsigned int src = mpic_irq_to_hw(irq);
 766
 767 #ifdef DEBUG_IRQ
 768         DBG("%s: end_irq: %d\n", mpic->name, irq);
 769 #endif
 770         /* We always EOI on end_irq() even for edge interrupts since that
 771          * should only lower the priority, the MPIC should have properly
 772          * latched another edge interrupt coming in anyway
 773          */
 774
 775         if (irq_desc[irq].status & IRQ_LEVEL)
 776                 mpic_ht_end_irq(mpic, src);
 777         mpic_eoi(mpic);
 778 }
 779 #endif /* !CONFIG_MPIC_U3_HT_IRQS */
 780
 781 #ifdef CONFIG_SMP
 782
 783 static void mpic_unmask_ipi(unsigned int irq)
 784 {
 785         struct mpic *mpic = mpic_from_ipi(irq);
 786         unsigned int src = mpic_irq_to_hw(irq) - mpic->ipi_vecs[0];
 787
 788         DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src);
 789         mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
 790 }
 791
 792 static void mpic_mask_ipi(unsigned int irq)
 793 {
 794         /* NEVER disable an IPI... that's just plain wrong! */
 795 }
 796
 797 static void mpic_end_ipi(unsigned int irq)
 798 {
 799         struct mpic *mpic = mpic_from_ipi(irq);
 800
 801         /*
 802          * IPIs are marked IRQ_PER_CPU. This has the side effect of
 803          * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
 804          * applying to them. We EOI them late to avoid re-entering.
 805          * We mark IPI's with IRQF_DISABLED as they must run with
 806          * irqs disabled.
 807          */
 808         mpic_eoi(mpic);
 809 }
 810
 811 #endif /* CONFIG_SMP */
 812
 813 int mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask)
 814 {
 815         struct mpic *mpic = mpic_from_irq(irq);
 816         unsigned int src = mpic_irq_to_hw(irq);
 817
 818         if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
 819                 int cpuid = irq_choose_cpu(irq);
 820
 821                 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
 822         } else {
 823                 cpumask_t tmp;
 824
 825                 cpumask_and(&tmp, cpumask, cpu_online_mask);
 826
 827                 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
 828                                mpic_physmask(cpus_addr(tmp)[0]));
 829         }
 830
 831         return 0;
 832 }
 833
 834 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
 835 {
 836         /* Now convert sense value */
 837         switch(type & IRQ_TYPE_SENSE_MASK) {
 838         case IRQ_TYPE_EDGE_RISING:
 839                 return MPIC_INFO(VECPRI_SENSE_EDGE) |
 840                        MPIC_INFO(VECPRI_POLARITY_POSITIVE);
 841         case IRQ_TYPE_EDGE_FALLING:
 842         case IRQ_TYPE_EDGE_BOTH:
 843                 return MPIC_INFO(VECPRI_SENSE_EDGE) |
 844                        MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
 845         case IRQ_TYPE_LEVEL_HIGH:
 846                 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
 847                        MPIC_INFO(VECPRI_POLARITY_POSITIVE);
 848         case IRQ_TYPE_LEVEL_LOW:
 849         default:
 850                 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
 851                        MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
 852         }
 853 }
 854
 855 int mpic_set_irq_type(unsigned int virq, unsigned int flow_type)
 856 {
 857         struct mpic *mpic = mpic_from_irq(virq);
 858         unsigned int src = mpic_irq_to_hw(virq);
 859         struct irq_desc *desc = get_irq_desc(virq);
 860         unsigned int vecpri, vold, vnew;
 861
 862         DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
 863             mpic, virq, src, flow_type);
 864
 865         if (src >= mpic->irq_count)
 866                 return -EINVAL;
 867
 868         if (flow_type == IRQ_TYPE_NONE)
 869                 if (mpic->senses && src < mpic->senses_count)
 870                         flow_type = mpic->senses[src];
 871         if (flow_type == IRQ_TYPE_NONE)
 872                 flow_type = IRQ_TYPE_LEVEL_LOW;
 873
 874         desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
 875         desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
 876         if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
 877                 desc->status |= IRQ_LEVEL;
 878
 879         if (mpic_is_ht_interrupt(mpic, src))
 880                 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
 881                         MPIC_VECPRI_SENSE_EDGE;
 882         else
 883                 vecpri = mpic_type_to_vecpri(mpic, flow_type);
 884
 885         vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
 886         vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
 887                         MPIC_INFO(VECPRI_SENSE_MASK));
 888         vnew |= vecpri;
 889         if (vold != vnew)
 890                 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
 891
 892         return 0;
 893 }
 894
 895 void mpic_set_vector(unsigned int virq, unsigned int vector)
 896 {
 897         struct mpic *mpic = mpic_from_irq(virq);
 898         unsigned int src = mpic_irq_to_hw(virq);
 899         unsigned int vecpri;
 900
 901         DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
 902             mpic, virq, src, vector);
 903
 904         if (src >= mpic->irq_count)
 905                 return;
 906
 907         vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
 908         vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
 909         vecpri |= vector;
 910         mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
 911 }
 912
 913 static struct irq_chip mpic_irq_chip = {
 914         .mask           = mpic_mask_irq,
 915         .unmask         = mpic_unmask_irq,
 916         .eoi            = mpic_end_irq,
 917         .set_type       = mpic_set_irq_type,
 918 };
 919
 920 #ifdef CONFIG_SMP
 921 static struct irq_chip mpic_ipi_chip = {
 922         .mask           = mpic_mask_ipi,
 923         .unmask         = mpic_unmask_ipi,
 924         .eoi            = mpic_end_ipi,
 925 };
 926 #endif /* CONFIG_SMP */
 927
 928 #ifdef CONFIG_MPIC_U3_HT_IRQS
 929 static struct irq_chip mpic_irq_ht_chip = {
 930         .startup        = mpic_startup_ht_irq,
 931         .shutdown       = mpic_shutdown_ht_irq,
 932         .mask           = mpic_mask_irq,
 933         .unmask         = mpic_unmask_ht_irq,
 934         .eoi            = mpic_end_ht_irq,
 935         .set_type       = mpic_set_irq_type,
 936 };
 937 #endif /* CONFIG_MPIC_U3_HT_IRQS */
 938
 939
 940 static int mpic_host_match(struct irq_host *h, struct device_node *node)
 941 {
 942         /* Exact match, unless mpic node is NULL */
 943         return h->of_node == NULL || h->of_node == node;
 944 }
 945
 946 static int mpic_host_map(struct irq_host *h, unsigned int virq,
 947                          irq_hw_number_t hw)
 948 {
 949         struct mpic *mpic = h->host_data;
 950         struct irq_chip *chip;
 951
 952         DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
 953
 954         if (hw == mpic->spurious_vec)
 955                 return -EINVAL;
 956         if (mpic->protected && test_bit(hw, mpic->protected))
 957                 return -EINVAL;
 958
 959 #ifdef CONFIG_SMP
 960         else if (hw >= mpic->ipi_vecs[0]) {
 961                 WARN_ON(!(mpic->flags & MPIC_PRIMARY));
 962
 963                 DBG("mpic: mapping as IPI\n");
 964                 set_irq_chip_data(virq, mpic);
 965                 set_irq_chip_and_handler(virq, &mpic->hc_ipi,
 966                                          handle_percpu_irq);
 967                 return 0;
 968         }
 969 #endif /* CONFIG_SMP */
 970
 971         if (hw >= mpic->irq_count)
 972                 return -EINVAL;
 973
 974         mpic_msi_reserve_hwirq(mpic, hw);
 975
 976         /* Default chip */
 977         chip = &mpic->hc_irq;
 978
 979 #ifdef CONFIG_MPIC_U3_HT_IRQS
 980         /* Check for HT interrupts, override vecpri */
 981         if (mpic_is_ht_interrupt(mpic, hw))
 982                 chip = &mpic->hc_ht_irq;
 983 #endif /* CONFIG_MPIC_U3_HT_IRQS */
 984
 985         DBG("mpic: mapping to irq chip @%p\n", chip);
 986
 987         set_irq_chip_data(virq, mpic);
 988         set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq);
 989
 990         /* Set default irq type */
 991         set_irq_type(virq, IRQ_TYPE_NONE);
 992
 993         return 0;
 994 }
 995
 996 static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
 997                            u32 *intspec, unsigned int intsize,
 998                            irq_hw_number_t *out_hwirq, unsigned int *out_flags)
 999
1000 {
1001         static unsigned char map_mpic_senses[4] = {
1002                 IRQ_TYPE_EDGE_RISING,
1003                 IRQ_TYPE_LEVEL_LOW,
1004                 IRQ_TYPE_LEVEL_HIGH,
1005                 IRQ_TYPE_EDGE_FALLING,
1006         };
1007
1008         *out_hwirq = intspec[0];
1009         if (intsize > 1) {
1010                 u32 mask = 0x3;
1011
1012                 /* Apple invented a new race of encoding on machines with
1013                  * an HT APIC. They encode, among others, the index within
1014                  * the HT APIC. We don't care about it here since thankfully,
1015                  * it appears that they have the APIC already properly
1016                  * configured, and thus our current fixup code that reads the
1017                  * APIC config works fine. However, we still need to mask out
1018                  * bits in the specifier to make sure we only get bit 0 which
1019                  * is the level/edge bit (the only sense bit exposed by Apple),
1020                  * as their bit 1 means something else.
1021                  */
1022                 if (machine_is(powermac))
1023                         mask = 0x1;
1024                 *out_flags = map_mpic_senses[intspec[1] & mask];
1025         } else
1026                 *out_flags = IRQ_TYPE_NONE;
1027
1028         DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1029             intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
1030
1031         return 0;
1032 }
1033
1034 static struct irq_host_ops mpic_host_ops = {
1035         .match = mpic_host_match,
1036         .map = mpic_host_map,
1037         .xlate = mpic_host_xlate,
1038 };
1039
1040 /*
1041  * Exported functions
1042  */
1043
1044 struct mpic * __init mpic_alloc(struct device_node *node,
1045                                 phys_addr_t phys_addr,
1046                                 unsigned int flags,
1047                                 unsigned int isu_size,
1048                                 unsigned int irq_count,
1049                                 const char *name)
1050 {
1051         struct mpic     *mpic;
1052         u32             greg_feature;
1053         const char      *vers;
1054         int             i;
1055         int             intvec_top;
1056         u64             paddr = phys_addr;
1057
1058         mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
1059         if (mpic == NULL)
1060                 return NULL;
1061
1062         mpic->name = name;
1063
1064         mpic->hc_irq = mpic_irq_chip;
1065         mpic->hc_irq.typename = name;
1066         if (flags & MPIC_PRIMARY)
1067                 mpic->hc_irq.set_affinity = mpic_set_affinity;
1068 #ifdef CONFIG_MPIC_U3_HT_IRQS
1069         mpic->hc_ht_irq = mpic_irq_ht_chip;
1070         mpic->hc_ht_irq.typename = name;
1071         if (flags & MPIC_PRIMARY)
1072                 mpic->hc_ht_irq.set_affinity = mpic_set_affinity;
1073 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1074
1075 #ifdef CONFIG_SMP
1076         mpic->hc_ipi = mpic_ipi_chip;
1077         mpic->hc_ipi.typename = name;
1078 #endif /* CONFIG_SMP */
1079
1080         mpic->flags = flags;
1081         mpic->isu_size = isu_size;
1082         mpic->irq_count = irq_count;
1083         mpic->num_sources = 0; /* so far */
1084
1085         if (flags & MPIC_LARGE_VECTORS)
1086                 intvec_top = 2047;
1087         else
1088                 intvec_top = 255;
1089
1090         mpic->timer_vecs[0] = intvec_top - 8;
1091         mpic->timer_vecs[1] = intvec_top - 7;
1092         mpic->timer_vecs[2] = intvec_top - 6;
1093         mpic->timer_vecs[3] = intvec_top - 5;
1094         mpic->ipi_vecs[0]   = intvec_top - 4;
1095         mpic->ipi_vecs[1]   = intvec_top - 3;
1096         mpic->ipi_vecs[2]   = intvec_top - 2;
1097         mpic->ipi_vecs[3]   = intvec_top - 1;
1098         mpic->spurious_vec  = intvec_top;
1099
1100         /* Check for "big-endian" in device-tree */
1101         if (node && of_get_property(node, "big-endian", NULL) != NULL)
1102                 mpic->flags |= MPIC_BIG_ENDIAN;
1103
1104         /* Look for protected sources */
1105         if (node) {
1106                 int psize;
1107                 unsigned int bits, mapsize;
1108                 const u32 *psrc =
1109                         of_get_property(node, "protected-sources", &psize);
1110                 if (psrc) {
1111                         psize /= 4;
1112                         bits = intvec_top + 1;
1113                         mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long);
1114                         mpic->protected = kzalloc(mapsize, GFP_KERNEL);
1115                         BUG_ON(mpic->protected == NULL);
1116                         for (i = 0; i < psize; i++) {
1117                                 if (psrc[i] > intvec_top)
1118                                         continue;
1119                                 __set_bit(psrc[i], mpic->protected);
1120                         }
1121                 }
1122         }
1123
1124 #ifdef CONFIG_MPIC_WEIRD
1125         mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
1126 #endif
1127
1128         /* default register type */
1129         mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ?
1130                 mpic_access_mmio_be : mpic_access_mmio_le;
1131
1132         /* If no physical address is passed in, a device-node is mandatory */
1133         BUG_ON(paddr == 0 && node == NULL);
1134
1135         /* If no physical address passed in, check if it's dcr based */
1136         if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) {
1137 #ifdef CONFIG_PPC_DCR
1138                 mpic->flags |= MPIC_USES_DCR;
1139                 mpic->reg_type = mpic_access_dcr;
1140 #else
1141                 BUG();
1142 #endif /* CONFIG_PPC_DCR */
1143         }
1144
1145         /* If the MPIC is not DCR based, and no physical address was passed
1146          * in, try to obtain one
1147          */
1148         if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {
1149                 const u32 *reg = of_get_property(node, "reg", NULL);
1150                 BUG_ON(reg == NULL);
1151                 paddr = of_translate_address(node, reg);
1152                 BUG_ON(paddr == OF_BAD_ADDR);
1153         }
1154
1155         /* Map the global registers */
1156         mpic_map(mpic, node, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1157         mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1158
1159         /* Reset */
1160         if (flags & MPIC_WANTS_RESET) {
1161                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1162                            mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1163                            | MPIC_GREG_GCONF_RESET);
1164                 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1165                        & MPIC_GREG_GCONF_RESET)
1166                         mb();
1167         }
1168
1169         /* CoreInt */
1170         if (flags & MPIC_ENABLE_COREINT)
1171                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1172                            mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1173                            | MPIC_GREG_GCONF_COREINT);
1174
1175         if (flags & MPIC_ENABLE_MCK)
1176                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1177                            mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1178                            | MPIC_GREG_GCONF_MCK);
1179
1180         /* Read feature register, calculate num CPUs and, for non-ISU
1181          * MPICs, num sources as well. On ISU MPICs, sources are counted
1182          * as ISUs are added
1183          */
1184         greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1185         mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK)
1186                           >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
1187         if (isu_size == 0) {
1188                 if (flags & MPIC_BROKEN_FRR_NIRQS)
1189                         mpic->num_sources = mpic->irq_count;
1190                 else
1191                         mpic->num_sources =
1192                                 ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1193                                  >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
1194         }
1195
1196         /* Map the per-CPU registers */
1197         for (i = 0; i < mpic->num_cpus; i++) {
1198                 mpic_map(mpic, node, paddr, &mpic->cpuregs[i],
1199                          MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE),
1200                          0x1000);
1201         }
1202
1203         /* Initialize main ISU if none provided */
1204         if (mpic->isu_size == 0) {
1205                 mpic->isu_size = mpic->num_sources;
1206                 mpic_map(mpic, node, paddr, &mpic->isus[0],
1207                          MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1208         }
1209         mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1210         mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1211
1212         mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
1213                                        isu_size ? isu_size : mpic->num_sources,
1214                                        &mpic_host_ops,
1215                                        flags & MPIC_LARGE_VECTORS ? 2048 : 256);
1216         if (mpic->irqhost == NULL)
1217                 return NULL;
1218
1219         mpic->irqhost->host_data = mpic;
1220
1221         /* Display version */
1222         switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1223         case 1:
1224                 vers = "1.0";
1225                 break;
1226         case 2:
1227                 vers = "1.2";
1228                 break;
1229         case 3:
1230                 vers = "1.3";
1231                 break;
1232         default:
1233                 vers = "<unknown>";
1234                 break;
1235         }
1236         printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1237                " max %d CPUs\n",
1238                name, vers, (unsigned long long)paddr, mpic->num_cpus);
1239         printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1240                mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1241
1242         mpic->next = mpics;
1243         mpics = mpic;
1244
1245         if (flags & MPIC_PRIMARY) {
1246                 mpic_primary = mpic;
1247                 irq_set_default_host(mpic->irqhost);
1248         }
1249
1250         return mpic;
1251 }
1252
1253 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1254                             phys_addr_t paddr)
1255 {
1256         unsigned int isu_first = isu_num * mpic->isu_size;
1257
1258         BUG_ON(isu_num >= MPIC_MAX_ISU);
1259
1260         mpic_map(mpic, mpic->irqhost->of_node,
1261                  paddr, &mpic->isus[isu_num], 0,
1262                  MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1263
1264         if ((isu_first + mpic->isu_size) > mpic->num_sources)
1265                 mpic->num_sources = isu_first + mpic->isu_size;
1266 }
1267
1268 void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
1269 {
1270         mpic->senses = senses;
1271         mpic->senses_count = count;
1272 }
1273
1274 void __init mpic_init(struct mpic *mpic)
1275 {
1276         int i;
1277         int cpu;
1278
1279         BUG_ON(mpic->num_sources == 0);
1280
1281         printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1282
1283         /* Set current processor priority to max */
1284         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1285
1286         /* Initialize timers: just disable them all */
1287         for (i = 0; i < 4; i++) {
1288                 mpic_write(mpic->tmregs,
1289                            i * MPIC_INFO(TIMER_STRIDE) +
1290                            MPIC_INFO(TIMER_DESTINATION), 0);
1291                 mpic_write(mpic->tmregs,
1292                            i * MPIC_INFO(TIMER_STRIDE) +
1293                            MPIC_INFO(TIMER_VECTOR_PRI),
1294                            MPIC_VECPRI_MASK |
1295                            (mpic->timer_vecs[0] + i));
1296         }
1297
1298         /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1299         mpic_test_broken_ipi(mpic);
1300         for (i = 0; i < 4; i++) {
1301                 mpic_ipi_write(i,
1302                                MPIC_VECPRI_MASK |
1303                                (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1304                                (mpic->ipi_vecs[0] + i));
1305         }
1306
1307         /* Initialize interrupt sources */
1308         if (mpic->irq_count == 0)
1309                 mpic->irq_count = mpic->num_sources;
1310
1311         /* Do the HT PIC fixups on U3 broken mpic */
1312         DBG("MPIC flags: %x\n", mpic->flags);
1313         if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) {
1314                 mpic_scan_ht_pics(mpic);
1315                 mpic_u3msi_init(mpic);
1316         }
1317
1318         mpic_pasemi_msi_init(mpic);
1319
1320         if (mpic->flags & MPIC_PRIMARY)
1321                 cpu = hard_smp_processor_id();
1322         else
1323                 cpu = 0;
1324
1325         for (i = 0; i < mpic->num_sources; i++) {
1326                 /* start with vector = source number, and masked */
1327                 u32 vecpri = MPIC_VECPRI_MASK | i |
1328                         (8 << MPIC_VECPRI_PRIORITY_SHIFT);
1329
1330                 /* check if protected */
1331                 if (mpic->protected && test_bit(i, mpic->protected))
1332                         continue;
1333                 /* init hw */
1334                 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1335                 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1336         }
1337
1338         /* Init spurious vector */
1339         mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1340
1341         /* Disable 8259 passthrough, if supported */
1342         if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1343                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1344                            mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1345                            | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1346
1347         if (mpic->flags & MPIC_NO_BIAS)
1348                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1349                         mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1350                         | MPIC_GREG_GCONF_NO_BIAS);
1351
1352         /* Set current processor priority to 0 */
1353         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1354
1355 #ifdef CONFIG_PM
1356         /* allocate memory to save mpic state */
1357         mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data),
1358                                   GFP_KERNEL);
1359         BUG_ON(mpic->save_data == NULL);
1360 #endif
1361 }
1362
1363 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
1364 {
1365         u32 v;
1366
1367         v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1368         v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
1369         v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
1370         mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1371 }
1372
1373 void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1374 {
1375         unsigned long flags;
1376         u32 v;
1377
1378         spin_lock_irqsave(&mpic_lock, flags);
1379         v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1380         if (enable)
1381                 v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
1382         else
1383                 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
1384         mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1385         spin_unlock_irqrestore(&mpic_lock, flags);
1386 }
1387
1388 void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1389 {
1390         struct mpic *mpic = mpic_find(irq);
1391         unsigned int src = mpic_irq_to_hw(irq);
1392         unsigned long flags;
1393         u32 reg;
1394
1395         if (!mpic)
1396                 return;
1397
1398         spin_lock_irqsave(&mpic_lock, flags);
1399         if (mpic_is_ipi(mpic, irq)) {
1400                 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1401                         ~MPIC_VECPRI_PRIORITY_MASK;
1402                 mpic_ipi_write(src - mpic->ipi_vecs[0],
1403                                reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1404         } else {
1405                 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1406                         & ~MPIC_VECPRI_PRIORITY_MASK;
1407                 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1408                                reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1409         }
1410         spin_unlock_irqrestore(&mpic_lock, flags);
1411 }
1412
1413 void mpic_setup_this_cpu(void)
1414 {
1415 #ifdef CONFIG_SMP
1416         struct mpic *mpic = mpic_primary;
1417         unsigned long flags;
1418         u32 msk = 1 << hard_smp_processor_id();
1419         unsigned int i;
1420
1421         BUG_ON(mpic == NULL);
1422
1423         DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1424
1425         spin_lock_irqsave(&mpic_lock, flags);
1426
1427         /* let the mpic know we want intrs. default affinity is 0xffffffff
1428          * until changed via /proc. That's how it's done on x86. If we want
1429          * it differently, then we should make sure we also change the default
1430          * values of irq_desc[].affinity in irq.c.
1431          */
1432         if (distribute_irqs) {
1433                 for (i = 0; i < mpic->num_sources ; i++)
1434                         mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1435                                 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1436         }
1437
1438         /* Set current processor priority to 0 */
1439         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1440
1441         spin_unlock_irqrestore(&mpic_lock, flags);
1442 #endif /* CONFIG_SMP */
1443 }
1444
1445 int mpic_cpu_get_priority(void)
1446 {
1447         struct mpic *mpic = mpic_primary;
1448
1449         return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1450 }
1451
1452 void mpic_cpu_set_priority(int prio)
1453 {
1454         struct mpic *mpic = mpic_primary;
1455
1456         prio &= MPIC_CPU_TASKPRI_MASK;
1457         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1458 }
1459
1460 void mpic_teardown_this_cpu(int secondary)
1461 {
1462         struct mpic *mpic = mpic_primary;
1463         unsigned long flags;
1464         u32 msk = 1 << hard_smp_processor_id();
1465         unsigned int i;
1466
1467         BUG_ON(mpic == NULL);
1468
1469         DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1470         spin_lock_irqsave(&mpic_lock, flags);
1471
1472         /* let the mpic know we don't want intrs.  */
1473         for (i = 0; i < mpic->num_sources ; i++)
1474                 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1475                         mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1476
1477         /* Set current processor priority to max */
1478         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1479         /* We need to EOI the IPI since not all platforms reset the MPIC
1480          * on boot and new interrupts wouldn't get delivered otherwise.
1481          */
1482         mpic_eoi(mpic);
1483
1484         spin_unlock_irqrestore(&mpic_lock, flags);
1485 }
1486
1487
1488 void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask)
1489 {
1490         struct mpic *mpic = mpic_primary;
1491
1492         BUG_ON(mpic == NULL);
1493
1494 #ifdef DEBUG_IPI
1495         DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
1496 #endif
1497
1498         mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1499                        ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),
1500                        mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0]));
1501 }
1502
1503 static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1504 {
1505         u32 src;
1506
1507         src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
1508 #ifdef DEBUG_LOW
1509         DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1510 #endif
1511         if (unlikely(src == mpic->spurious_vec)) {
1512                 if (mpic->flags & MPIC_SPV_EOI)
1513                         mpic_eoi(mpic);
1514                 return NO_IRQ;
1515         }
1516         if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1517                 if (printk_ratelimit())
1518                         printk(KERN_WARNING "%s: Got protected source %d !\n",
1519                                mpic->name, (int)src);
1520                 mpic_eoi(mpic);
1521                 return NO_IRQ;
1522         }
1523
1524         return irq_linear_revmap(mpic->irqhost, src);
1525 }
1526
1527 unsigned int mpic_get_one_irq(struct mpic *mpic)
1528 {
1529         return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
1530 }
1531
1532 unsigned int mpic_get_irq(void)
1533 {
1534         struct mpic *mpic = mpic_primary;
1535
1536         BUG_ON(mpic == NULL);
1537
1538         return mpic_get_one_irq(mpic);
1539 }
1540
1541 unsigned int mpic_get_coreint_irq(void)
1542 {
1543 #ifdef CONFIG_BOOKE
1544         struct mpic *mpic = mpic_primary;
1545         u32 src;
1546
1547         BUG_ON(mpic == NULL);
1548
1549         src = mfspr(SPRN_EPR);
1550
1551         if (unlikely(src == mpic->spurious_vec)) {
1552                 if (mpic->flags & MPIC_SPV_EOI)
1553                         mpic_eoi(mpic);
1554                 return NO_IRQ;
1555         }
1556         if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1557                 if (printk_ratelimit())
1558                         printk(KERN_WARNING "%s: Got protected source %d !\n",
1559                                mpic->name, (int)src);
1560                 return NO_IRQ;
1561         }
1562
1563         return irq_linear_revmap(mpic->irqhost, src);
1564 #else
1565         return NO_IRQ;
1566 #endif
1567 }
1568
1569 unsigned int mpic_get_mcirq(void)
1570 {
1571         struct mpic *mpic = mpic_primary;
1572
1573         BUG_ON(mpic == NULL);
1574
1575         return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
1576 }
1577
1578 #ifdef CONFIG_SMP
1579 void mpic_request_ipis(void)
1580 {
1581         struct mpic *mpic = mpic_primary;
1582         int i;
1583         BUG_ON(mpic == NULL);
1584
1585         printk(KERN_INFO "mpic: requesting IPIs ... \n");
1586
1587         for (i = 0; i < 4; i++) {
1588                 unsigned int vipi = irq_create_mapping(mpic->irqhost,
1589                                                        mpic->ipi_vecs[0] + i);
1590                 if (vipi == NO_IRQ) {
1591                         printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
1592                         continue;
1593                 }
1594                 smp_request_message_ipi(vipi, i);
1595         }
1596 }
1597
1598 void smp_mpic_message_pass(int target, int msg)
1599 {
1600         /* make sure we're sending something that translates to an IPI */
1601         if ((unsigned int)msg > 3) {
1602                 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1603                        smp_processor_id(), msg);
1604                 return;
1605         }
1606         switch (target) {
1607         case MSG_ALL:
1608                 mpic_send_ipi(msg, 0xffffffff);
1609                 break;
1610         case MSG_ALL_BUT_SELF:
1611                 mpic_send_ipi(msg, 0xffffffff & ~(1 << smp_processor_id()));
1612                 break;
1613         default:
1614                 mpic_send_ipi(msg, 1 << target);
1615                 break;
1616         }
1617 }
1618
1619 int __init smp_mpic_probe(void)
1620 {
1621         int nr_cpus;
1622
1623         DBG("smp_mpic_probe()...\n");
1624
1625         nr_cpus = cpus_weight(cpu_possible_map);
1626
1627         DBG("nr_cpus: %d\n", nr_cpus);
1628
1629         if (nr_cpus > 1)
1630                 mpic_request_ipis();
1631
1632         return nr_cpus;
1633 }
1634
1635 void __devinit smp_mpic_setup_cpu(int cpu)
1636 {
1637         mpic_setup_this_cpu();
1638 }
1639 #endif /* CONFIG_SMP */
1640
1641 #ifdef CONFIG_PM
1642 static int mpic_suspend(struct sys_device *dev, pm_message_t state)
1643 {
1644         struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1645         int i;
1646
1647         for (i = 0; i < mpic->num_sources; i++) {
1648                 mpic->save_data[i].vecprio =
1649                         mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1650                 mpic->save_data[i].dest =
1651                         mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1652         }
1653
1654         return 0;
1655 }
1656
1657 static int mpic_resume(struct sys_device *dev)
1658 {
1659         struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1660         int i;
1661
1662         for (i = 0; i < mpic->num_sources; i++) {
1663                 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
1664                                mpic->save_data[i].vecprio);
1665                 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1666                                mpic->save_data[i].dest);
1667
1668 #ifdef CONFIG_MPIC_U3_HT_IRQS
1669         {
1670                 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1671
1672                 if (fixup->base) {
1673                         /* we use the lowest bit in an inverted meaning */
1674                         if ((mpic->save_data[i].fixup_data & 1) == 0)
1675                                 continue;
1676
1677                         /* Enable and configure */
1678                         writeb(0x10 + 2 * fixup->index, fixup->base + 2);
1679
1680                         writel(mpic->save_data[i].fixup_data & ~1,
1681                                fixup->base + 4);
1682                 }
1683         }
1684 #endif
1685         } /* end for loop */
1686
1687         return 0;
1688 }
1689 #endif
1690
1691 static struct sysdev_class mpic_sysclass = {
1692 #ifdef CONFIG_PM
1693         .resume = mpic_resume,
1694         .suspend = mpic_suspend,
1695 #endif
1696         .name = "mpic",
1697 };
1698
1699 static int mpic_init_sys(void)
1700 {
1701         struct mpic *mpic = mpics;
1702         int error, id = 0;
1703
1704         error = sysdev_class_register(&mpic_sysclass);
1705
1706         while (mpic && !error) {
1707                 mpic->sysdev.cls = &mpic_sysclass;
1708                 mpic->sysdev.id = id++;
1709                 error = sysdev_register(&mpic->sysdev);
1710                 mpic = mpic->next;
1711         }
1712         return error;
1713 }
1714
1715 device_initcall(mpic_init_sys);