SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/powerpc/sysdev/fsl_pci.c

   1 /*
   2  * MPC85xx/86xx PCI/PCIE support routing.
   3  *
   4  * Copyright 2007 Freescale Semiconductor, Inc
   5  *
   6  * Initial author: Xianghua Xiao <x.xiao@freescale.com>
   7  * Recode: ZHANG WEI <wei.zhang@freescale.com>
   8  * Rewrite the routing for Frescale PCI and PCI Express
   9  *      Roy Zang <tie-fei.zang@freescale.com>
  10  *
  11  * This program is free software; you can redistribute  it and/or modify it
  12  * under  the terms of  the GNU General  Public License as published by the
  13  * Free Software Foundation;  either version 2 of the  License, or (at your
  14  * option) any later version.
  15  */
  16 #include <linux/kernel.h>
  17 #include <linux/pci.h>
  18 #include <linux/delay.h>
  19 #include <linux/string.h>
  20 #include <linux/init.h>
  21 #include <linux/bootmem.h>
  22
  23 #include <asm/io.h>
  24 #include <asm/prom.h>
  25 #include <asm/pci-bridge.h>
  26 #include <asm/machdep.h>
  27 #include <sysdev/fsl_soc.h>
  28 #include <sysdev/fsl_pci.h>
  29
  30 /* atmu setup for fsl pci/pcie controller */
  31 void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc)
  32 {
  33         struct ccsr_pci __iomem *pci;
  34         int i;
  35
  36         pr_debug("PCI memory map start 0x%x, size 0x%x\n", rsrc->start,
  37                         rsrc->end - rsrc->start + 1);
  38         pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
  39
  40         /* Disable all windows (except powar0 since its ignored) */
  41         for(i = 1; i < 5; i++)
  42                 out_be32(&pci->pow[i].powar, 0);
  43         for(i = 0; i < 3; i++)
  44                 out_be32(&pci->piw[i].piwar, 0);
  45
  46         /* Setup outbound MEM window */
  47         for(i = 0; i < 3; i++)
  48                 if (hose->mem_resources[i].flags & IORESOURCE_MEM){
  49                         pr_debug("PCI MEM resource start 0x%08x, size 0x%08x.\n",
  50                                 hose->mem_resources[i].start,
  51                                 hose->mem_resources[i].end
  52                                   - hose->mem_resources[i].start + 1);
  53                         out_be32(&pci->pow[i+1].potar,
  54                                 (hose->mem_resources[i].start >> 12)
  55                                 & 0x000fffff);
  56                         out_be32(&pci->pow[i+1].potear, 0);
  57                         out_be32(&pci->pow[i+1].powbar,
  58                                 (hose->mem_resources[i].start >> 12)
  59                                 & 0x000fffff);
  60                         /* Enable, Mem R/W */
  61                         out_be32(&pci->pow[i+1].powar, 0x80044000
  62                                 | (__ilog2(hose->mem_resources[i].end
  63                                 - hose->mem_resources[i].start + 1) - 1));
  64                 }
  65
  66         /* Setup outbound IO window */
  67         if (hose->io_resource.flags & IORESOURCE_IO){
  68                 pr_debug("PCI IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n",
  69                         hose->io_resource.start,
  70                         hose->io_resource.end - hose->io_resource.start + 1,
  71                         hose->io_base_phys);
  72                 out_be32(&pci->pow[i+1].potar, (hose->io_resource.start >> 12)
  73                                 & 0x000fffff);
  74                 out_be32(&pci->pow[i+1].potear, 0);
  75                 out_be32(&pci->pow[i+1].powbar, (hose->io_base_phys >> 12)
  76                                 & 0x000fffff);
  77                 /* Enable, IO R/W */
  78                 out_be32(&pci->pow[i+1].powar, 0x80088000
  79                         | (__ilog2(hose->io_resource.end
  80                         - hose->io_resource.start + 1) - 1));
  81         }
  82
  83         /* Setup 2G inbound Memory Window @ 1 */
  84         out_be32(&pci->piw[2].pitar, 0x00000000);
  85         out_be32(&pci->piw[2].piwbar,0x00000000);
  86         out_be32(&pci->piw[2].piwar, PIWAR_2G);
  87 }
  88
  89 void __init setup_pci_cmd(struct pci_controller *hose)
  90 {
  91         u16 cmd;
  92         early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
  93         cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
  94                 | PCI_COMMAND_IO;
  95         early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
  96         early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
  97 }
  98
  99 static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev)
 100 {
 101         struct resource *res;
 102         int i, res_idx = PCI_BRIDGE_RESOURCES;
 103         struct pci_controller *hose;
 104
 105         /* if we aren't a PCIe don't bother */
 106         if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
 107                 return ;
 108
 109         /*
 110          * Make the bridge be transparent.
 111          */
 112         dev->transparent = 1;
 113
 114         hose = pci_bus_to_host(dev->bus);
 115         if (!hose) {
 116                 printk(KERN_ERR "Can't find hose for bus %d\n",
 117                        dev->bus->number);
 118                 return;
 119         }
 120
 121         if (hose->io_resource.flags) {
 122                 res = &dev->resource[res_idx++];
 123                 res->start = hose->io_resource.start;
 124                 res->end = hose->io_resource.end;
 125                 res->flags = hose->io_resource.flags;
 126         }
 127
 128         for (i = 0; i < 3; i++) {
 129                 res = &dev->resource[res_idx + i];
 130                 res->start = hose->mem_resources[i].start;
 131                 res->end = hose->mem_resources[i].end;
 132                 res->flags = hose->mem_resources[i].flags;
 133         }
 134 }
 135
 136 int __init fsl_pcie_check_link(struct pci_controller *hose)
 137 {
 138         u16 val;
 139         early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val);
 140         if (val < PCIE_LTSSM_L0)
 141                 return 1;
 142         return 0;
 143 }
 144
 145 void fsl_pcibios_fixup_bus(struct pci_bus *bus)
 146 {
 147         struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
 148         int i;
 149
 150         /* deal with bogus pci_bus when we don't have anything connected on PCIe */
 151         if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) {
 152                 if (bus->parent) {
 153                         for (i = 0; i < 4; ++i)
 154                                 bus->resource[i] = bus->parent->resource[i];
 155                 }
 156         }
 157 }
 158
 159 int __init fsl_add_bridge(struct device_node *dev, int is_primary)
 160 {
 161         int len;
 162         struct pci_controller *hose;
 163         struct resource rsrc;
 164         const int *bus_range;
 165
 166         pr_debug("Adding PCI host bridge %s\n", dev->full_name);
 167
 168         /* Fetch host bridge registers address */
 169         if (of_address_to_resource(dev, 0, &rsrc)) {
 170                 printk(KERN_WARNING "Can't get pci register base!");
 171                 return -ENOMEM;
 172         }
 173
 174         /* Get bus range if any */
 175         bus_range = of_get_property(dev, "bus-range", &len);
 176         if (bus_range == NULL || len < 2 * sizeof(int))
 177                 printk(KERN_WARNING "Can't get bus-range for %s, assume"
 178                         " bus 0\n", dev->full_name);
 179
 180         pci_assign_all_buses = 1;
 181         hose = pcibios_alloc_controller(dev);
 182         if (!hose)
 183                 return -ENOMEM;
 184
 185         hose->first_busno = bus_range ? bus_range[0] : 0x0;
 186         hose->last_busno = bus_range ? bus_range[1] : 0xff;
 187
 188         setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
 189                 PPC_INDIRECT_TYPE_BIG_ENDIAN);
 190         setup_pci_cmd(hose);
 191
 192         /* check PCI express link status */
 193         if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
 194                 hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG |
 195                         PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
 196                 if (fsl_pcie_check_link(hose))
 197                         hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
 198         }
 199
 200         printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx."
 201                 "Firmware bus number: %d->%d\n",
 202                 (unsigned long long)rsrc.start, hose->first_busno,
 203                 hose->last_busno);
 204
 205         pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
 206                 hose, hose->cfg_addr, hose->cfg_data);
 207
 208         /* Interpret the "ranges" property */
 209         /* This also maps the I/O region and sets isa_io/mem_base */
 210         pci_process_bridge_OF_ranges(hose, dev, is_primary);
 211
 212         /* Setup PEX window registers */
 213         setup_pci_atmu(hose, &rsrc);
 214
 215         return 0;
 216 }
 217
 218 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0012, quirk_fsl_pcie_transparent);
 219 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0013, quirk_fsl_pcie_transparent);
 220 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0014, quirk_fsl_pcie_transparent);
 221 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0015, quirk_fsl_pcie_transparent);
 222 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0018, quirk_fsl_pcie_transparent);
 223 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0019, quirk_fsl_pcie_transparent);
 224 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x001a, quirk_fsl_pcie_transparent);
 225 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0020, quirk_fsl_pcie_transparent);
 226 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0021, quirk_fsl_pcie_transparent);
 227 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0024, quirk_fsl_pcie_transparent);
 228 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0025, quirk_fsl_pcie_transparent);
 229 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent);
 230 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent);