2 * MPC83xx/85xx/86xx PCI/PCIE support routing.
4 * Copyright 2007-2009 Freescale Semiconductor, Inc.
5 * Copyright 2008-2009 MontaVista Software, Inc.
7 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
8 * Recode: ZHANG WEI <wei.zhang@freescale.com>
9 * Rewrite the routing for Frescale PCI and PCI Express
10 * Roy Zang <tie-fei.zang@freescale.com>
11 * MPC83xx PCI-Express support:
12 * Tony Li <tony.li@freescale.com>
13 * Anton Vorontsov <avorontsov@ru.mvista.com>
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 #include <linux/kernel.h>
21 #include <linux/pci.h>
22 #include <linux/delay.h>
23 #include <linux/string.h>
24 #include <linux/init.h>
25 #include <linux/bootmem.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/machdep.h>
31 #include <sysdev/fsl_soc.h>
32 #include <sysdev/fsl_pci.h>
34 static int fsl_pcie_bus_fixup;
36 static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
38 /* if we aren't a PCIe don't bother */
39 if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
42 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
43 fsl_pcie_bus_fixup = 1;
47 static int __init fsl_pcie_check_link(struct pci_controller *hose)
51 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
52 if (val < PCIE_LTSSM_L0)
57 #if defined(CONFIG_PPC_85xx) || defined(CONFIG_PPC_86xx)
58 static int __init setup_one_atmu(struct ccsr_pci __iomem *pci,
59 unsigned int index, const struct resource *res,
60 resource_size_t offset)
62 resource_size_t pci_addr = res->start - offset;
63 resource_size_t phys_addr = res->start;
64 resource_size_t size = res->end - res->start + 1;
65 u32 flags = 0x80044000; /* enable & mem R/W */
68 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
69 (u64)res->start, (u64)size);
71 if (res->flags & IORESOURCE_PREFETCH)
72 flags |= 0x10000000; /* enable relaxed ordering */
74 for (i = 0; size > 0; i++) {
75 unsigned int bits = min(__ilog2(size),
76 __ffs(pci_addr | phys_addr));
81 out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
82 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
83 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
84 out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
86 pci_addr += (resource_size_t)1U << bits;
87 phys_addr += (resource_size_t)1U << bits;
88 size -= (resource_size_t)1U << bits;
94 /* atmu setup for fsl pci/pcie controller */
95 static void __init setup_pci_atmu(struct pci_controller *hose,
96 struct resource *rsrc)
98 struct ccsr_pci __iomem *pci;
101 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
102 (u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1);
103 pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
105 dev_err(hose->parent, "Unable to map ATMU registers\n");
109 /* Disable all windows (except powar0 since it's ignored) */
110 for(i = 1; i < 5; i++)
111 out_be32(&pci->pow[i].powar, 0);
112 for(i = 0; i < 3; i++)
113 out_be32(&pci->piw[i].piwar, 0);
115 /* Setup outbound MEM window */
116 for(i = 0, j = 1; i < 3; i++) {
117 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
120 n = setup_one_atmu(pci, j, &hose->mem_resources[i],
121 hose->pci_mem_offset);
123 if (n < 0 || j >= 5) {
124 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
125 hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
130 /* Setup outbound IO window */
131 if (hose->io_resource.flags & IORESOURCE_IO) {
133 pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
135 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
136 "phy base 0x%016llx.\n",
137 (u64)hose->io_resource.start,
138 (u64)hose->io_resource.end - (u64)hose->io_resource.start + 1,
139 (u64)hose->io_base_phys);
140 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
141 out_be32(&pci->pow[j].potear, 0);
142 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
144 out_be32(&pci->pow[j].powar, 0x80088000
145 | (__ilog2(hose->io_resource.end
146 - hose->io_resource.start + 1) - 1));
150 /* Setup 2G inbound Memory Window @ 1 */
151 out_be32(&pci->piw[2].pitar, 0x00000000);
152 out_be32(&pci->piw[2].piwbar,0x00000000);
153 out_be32(&pci->piw[2].piwar, PIWAR_2G);
155 /* Save the base address and size covered by inbound window mappings */
156 hose->dma_window_base_cur = 0x00000000;
157 hose->dma_window_size = 0x80000000;
162 static void __init setup_pci_cmd(struct pci_controller *hose)
167 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
168 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
170 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
172 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
174 int pci_x_cmd = cap_x + PCI_X_CMD;
175 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
176 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
177 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
179 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
183 static void __init setup_pci_pcsrbar(struct pci_controller *hose)
185 #ifdef CONFIG_PCI_MSI
186 phys_addr_t immr_base;
188 immr_base = get_immrbase();
189 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, immr_base);
193 void fsl_pcibios_fixup_bus(struct pci_bus *bus)
195 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
198 if ((bus->parent == hose->bus) &&
199 ((fsl_pcie_bus_fixup &&
200 early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) ||
201 (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)))
203 for (i = 0; i < 4; ++i) {
204 struct resource *res = bus->resource[i];
205 struct resource *par = bus->parent->resource[i];
212 res->start = par->start;
214 res->flags = par->flags;
220 int __init fsl_add_bridge(struct device_node *dev, int is_primary)
223 struct pci_controller *hose;
224 struct resource rsrc;
225 const int *bus_range;
227 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
229 /* Fetch host bridge registers address */
230 if (of_address_to_resource(dev, 0, &rsrc)) {
231 printk(KERN_WARNING "Can't get pci register base!");
235 /* Get bus range if any */
236 bus_range = of_get_property(dev, "bus-range", &len);
237 if (bus_range == NULL || len < 2 * sizeof(int))
238 printk(KERN_WARNING "Can't get bus-range for %s, assume"
239 " bus 0\n", dev->full_name);
241 ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS);
242 hose = pcibios_alloc_controller(dev);
246 hose->first_busno = bus_range ? bus_range[0] : 0x0;
247 hose->last_busno = bus_range ? bus_range[1] : 0xff;
249 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
250 PPC_INDIRECT_TYPE_BIG_ENDIAN);
253 /* check PCI express link status */
254 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
255 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
256 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
257 if (fsl_pcie_check_link(hose))
258 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
261 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
262 "Firmware bus number: %d->%d\n",
263 (unsigned long long)rsrc.start, hose->first_busno,
266 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
267 hose, hose->cfg_addr, hose->cfg_data);
269 /* Interpret the "ranges" property */
270 /* This also maps the I/O region and sets isa_io/mem_base */
271 pci_process_bridge_OF_ranges(hose, dev, is_primary);
273 /* Setup PEX window registers */
274 setup_pci_atmu(hose, &rsrc);
276 /* Setup PEXCSRBAR */
277 setup_pci_pcsrbar(hose);
281 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548E, quirk_fsl_pcie_header);
282 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548, quirk_fsl_pcie_header);
283 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543E, quirk_fsl_pcie_header);
284 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_header);
285 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_header);
286 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_header);
287 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_header);
288 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569E, quirk_fsl_pcie_header);
289 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569, quirk_fsl_pcie_header);
290 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_header);
291 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_header);
292 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_header);
293 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_header);
294 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533E, quirk_fsl_pcie_header);
295 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533, quirk_fsl_pcie_header);
296 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_header);
297 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_header);
298 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572E, quirk_fsl_pcie_header);
299 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572, quirk_fsl_pcie_header);
300 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536E, quirk_fsl_pcie_header);
301 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536, quirk_fsl_pcie_header);
302 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_header);
303 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_header);
304 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header);
305 #endif /* CONFIG_PPC_85xx || CONFIG_PPC_86xx */
307 #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
308 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314E, quirk_fsl_pcie_header);
309 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314, quirk_fsl_pcie_header);
310 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315E, quirk_fsl_pcie_header);
311 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315, quirk_fsl_pcie_header);
312 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377E, quirk_fsl_pcie_header);
313 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377, quirk_fsl_pcie_header);
314 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378E, quirk_fsl_pcie_header);
315 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378, quirk_fsl_pcie_header);
317 struct mpc83xx_pcie_priv {
318 void __iomem *cfg_type0;
319 void __iomem *cfg_type1;
324 * With the convention of u-boot, the PCIE outbound window 0 serves
325 * as configuration transactions outbound.
327 #define PEX_OUTWIN0_BAR 0xCA4
328 #define PEX_OUTWIN0_TAL 0xCA8
329 #define PEX_OUTWIN0_TAH 0xCAC
331 static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
333 struct pci_controller *hose = bus->sysdata;
335 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
336 return PCIBIOS_DEVICE_NOT_FOUND;
338 * Workaround for the HW bug: for Type 0 configure transactions the
339 * PCI-E controller does not check the device number bits and just
340 * assumes that the device number bits are 0.
342 if (bus->number == hose->first_busno ||
343 bus->primary == hose->first_busno) {
345 return PCIBIOS_DEVICE_NOT_FOUND;
348 if (ppc_md.pci_exclude_device) {
349 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
350 return PCIBIOS_DEVICE_NOT_FOUND;
353 return PCIBIOS_SUCCESSFUL;
356 static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
357 unsigned int devfn, int offset)
359 struct pci_controller *hose = bus->sysdata;
360 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
361 u8 bus_no = bus->number - hose->first_busno;
362 u32 dev_base = bus_no << 24 | devfn << 16;
365 ret = mpc83xx_pcie_exclude_device(bus, devfn);
372 if (bus->number == hose->first_busno)
373 return pcie->cfg_type0 + offset;
375 if (pcie->dev_base == dev_base)
378 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base);
380 pcie->dev_base = dev_base;
382 return pcie->cfg_type1 + offset;
385 static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
386 int offset, int len, u32 *val)
388 void __iomem *cfg_addr;
390 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
392 return PCIBIOS_DEVICE_NOT_FOUND;
396 *val = in_8(cfg_addr);
399 *val = in_le16(cfg_addr);
402 *val = in_le32(cfg_addr);
406 return PCIBIOS_SUCCESSFUL;
409 static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
410 int offset, int len, u32 val)
412 void __iomem *cfg_addr;
414 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
416 return PCIBIOS_DEVICE_NOT_FOUND;
420 out_8(cfg_addr, val);
423 out_le16(cfg_addr, val);
426 out_le32(cfg_addr, val);
430 return PCIBIOS_SUCCESSFUL;
433 static struct pci_ops mpc83xx_pcie_ops = {
434 .read = mpc83xx_pcie_read_config,
435 .write = mpc83xx_pcie_write_config,
438 static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
439 struct resource *reg)
441 struct mpc83xx_pcie_priv *pcie;
445 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL);
449 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg));
450 if (!pcie->cfg_type0)
453 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR);
455 /* PCI-E isn't configured. */
460 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000);
461 if (!pcie->cfg_type1)
464 WARN_ON(hose->dn->data);
465 hose->dn->data = pcie;
466 hose->ops = &mpc83xx_pcie_ops;
468 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
469 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
471 if (fsl_pcie_check_link(hose))
472 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
476 iounmap(pcie->cfg_type0);
483 int __init mpc83xx_add_bridge(struct device_node *dev)
487 struct pci_controller *hose;
488 struct resource rsrc_reg;
489 struct resource rsrc_cfg;
490 const int *bus_range;
493 if (!of_device_is_available(dev)) {
494 pr_warning("%s: disabled by the firmware.\n",
498 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
500 /* Fetch host bridge registers address */
501 if (of_address_to_resource(dev, 0, &rsrc_reg)) {
502 printk(KERN_WARNING "Can't get pci register base!\n");
506 memset(&rsrc_cfg, 0, sizeof(rsrc_cfg));
508 if (of_address_to_resource(dev, 1, &rsrc_cfg)) {
510 "No pci config register base in dev tree, "
513 * MPC83xx supports up to two host controllers
514 * one at 0x8500 has config space registers at 0x8300
515 * one at 0x8600 has config space registers at 0x8380
517 if ((rsrc_reg.start & 0xfffff) == 0x8500)
518 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;
519 else if ((rsrc_reg.start & 0xfffff) == 0x8600)
520 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;
523 * Controller at offset 0x8500 is primary
525 if ((rsrc_reg.start & 0xfffff) == 0x8500)
530 /* Get bus range if any */
531 bus_range = of_get_property(dev, "bus-range", &len);
532 if (bus_range == NULL || len < 2 * sizeof(int)) {
533 printk(KERN_WARNING "Can't get bus-range for %s, assume"
534 " bus 0\n", dev->full_name);
537 ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS);
538 hose = pcibios_alloc_controller(dev);
542 hose->first_busno = bus_range ? bus_range[0] : 0;
543 hose->last_busno = bus_range ? bus_range[1] : 0xff;
545 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) {
546 ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
550 setup_indirect_pci(hose, rsrc_cfg.start,
551 rsrc_cfg.start + 4, 0);
554 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
555 "Firmware bus number: %d->%d\n",
556 (unsigned long long)rsrc_reg.start, hose->first_busno,
559 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
560 hose, hose->cfg_addr, hose->cfg_data);
562 /* Interpret the "ranges" property */
563 /* This also maps the I/O region and sets isa_io/mem_base */
564 pci_process_bridge_OF_ranges(hose, dev, primary);
568 pcibios_free_controller(hose);
571 #endif /* CONFIG_PPC_83xx */