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   1 /*
   2  * General Purpose functions for the global management of the
   3  * 8260 Communication Processor Module.
   4  * Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
   5  * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
   6  *      2.3.99 Updates
   7  *
   8  * 2006 (c) MontaVista Software, Inc.
   9  * Vitaly Bordug <vbordug@ru.mvista.com>
  10  *      Merged to arch/powerpc from arch/ppc/syslib/cpm2_common.c
  11  *
  12  * This file is licensed under the terms of the GNU General Public License
  13  * version 2. This program is licensed "as is" without any warranty of any
  14  * kind, whether express or implied.
  15  */
  16
  17 /*
  18  *
  19  * In addition to the individual control of the communication
  20  * channels, there are a few functions that globally affect the
  21  * communication processor.
  22  *
  23  * Buffer descriptors must be allocated from the dual ported memory
  24  * space.  The allocator for that is here.  When the communication
  25  * process is reset, we reclaim the memory available.  There is
  26  * currently no deallocator for this memory.
  27  */
  28 #include <linux/errno.h>
  29 #include <linux/sched.h>
  30 #include <linux/kernel.h>
  31 #include <linux/param.h>
  32 #include <linux/string.h>
  33 #include <linux/mm.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/module.h>
  36 #include <linux/of.h>
  37
  38 #include <asm/io.h>
  39 #include <asm/irq.h>
  40 #include <asm/mpc8260.h>
  41 #include <asm/page.h>
  42 #include <asm/pgtable.h>
  43 #include <asm/cpm2.h>
  44 #include <asm/rheap.h>
  45 #include <asm/fs_pd.h>
  46
  47 #include <sysdev/fsl_soc.h>
  48
  49 #ifndef CONFIG_PPC_CPM_NEW_BINDING
  50 static void cpm2_dpinit(void);
  51 #endif
  52
  53 cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor space */
  54
  55 /* We allocate this here because it is used almost exclusively for
  56  * the communication processor devices.
  57  */
  58 cpm2_map_t __iomem *cpm2_immr;
  59
  60 #define CPM_MAP_SIZE    (0x40000)       /* 256k - the PQ3 reserve this amount
  61                                            of space for CPM as it is larger
  62                                            than on PQ2 */
  63
  64 void __init cpm2_reset(void)
  65 {
  66 #ifdef CONFIG_PPC_85xx
  67         cpm2_immr = ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE);
  68 #else
  69         cpm2_immr = ioremap(get_immrbase(), CPM_MAP_SIZE);
  70 #endif
  71
  72         /* Reclaim the DP memory for our use.
  73          */
  74 #ifdef CONFIG_PPC_CPM_NEW_BINDING
  75         cpm_muram_init();
  76 #else
  77         cpm2_dpinit();
  78 #endif
  79
  80         /* Tell everyone where the comm processor resides.
  81          */
  82         cpmp = &cpm2_immr->im_cpm;
  83
  84 #ifndef CONFIG_PPC_EARLY_DEBUG_CPM
  85         /* Reset the CPM.
  86          */
  87         cpm_command(CPM_CR_RST, 0);
  88 #endif
  89 }
  90
  91 static DEFINE_SPINLOCK(cmd_lock);
  92
  93 #define MAX_CR_CMD_LOOPS        10000
  94
  95 int cpm_command(u32 command, u8 opcode)
  96 {
  97         int i, ret;
  98         unsigned long flags;
  99
 100         spin_lock_irqsave(&cmd_lock, flags);
 101
 102         ret = 0;
 103         out_be32(&cpmp->cp_cpcr, command | opcode | CPM_CR_FLG);
 104         for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
 105                 if ((in_be32(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
 106                         goto out;
 107
 108         printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__);
 109         ret = -EIO;
 110 out:
 111         spin_unlock_irqrestore(&cmd_lock, flags);
 112         return ret;
 113 }
 114 EXPORT_SYMBOL(cpm_command);
 115
 116 /* Set a baud rate generator.  This needs lots of work.  There are
 117  * eight BRGs, which can be connected to the CPM channels or output
 118  * as clocks.  The BRGs are in two different block of internal
 119  * memory mapped space.
 120  * The baud rate clock is the system clock divided by something.
 121  * It was set up long ago during the initial boot phase and is
 122  * is given to us.
 123  * Baud rate clocks are zero-based in the driver code (as that maps
 124  * to port numbers).  Documentation uses 1-based numbering.
 125  */
 126 #define BRG_INT_CLK     (get_brgfreq())
 127 #define BRG_UART_CLK    (BRG_INT_CLK/16)
 128
 129 /* This function is used by UARTS, or anything else that uses a 16x
 130  * oversampled clock.
 131  */
 132 void
 133 cpm_setbrg(uint brg, uint rate)
 134 {
 135         u32 __iomem *bp;
 136
 137         /* This is good enough to get SMCs running.....
 138         */
 139         if (brg < 4) {
 140                 bp = cpm2_map_size(im_brgc1, 16);
 141         } else {
 142                 bp = cpm2_map_size(im_brgc5, 16);
 143                 brg -= 4;
 144         }
 145         bp += brg;
 146         out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN);
 147
 148         cpm2_unmap(bp);
 149 }
 150
 151 /* This function is used to set high speed synchronous baud rate
 152  * clocks.
 153  */
 154 void
 155 cpm2_fastbrg(uint brg, uint rate, int div16)
 156 {
 157         u32 __iomem *bp;
 158         u32 val;
 159
 160         if (brg < 4) {
 161                 bp = cpm2_map_size(im_brgc1, 16);
 162         } else {
 163                 bp = cpm2_map_size(im_brgc5, 16);
 164                 brg -= 4;
 165         }
 166         bp += brg;
 167         val = ((BRG_INT_CLK / rate) << 1) | CPM_BRG_EN;
 168         if (div16)
 169                 val |= CPM_BRG_DIV16;
 170
 171         out_be32(bp, val);
 172         cpm2_unmap(bp);
 173 }
 174
 175 int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode)
 176 {
 177         int ret = 0;
 178         int shift;
 179         int i, bits = 0;
 180         cpmux_t __iomem *im_cpmux;
 181         u32 __iomem *reg;
 182         u32 mask = 7;
 183
 184         u8 clk_map[][3] = {
 185                 {CPM_CLK_FCC1, CPM_BRG5, 0},
 186                 {CPM_CLK_FCC1, CPM_BRG6, 1},
 187                 {CPM_CLK_FCC1, CPM_BRG7, 2},
 188                 {CPM_CLK_FCC1, CPM_BRG8, 3},
 189                 {CPM_CLK_FCC1, CPM_CLK9, 4},
 190                 {CPM_CLK_FCC1, CPM_CLK10, 5},
 191                 {CPM_CLK_FCC1, CPM_CLK11, 6},
 192                 {CPM_CLK_FCC1, CPM_CLK12, 7},
 193                 {CPM_CLK_FCC2, CPM_BRG5, 0},
 194                 {CPM_CLK_FCC2, CPM_BRG6, 1},
 195                 {CPM_CLK_FCC2, CPM_BRG7, 2},
 196                 {CPM_CLK_FCC2, CPM_BRG8, 3},
 197                 {CPM_CLK_FCC2, CPM_CLK13, 4},
 198                 {CPM_CLK_FCC2, CPM_CLK14, 5},
 199                 {CPM_CLK_FCC2, CPM_CLK15, 6},
 200                 {CPM_CLK_FCC2, CPM_CLK16, 7},
 201                 {CPM_CLK_FCC3, CPM_BRG5, 0},
 202                 {CPM_CLK_FCC3, CPM_BRG6, 1},
 203                 {CPM_CLK_FCC3, CPM_BRG7, 2},
 204                 {CPM_CLK_FCC3, CPM_BRG8, 3},
 205                 {CPM_CLK_FCC3, CPM_CLK13, 4},
 206                 {CPM_CLK_FCC3, CPM_CLK14, 5},
 207                 {CPM_CLK_FCC3, CPM_CLK15, 6},
 208                 {CPM_CLK_FCC3, CPM_CLK16, 7},
 209                 {CPM_CLK_SCC1, CPM_BRG1, 0},
 210                 {CPM_CLK_SCC1, CPM_BRG2, 1},
 211                 {CPM_CLK_SCC1, CPM_BRG3, 2},
 212                 {CPM_CLK_SCC1, CPM_BRG4, 3},
 213                 {CPM_CLK_SCC1, CPM_CLK11, 4},
 214                 {CPM_CLK_SCC1, CPM_CLK12, 5},
 215                 {CPM_CLK_SCC1, CPM_CLK3, 6},
 216                 {CPM_CLK_SCC1, CPM_CLK4, 7},
 217                 {CPM_CLK_SCC2, CPM_BRG1, 0},
 218                 {CPM_CLK_SCC2, CPM_BRG2, 1},
 219                 {CPM_CLK_SCC2, CPM_BRG3, 2},
 220                 {CPM_CLK_SCC2, CPM_BRG4, 3},
 221                 {CPM_CLK_SCC2, CPM_CLK11, 4},
 222                 {CPM_CLK_SCC2, CPM_CLK12, 5},
 223                 {CPM_CLK_SCC2, CPM_CLK3, 6},
 224                 {CPM_CLK_SCC2, CPM_CLK4, 7},
 225                 {CPM_CLK_SCC3, CPM_BRG1, 0},
 226                 {CPM_CLK_SCC3, CPM_BRG2, 1},
 227                 {CPM_CLK_SCC3, CPM_BRG3, 2},
 228                 {CPM_CLK_SCC3, CPM_BRG4, 3},
 229                 {CPM_CLK_SCC3, CPM_CLK5, 4},
 230                 {CPM_CLK_SCC3, CPM_CLK6, 5},
 231                 {CPM_CLK_SCC3, CPM_CLK7, 6},
 232                 {CPM_CLK_SCC3, CPM_CLK8, 7},
 233                 {CPM_CLK_SCC4, CPM_BRG1, 0},
 234                 {CPM_CLK_SCC4, CPM_BRG2, 1},
 235                 {CPM_CLK_SCC4, CPM_BRG3, 2},
 236                 {CPM_CLK_SCC4, CPM_BRG4, 3},
 237                 {CPM_CLK_SCC4, CPM_CLK5, 4},
 238                 {CPM_CLK_SCC4, CPM_CLK6, 5},
 239                 {CPM_CLK_SCC4, CPM_CLK7, 6},
 240                 {CPM_CLK_SCC4, CPM_CLK8, 7},
 241         };
 242
 243         im_cpmux = cpm2_map(im_cpmux);
 244
 245         switch (target) {
 246         case CPM_CLK_SCC1:
 247                 reg = &im_cpmux->cmx_scr;
 248                 shift = 24;
 249                 break;
 250         case CPM_CLK_SCC2:
 251                 reg = &im_cpmux->cmx_scr;
 252                 shift = 16;
 253                 break;
 254         case CPM_CLK_SCC3:
 255                 reg = &im_cpmux->cmx_scr;
 256                 shift = 8;
 257                 break;
 258         case CPM_CLK_SCC4:
 259                 reg = &im_cpmux->cmx_scr;
 260                 shift = 0;
 261                 break;
 262         case CPM_CLK_FCC1:
 263                 reg = &im_cpmux->cmx_fcr;
 264                 shift = 24;
 265                 break;
 266         case CPM_CLK_FCC2:
 267                 reg = &im_cpmux->cmx_fcr;
 268                 shift = 16;
 269                 break;
 270         case CPM_CLK_FCC3:
 271                 reg = &im_cpmux->cmx_fcr;
 272                 shift = 8;
 273                 break;
 274         default:
 275                 printk(KERN_ERR "cpm2_clock_setup: invalid clock target\n");
 276                 return -EINVAL;
 277         }
 278
 279         if (mode == CPM_CLK_RX)
 280                 shift += 3;
 281
 282         for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
 283                 if (clk_map[i][0] == target && clk_map[i][1] == clock) {
 284                         bits = clk_map[i][2];
 285                         break;
 286                 }
 287         }
 288         if (i == ARRAY_SIZE(clk_map))
 289             ret = -EINVAL;
 290
 291         bits <<= shift;
 292         mask <<= shift;
 293
 294         out_be32(reg, (in_be32(reg) & ~mask) | bits);
 295
 296         cpm2_unmap(im_cpmux);
 297         return ret;
 298 }
 299
 300 int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock)
 301 {
 302         int ret = 0;
 303         int shift;
 304         int i, bits = 0;
 305         cpmux_t __iomem *im_cpmux;
 306         u8 __iomem *reg;
 307         u8 mask = 3;
 308
 309         u8 clk_map[][3] = {
 310                 {CPM_CLK_SMC1, CPM_BRG1, 0},
 311                 {CPM_CLK_SMC1, CPM_BRG7, 1},
 312                 {CPM_CLK_SMC1, CPM_CLK7, 2},
 313                 {CPM_CLK_SMC1, CPM_CLK9, 3},
 314                 {CPM_CLK_SMC2, CPM_BRG2, 0},
 315                 {CPM_CLK_SMC2, CPM_BRG8, 1},
 316                 {CPM_CLK_SMC2, CPM_CLK4, 2},
 317                 {CPM_CLK_SMC2, CPM_CLK15, 3},
 318         };
 319
 320         im_cpmux = cpm2_map(im_cpmux);
 321
 322         switch (target) {
 323         case CPM_CLK_SMC1:
 324                 reg = &im_cpmux->cmx_smr;
 325                 mask = 3;
 326                 shift = 4;
 327                 break;
 328         case CPM_CLK_SMC2:
 329                 reg = &im_cpmux->cmx_smr;
 330                 mask = 3;
 331                 shift = 0;
 332                 break;
 333         default:
 334                 printk(KERN_ERR "cpm2_smc_clock_setup: invalid clock target\n");
 335                 return -EINVAL;
 336         }
 337
 338         for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
 339                 if (clk_map[i][0] == target && clk_map[i][1] == clock) {
 340                         bits = clk_map[i][2];
 341                         break;
 342                 }
 343         }
 344         if (i == ARRAY_SIZE(clk_map))
 345             ret = -EINVAL;
 346
 347         bits <<= shift;
 348         mask <<= shift;
 349
 350         out_8(reg, (in_8(reg) & ~mask) | bits);
 351
 352         cpm2_unmap(im_cpmux);
 353         return ret;
 354 }
 355
 356 #ifndef CONFIG_PPC_CPM_NEW_BINDING
 357 /*
 358  * dpalloc / dpfree bits.
 359  */
 360 static spinlock_t cpm_dpmem_lock;
 361 /* 16 blocks should be enough to satisfy all requests
 362  * until the memory subsystem goes up... */
 363 static rh_block_t cpm_boot_dpmem_rh_block[16];
 364 static rh_info_t cpm_dpmem_info;
 365 static u8 __iomem *im_dprambase;
 366
 367 static void cpm2_dpinit(void)
 368 {
 369         spin_lock_init(&cpm_dpmem_lock);
 370
 371         /* initialize the info header */
 372         rh_init(&cpm_dpmem_info, 1,
 373                         sizeof(cpm_boot_dpmem_rh_block) /
 374                         sizeof(cpm_boot_dpmem_rh_block[0]),
 375                         cpm_boot_dpmem_rh_block);
 376
 377         im_dprambase = cpm2_immr;
 378
 379         /* Attach the usable dpmem area */
 380         /* XXX: This is actually crap. CPM_DATAONLY_BASE and
 381          * CPM_DATAONLY_SIZE is only a subset of the available dpram. It
 382          * varies with the processor and the microcode patches activated.
 383          * But the following should be at least safe.
 384          */
 385         rh_attach_region(&cpm_dpmem_info, CPM_DATAONLY_BASE, CPM_DATAONLY_SIZE);
 386 }
 387
 388 /* This function returns an index into the DPRAM area.
 389  */
 390 unsigned long cpm_dpalloc(uint size, uint align)
 391 {
 392         unsigned long start;
 393         unsigned long flags;
 394
 395         spin_lock_irqsave(&cpm_dpmem_lock, flags);
 396         cpm_dpmem_info.alignment = align;
 397         start = rh_alloc(&cpm_dpmem_info, size, "commproc");
 398         spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
 399
 400         return (uint)start;
 401 }
 402 EXPORT_SYMBOL(cpm_dpalloc);
 403
 404 int cpm_dpfree(unsigned long offset)
 405 {
 406         int ret;
 407         unsigned long flags;
 408
 409         spin_lock_irqsave(&cpm_dpmem_lock, flags);
 410         ret = rh_free(&cpm_dpmem_info, offset);
 411         spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
 412
 413         return ret;
 414 }
 415 EXPORT_SYMBOL(cpm_dpfree);
 416
 417 /* not sure if this is ever needed */
 418 unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align)
 419 {
 420         unsigned long start;
 421         unsigned long flags;
 422
 423         spin_lock_irqsave(&cpm_dpmem_lock, flags);
 424         cpm_dpmem_info.alignment = align;
 425         start = rh_alloc_fixed(&cpm_dpmem_info, offset, size, "commproc");
 426         spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
 427
 428         return start;
 429 }
 430 EXPORT_SYMBOL(cpm_dpalloc_fixed);
 431
 432 void cpm_dpdump(void)
 433 {
 434         rh_dump(&cpm_dpmem_info);
 435 }
 436 EXPORT_SYMBOL(cpm_dpdump);
 437
 438 void *cpm_dpram_addr(unsigned long offset)
 439 {
 440         return (void *)(im_dprambase + offset);
 441 }
 442 EXPORT_SYMBOL(cpm_dpram_addr);
 443 #endif /* !CONFIG_PPC_CPM_NEW_BINDING */
 444
 445 struct cpm2_ioports {
 446         u32 dir, par, sor, odr, dat;
 447         u32 res[3];
 448 };
 449
 450 void cpm2_set_pin(int port, int pin, int flags)
 451 {
 452         struct cpm2_ioports __iomem *iop =
 453                 (struct cpm2_ioports __iomem *)&cpm2_immr->im_ioport;
 454
 455         pin = 1 << (31 - pin);
 456
 457         if (flags & CPM_PIN_OUTPUT)
 458                 setbits32(&iop[port].dir, pin);
 459         else
 460                 clrbits32(&iop[port].dir, pin);
 461
 462         if (!(flags & CPM_PIN_GPIO))
 463                 setbits32(&iop[port].par, pin);
 464         else
 465                 clrbits32(&iop[port].par, pin);
 466
 467         if (flags & CPM_PIN_SECONDARY)
 468                 setbits32(&iop[port].sor, pin);
 469         else
 470                 clrbits32(&iop[port].sor, pin);
 471
 472         if (flags & CPM_PIN_OPENDRAIN)
 473                 setbits32(&iop[port].odr, pin);
 474         else
 475                 clrbits32(&iop[port].odr, pin);
 476 }