2 * General Purpose functions for the global management of the
3 * 8260 Communication Processor Module.
4 * Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
5 * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
8 * 2006 (c) MontaVista Software, Inc.
9 * Vitaly Bordug <vbordug@ru.mvista.com>
10 * Merged to arch/powerpc from arch/ppc/syslib/cpm2_common.c
12 * This file is licensed under the terms of the GNU General Public License
13 * version 2. This program is licensed "as is" without any warranty of any
14 * kind, whether express or implied.
19 * In addition to the individual control of the communication
20 * channels, there are a few functions that globally affect the
21 * communication processor.
23 * Buffer descriptors must be allocated from the dual ported memory
24 * space. The allocator for that is here. When the communication
25 * process is reset, we reclaim the memory available. There is
26 * currently no deallocator for this memory.
28 #include <linux/errno.h>
29 #include <linux/sched.h>
30 #include <linux/kernel.h>
31 #include <linux/param.h>
32 #include <linux/string.h>
34 #include <linux/interrupt.h>
35 #include <linux/module.h>
40 #include <asm/mpc8260.h>
42 #include <asm/pgtable.h>
44 #include <asm/rheap.h>
45 #include <asm/fs_pd.h>
47 #include <sysdev/fsl_soc.h>
49 cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor space */
51 /* We allocate this here because it is used almost exclusively for
52 * the communication processor devices.
54 cpm2_map_t __iomem *cpm2_immr;
56 #define CPM_MAP_SIZE (0x40000) /* 256k - the PQ3 reserve this amount
57 of space for CPM as it is larger
60 void __init cpm2_reset(void)
62 #ifdef CONFIG_PPC_85xx
63 cpm2_immr = ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE);
65 cpm2_immr = ioremap(get_immrbase(), CPM_MAP_SIZE);
68 /* Reclaim the DP memory for our use.
72 /* Tell everyone where the comm processor resides.
74 cpmp = &cpm2_immr->im_cpm;
76 #ifndef CONFIG_PPC_EARLY_DEBUG_CPM
79 cpm_command(CPM_CR_RST, 0);
83 static DEFINE_SPINLOCK(cmd_lock);
85 #define MAX_CR_CMD_LOOPS 10000
87 int cpm_command(u32 command, u8 opcode)
92 spin_lock_irqsave(&cmd_lock, flags);
95 out_be32(&cpmp->cp_cpcr, command | opcode | CPM_CR_FLG);
96 for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
97 if ((in_be32(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
100 printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__);
103 spin_unlock_irqrestore(&cmd_lock, flags);
106 EXPORT_SYMBOL(cpm_command);
108 /* Set a baud rate generator. This needs lots of work. There are
109 * eight BRGs, which can be connected to the CPM channels or output
110 * as clocks. The BRGs are in two different block of internal
111 * memory mapped space.
112 * The baud rate clock is the system clock divided by something.
113 * It was set up long ago during the initial boot phase and is
115 * Baud rate clocks are zero-based in the driver code (as that maps
116 * to port numbers). Documentation uses 1-based numbering.
118 void __cpm2_setbrg(uint brg, uint rate, uint clk, int div16, int src)
123 /* This is good enough to get SMCs running.....
126 bp = cpm2_map_size(im_brgc1, 16);
128 bp = cpm2_map_size(im_brgc5, 16);
132 /* Round the clock divider to the nearest integer. */
133 val = (((clk * 2 / rate) - 1) & ~1) | CPM_BRG_EN | src;
135 val |= CPM_BRG_DIV16;
140 EXPORT_SYMBOL(__cpm2_setbrg);
142 int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode)
147 cpmux_t __iomem *im_cpmux;
152 {CPM_CLK_FCC1, CPM_BRG5, 0},
153 {CPM_CLK_FCC1, CPM_BRG6, 1},
154 {CPM_CLK_FCC1, CPM_BRG7, 2},
155 {CPM_CLK_FCC1, CPM_BRG8, 3},
156 {CPM_CLK_FCC1, CPM_CLK9, 4},
157 {CPM_CLK_FCC1, CPM_CLK10, 5},
158 {CPM_CLK_FCC1, CPM_CLK11, 6},
159 {CPM_CLK_FCC1, CPM_CLK12, 7},
160 {CPM_CLK_FCC2, CPM_BRG5, 0},
161 {CPM_CLK_FCC2, CPM_BRG6, 1},
162 {CPM_CLK_FCC2, CPM_BRG7, 2},
163 {CPM_CLK_FCC2, CPM_BRG8, 3},
164 {CPM_CLK_FCC2, CPM_CLK13, 4},
165 {CPM_CLK_FCC2, CPM_CLK14, 5},
166 {CPM_CLK_FCC2, CPM_CLK15, 6},
167 {CPM_CLK_FCC2, CPM_CLK16, 7},
168 {CPM_CLK_FCC3, CPM_BRG5, 0},
169 {CPM_CLK_FCC3, CPM_BRG6, 1},
170 {CPM_CLK_FCC3, CPM_BRG7, 2},
171 {CPM_CLK_FCC3, CPM_BRG8, 3},
172 {CPM_CLK_FCC3, CPM_CLK13, 4},
173 {CPM_CLK_FCC3, CPM_CLK14, 5},
174 {CPM_CLK_FCC3, CPM_CLK15, 6},
175 {CPM_CLK_FCC3, CPM_CLK16, 7},
176 {CPM_CLK_SCC1, CPM_BRG1, 0},
177 {CPM_CLK_SCC1, CPM_BRG2, 1},
178 {CPM_CLK_SCC1, CPM_BRG3, 2},
179 {CPM_CLK_SCC1, CPM_BRG4, 3},
180 {CPM_CLK_SCC1, CPM_CLK11, 4},
181 {CPM_CLK_SCC1, CPM_CLK12, 5},
182 {CPM_CLK_SCC1, CPM_CLK3, 6},
183 {CPM_CLK_SCC1, CPM_CLK4, 7},
184 {CPM_CLK_SCC2, CPM_BRG1, 0},
185 {CPM_CLK_SCC2, CPM_BRG2, 1},
186 {CPM_CLK_SCC2, CPM_BRG3, 2},
187 {CPM_CLK_SCC2, CPM_BRG4, 3},
188 {CPM_CLK_SCC2, CPM_CLK11, 4},
189 {CPM_CLK_SCC2, CPM_CLK12, 5},
190 {CPM_CLK_SCC2, CPM_CLK3, 6},
191 {CPM_CLK_SCC2, CPM_CLK4, 7},
192 {CPM_CLK_SCC3, CPM_BRG1, 0},
193 {CPM_CLK_SCC3, CPM_BRG2, 1},
194 {CPM_CLK_SCC3, CPM_BRG3, 2},
195 {CPM_CLK_SCC3, CPM_BRG4, 3},
196 {CPM_CLK_SCC3, CPM_CLK5, 4},
197 {CPM_CLK_SCC3, CPM_CLK6, 5},
198 {CPM_CLK_SCC3, CPM_CLK7, 6},
199 {CPM_CLK_SCC3, CPM_CLK8, 7},
200 {CPM_CLK_SCC4, CPM_BRG1, 0},
201 {CPM_CLK_SCC4, CPM_BRG2, 1},
202 {CPM_CLK_SCC4, CPM_BRG3, 2},
203 {CPM_CLK_SCC4, CPM_BRG4, 3},
204 {CPM_CLK_SCC4, CPM_CLK5, 4},
205 {CPM_CLK_SCC4, CPM_CLK6, 5},
206 {CPM_CLK_SCC4, CPM_CLK7, 6},
207 {CPM_CLK_SCC4, CPM_CLK8, 7},
210 im_cpmux = cpm2_map(im_cpmux);
214 reg = &im_cpmux->cmx_scr;
218 reg = &im_cpmux->cmx_scr;
222 reg = &im_cpmux->cmx_scr;
226 reg = &im_cpmux->cmx_scr;
230 reg = &im_cpmux->cmx_fcr;
234 reg = &im_cpmux->cmx_fcr;
238 reg = &im_cpmux->cmx_fcr;
242 printk(KERN_ERR "cpm2_clock_setup: invalid clock target\n");
246 if (mode == CPM_CLK_RX)
249 for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
250 if (clk_map[i][0] == target && clk_map[i][1] == clock) {
251 bits = clk_map[i][2];
255 if (i == ARRAY_SIZE(clk_map))
261 out_be32(reg, (in_be32(reg) & ~mask) | bits);
263 cpm2_unmap(im_cpmux);
267 int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock)
272 cpmux_t __iomem *im_cpmux;
277 {CPM_CLK_SMC1, CPM_BRG1, 0},
278 {CPM_CLK_SMC1, CPM_BRG7, 1},
279 {CPM_CLK_SMC1, CPM_CLK7, 2},
280 {CPM_CLK_SMC1, CPM_CLK9, 3},
281 {CPM_CLK_SMC2, CPM_BRG2, 0},
282 {CPM_CLK_SMC2, CPM_BRG8, 1},
283 {CPM_CLK_SMC2, CPM_CLK4, 2},
284 {CPM_CLK_SMC2, CPM_CLK15, 3},
287 im_cpmux = cpm2_map(im_cpmux);
291 reg = &im_cpmux->cmx_smr;
296 reg = &im_cpmux->cmx_smr;
301 printk(KERN_ERR "cpm2_smc_clock_setup: invalid clock target\n");
305 for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
306 if (clk_map[i][0] == target && clk_map[i][1] == clock) {
307 bits = clk_map[i][2];
311 if (i == ARRAY_SIZE(clk_map))
317 out_8(reg, (in_8(reg) & ~mask) | bits);
319 cpm2_unmap(im_cpmux);
323 struct cpm2_ioports {
324 u32 dir, par, sor, odr, dat;
328 void cpm2_set_pin(int port, int pin, int flags)
330 struct cpm2_ioports __iomem *iop =
331 (struct cpm2_ioports __iomem *)&cpm2_immr->im_ioport;
333 pin = 1 << (31 - pin);
335 if (flags & CPM_PIN_OUTPUT)
336 setbits32(&iop[port].dir, pin);
338 clrbits32(&iop[port].dir, pin);
340 if (!(flags & CPM_PIN_GPIO))
341 setbits32(&iop[port].par, pin);
343 clrbits32(&iop[port].par, pin);
345 if (flags & CPM_PIN_SECONDARY)
346 setbits32(&iop[port].sor, pin);
348 clrbits32(&iop[port].sor, pin);
350 if (flags & CPM_PIN_OPENDRAIN)
351 setbits32(&iop[port].odr, pin);
353 clrbits32(&iop[port].odr, pin);
356 static int cpm_init_par_io(void)
358 struct device_node *np;
360 for_each_compatible_node(np, NULL, "fsl,cpm2-pario-bank")
361 cpm2_gpiochip_add32(np);
364 arch_initcall(cpm_init_par_io);