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   1 /*
   2  * Cell Internal Interrupt Controller
   3  *
   4  * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
   5  *
   6  * Author: Arnd Bergmann <arndb@de.ibm.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2, or (at your option)
  11  * any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/config.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/irq.h>
  26 #include <linux/module.h>
  27 #include <linux/percpu.h>
  28 #include <linux/types.h>
  29
  30 #include <asm/io.h>
  31 #include <asm/pgtable.h>
  32 #include <asm/prom.h>
  33 #include <asm/ptrace.h>
  34
  35 #include "interrupt.h"
  36 #include "cbe_regs.h"
  37
  38 struct iic {
  39         struct cbe_iic_thread_regs __iomem *regs;
  40         u8 target_id;
  41 };
  42
  43 static DEFINE_PER_CPU(struct iic, iic);
  44
  45 void iic_local_enable(void)
  46 {
  47         struct iic *iic = &__get_cpu_var(iic);
  48         u64 tmp;
  49
  50         /*
  51          * There seems to be a bug that is present in DD2.x CPUs
  52          * and still only partially fixed in DD3.1.
  53          * This bug causes a value written to the priority register
  54          * not to make it there, resulting in a system hang unless we
  55          * write it again.
  56          * Masking with 0xf0 is done because the Cell BE does not
  57          * implement the lower four bits of the interrupt priority,
  58          * they always read back as zeroes, although future CPUs
  59          * might implement different bits.
  60          */
  61         do {
  62                 out_be64(&iic->regs->prio, 0xff);
  63                 tmp = in_be64(&iic->regs->prio);
  64         } while ((tmp & 0xf0) != 0xf0);
  65 }
  66
  67 void iic_local_disable(void)
  68 {
  69         out_be64(&__get_cpu_var(iic).regs->prio, 0x0);
  70 }
  71
  72 static unsigned int iic_startup(unsigned int irq)
  73 {
  74         return 0;
  75 }
  76
  77 static void iic_enable(unsigned int irq)
  78 {
  79         iic_local_enable();
  80 }
  81
  82 static void iic_disable(unsigned int irq)
  83 {
  84 }
  85
  86 static void iic_end(unsigned int irq)
  87 {
  88         iic_local_enable();
  89 }
  90
  91 static struct hw_interrupt_type iic_pic = {
  92         .typename = " CELL-IIC ",
  93         .startup = iic_startup,
  94         .enable = iic_enable,
  95         .disable = iic_disable,
  96         .end = iic_end,
  97 };
  98
  99 static int iic_external_get_irq(struct cbe_iic_pending_bits pending)
 100 {
 101         int irq;
 102         unsigned char node, unit;
 103
 104         node = pending.source >> 4;
 105         unit = pending.source & 0xf;
 106         irq = -1;
 107
 108         /*
 109          * This mapping is specific to the Cell Broadband
 110          * Engine. We might need to get the numbers
 111          * from the device tree to support future CPUs.
 112          */
 113         switch (unit) {
 114         case 0x00:
 115         case 0x0b:
 116                 /*
 117                  * One of these units can be connected
 118                  * to an external interrupt controller.
 119                  */
 120                 if (pending.prio > 0x3f ||
 121                     pending.class != 2)
 122                         break;
 123                 irq = IIC_EXT_OFFSET
 124                         + spider_get_irq(node)
 125                         + node * IIC_NODE_STRIDE;
 126                 break;
 127         case 0x01 ... 0x04:
 128         case 0x07 ... 0x0a:
 129                 /*
 130                  * These units are connected to the SPEs
 131                  */
 132                 if (pending.class > 2)
 133                         break;
 134                 irq = IIC_SPE_OFFSET
 135                         + pending.class * IIC_CLASS_STRIDE
 136                         + node * IIC_NODE_STRIDE
 137                         + unit;
 138                 break;
 139         }
 140         if (irq == -1)
 141                 printk(KERN_WARNING "Unexpected interrupt class %02x, "
 142                         "source %02x, prio %02x, cpu %02x\n", pending.class,
 143                         pending.source, pending.prio, smp_processor_id());
 144         return irq;
 145 }
 146
 147 /* Get an IRQ number from the pending state register of the IIC */
 148 int iic_get_irq(struct pt_regs *regs)
 149 {
 150         struct iic *iic;
 151         int irq;
 152         struct cbe_iic_pending_bits pending;
 153
 154         iic = &__get_cpu_var(iic);
 155         *(unsigned long *) &pending =
 156                 in_be64((unsigned long __iomem *) &iic->regs->pending_destr);
 157
 158         irq = -1;
 159         if (pending.flags & CBE_IIC_IRQ_VALID) {
 160                 if (pending.flags & CBE_IIC_IRQ_IPI) {
 161                         irq = IIC_IPI_OFFSET + (pending.prio >> 4);
 162 /*
 163                         if (irq > 0x80)
 164                                 printk(KERN_WARNING "Unexpected IPI prio %02x"
 165                                         "on CPU %02x\n", pending.prio,
 166                                                         smp_processor_id());
 167 */
 168                 } else {
 169                         irq = iic_external_get_irq(pending);
 170                 }
 171         }
 172         return irq;
 173 }
 174
 175 /* hardcoded part to be compatible with older firmware */
 176
 177 static int setup_iic_hardcoded(void)
 178 {
 179         struct device_node *np;
 180         int nodeid, cpu;
 181         unsigned long regs;
 182         struct iic *iic;
 183
 184         for_each_cpu(cpu) {
 185                 iic = &per_cpu(iic, cpu);
 186                 nodeid = cpu/2;
 187
 188                 for (np = of_find_node_by_type(NULL, "cpu");
 189                      np;
 190                      np = of_find_node_by_type(np, "cpu")) {
 191                         if (nodeid == *(int *)get_property(np, "node-id", NULL))
 192                                 break;
 193                         }
 194
 195                 if (!np) {
 196                         printk(KERN_WARNING "IIC: CPU %d not found\n", cpu);
 197                         iic->regs = NULL;
 198                         iic->target_id = 0xff;
 199                         return -ENODEV;
 200                         }
 201
 202                 regs = *(long *)get_property(np, "iic", NULL);
 203
 204                 /* hack until we have decided on the devtree info */
 205                 regs += 0x400;
 206                 if (cpu & 1)
 207                         regs += 0x20;
 208
 209                 printk(KERN_INFO "IIC for CPU %d at %lx\n", cpu, regs);
 210                 iic->regs = ioremap(regs, sizeof(struct cbe_iic_thread_regs));
 211                 iic->target_id = (nodeid << 4) + ((cpu & 1) ? 0xf : 0xe);
 212         }
 213
 214         return 0;
 215 }
 216
 217 static int setup_iic(void)
 218 {
 219         struct device_node *dn;
 220         unsigned long *regs;
 221         char *compatible;
 222         unsigned *np, found = 0;
 223         struct iic *iic = NULL;
 224
 225         for (dn = NULL; (dn = of_find_node_by_name(dn, "interrupt-controller"));) {
 226                 compatible = (char *)get_property(dn, "compatible", NULL);
 227
 228                 if (!compatible) {
 229                         printk(KERN_WARNING "no compatible property found !\n");
 230                         continue;
 231                 }
 232
 233                 if (strstr(compatible, "IBM,CBEA-Internal-Interrupt-Controller"))
 234                         regs = (unsigned long *)get_property(dn,"reg", NULL);
 235                 else
 236                         continue;
 237
 238                 if (!regs)
 239                         printk(KERN_WARNING "IIC: no reg property\n");
 240
 241                 np = (unsigned int *)get_property(dn, "ibm,interrupt-server-ranges", NULL);
 242
 243                 if (!np) {
 244                         printk(KERN_WARNING "IIC: CPU association not found\n");
 245                         iic->regs = NULL;
 246                         iic->target_id = 0xff;
 247                         return -ENODEV;
 248                 }
 249
 250                 iic = &per_cpu(iic, np[0]);
 251                 iic->regs = ioremap(regs[0], sizeof(struct cbe_iic_thread_regs));
 252                 iic->target_id = ((np[0] & 2) << 3) + ((np[0] & 1) ? 0xf : 0xe);
 253                 printk("IIC for CPU %d at %lx mapped to %p\n", np[0], regs[0], iic->regs);
 254
 255                 iic = &per_cpu(iic, np[1]);
 256                 iic->regs = ioremap(regs[2], sizeof(struct cbe_iic_thread_regs));
 257                 iic->target_id = ((np[1] & 2) << 3) + ((np[1] & 1) ? 0xf : 0xe);
 258                 printk("IIC for CPU %d at %lx mapped to %p\n", np[1], regs[2], iic->regs);
 259
 260                 found++;
 261         }
 262
 263         if (found)
 264                 return 0;
 265         else
 266                 return -ENODEV;
 267 }
 268
 269 #ifdef CONFIG_SMP
 270
 271 /* Use the highest interrupt priorities for IPI */
 272 static inline int iic_ipi_to_irq(int ipi)
 273 {
 274         return IIC_IPI_OFFSET + IIC_NUM_IPIS - 1 - ipi;
 275 }
 276
 277 static inline int iic_irq_to_ipi(int irq)
 278 {
 279         return IIC_NUM_IPIS - 1 - (irq - IIC_IPI_OFFSET);
 280 }
 281
 282 void iic_setup_cpu(void)
 283 {
 284         out_be64(&__get_cpu_var(iic).regs->prio, 0xff);
 285 }
 286
 287 void iic_cause_IPI(int cpu, int mesg)
 288 {
 289         out_be64(&per_cpu(iic, cpu).regs->generate, (IIC_NUM_IPIS - 1 - mesg) << 4);
 290 }
 291
 292 u8 iic_get_target_id(int cpu)
 293 {
 294         return per_cpu(iic, cpu).target_id;
 295 }
 296 EXPORT_SYMBOL_GPL(iic_get_target_id);
 297
 298 static irqreturn_t iic_ipi_action(int irq, void *dev_id, struct pt_regs *regs)
 299 {
 300         smp_message_recv(iic_irq_to_ipi(irq), regs);
 301         return IRQ_HANDLED;
 302 }
 303
 304 static void iic_request_ipi(int ipi, const char *name)
 305 {
 306         int irq;
 307
 308         irq = iic_ipi_to_irq(ipi);
 309         /* IPIs are marked SA_INTERRUPT as they must run with irqs
 310          * disabled */
 311         get_irq_desc(irq)->handler = &iic_pic;
 312         get_irq_desc(irq)->status |= IRQ_PER_CPU;
 313         request_irq(irq, iic_ipi_action, SA_INTERRUPT, name, NULL);
 314 }
 315
 316 void iic_request_IPIs(void)
 317 {
 318         iic_request_ipi(PPC_MSG_CALL_FUNCTION, "IPI-call");
 319         iic_request_ipi(PPC_MSG_RESCHEDULE, "IPI-resched");
 320 #ifdef CONFIG_DEBUGGER
 321         iic_request_ipi(PPC_MSG_DEBUGGER_BREAK, "IPI-debug");
 322 #endif /* CONFIG_DEBUGGER */
 323 }
 324 #endif /* CONFIG_SMP */
 325
 326 static void iic_setup_spe_handlers(void)
 327 {
 328         int be, isrc;
 329
 330         /* Assume two threads per BE are present */
 331         for (be=0; be < num_present_cpus() / 2; be++) {
 332                 for (isrc = 0; isrc < IIC_CLASS_STRIDE * 3; isrc++) {
 333                         int irq = IIC_NODE_STRIDE * be + IIC_SPE_OFFSET + isrc;
 334                         get_irq_desc(irq)->handler = &iic_pic;
 335                 }
 336         }
 337 }
 338
 339 void iic_init_IRQ(void)
 340 {
 341         int cpu, irq_offset;
 342         struct iic *iic;
 343
 344         if (setup_iic() < 0)
 345                 setup_iic_hardcoded();
 346
 347         irq_offset = 0;
 348         for_each_possible_cpu(cpu) {
 349                 iic = &per_cpu(iic, cpu);
 350                 if (iic->regs)
 351                         out_be64(&iic->regs->prio, 0xff);
 352         }
 353         iic_setup_spe_handlers();
 354 }