SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/powerpc/platforms/85xx/mpc85xx_mds.c

   1 /*
   2  * Copyright (C) Freescale Semicondutor, Inc. 2006-2007. All rights reserved.
   3  *
   4  * Author: Andy Fleming <afleming@freescale.com>
   5  *
   6  * Based on 83xx/mpc8360e_pb.c by:
   7  *         Li Yang <LeoLi@freescale.com>
   8  *         Yin Olivia <Hong-hua.Yin@freescale.com>
   9  *
  10  * Description:
  11  * MPC85xx MDS board specific routines.
  12  *
  13  * This program is free software; you can redistribute  it and/or modify it
  14  * under  the terms of  the GNU General  Public License as published by the
  15  * Free Software Foundation;  either version 2 of the  License, or (at your
  16  * option) any later version.
  17  */
  18
  19 #include <linux/stddef.h>
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/reboot.h>
  24 #include <linux/pci.h>
  25 #include <linux/kdev_t.h>
  26 #include <linux/major.h>
  27 #include <linux/console.h>
  28 #include <linux/delay.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/initrd.h>
  31 #include <linux/module.h>
  32 #include <linux/fsl_devices.h>
  33
  34 #include <asm/of_device.h>
  35 #include <asm/of_platform.h>
  36 #include <asm/system.h>
  37 #include <asm/atomic.h>
  38 #include <asm/time.h>
  39 #include <asm/io.h>
  40 #include <asm/machdep.h>
  41 #include <asm/pci-bridge.h>
  42 #include <asm/mpc85xx.h>
  43 #include <asm/irq.h>
  44 #include <mm/mmu_decl.h>
  45 #include <asm/prom.h>
  46 #include <asm/udbg.h>
  47 #include <sysdev/fsl_soc.h>
  48 #include <sysdev/fsl_pci.h>
  49 #include <asm/qe.h>
  50 #include <asm/qe_ic.h>
  51 #include <asm/mpic.h>
  52
  53 #undef DEBUG
  54 #ifdef DEBUG
  55 #define DBG(fmt...) udbg_printf(fmt)
  56 #else
  57 #define DBG(fmt...)
  58 #endif
  59
  60 /* ************************************************************************
  61  *
  62  * Setup the architecture
  63  *
  64  */
  65 static void __init mpc85xx_mds_setup_arch(void)
  66 {
  67         struct device_node *np;
  68         static u8 *bcsr_regs = NULL;
  69
  70         if (ppc_md.progress)
  71                 ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
  72
  73         /* Map BCSR area */
  74         np = of_find_node_by_name(NULL, "bcsr");
  75         if (np != NULL) {
  76                 struct resource res;
  77
  78                 of_address_to_resource(np, 0, &res);
  79                 bcsr_regs = ioremap(res.start, res.end - res.start +1);
  80                 of_node_put(np);
  81         }
  82
  83 #ifdef CONFIG_PCI
  84         for_each_node_by_type(np, "pci") {
  85                 if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
  86                     of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
  87                         struct resource rsrc;
  88                         of_address_to_resource(np, 0, &rsrc);
  89                         if ((rsrc.start & 0xfffff) == 0x8000)
  90                                 fsl_add_bridge(np, 1);
  91                         else
  92                                 fsl_add_bridge(np, 0);
  93                 }
  94         }
  95 #endif
  96
  97 #ifdef CONFIG_QUICC_ENGINE
  98         if ((np = of_find_node_by_name(NULL, "qe")) != NULL) {
  99                 qe_reset();
 100                 of_node_put(np);
 101         }
 102
 103         if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
 104                 struct device_node *ucc = NULL;
 105
 106                 par_io_init(np);
 107                 of_node_put(np);
 108
 109                 for ( ;(ucc = of_find_node_by_name(ucc, "ucc")) != NULL;)
 110                         par_io_of_config(ucc);
 111
 112                 of_node_put(ucc);
 113         }
 114
 115         if (bcsr_regs) {
 116 #define BCSR_UCC1_GETH_EN       (0x1 << 7)
 117 #define BCSR_UCC2_GETH_EN       (0x1 << 7)
 118 #define BCSR_UCC1_MODE_MSK      (0x3 << 4)
 119 #define BCSR_UCC2_MODE_MSK      (0x3 << 0)
 120
 121                 /* Turn off UCC1 & UCC2 */
 122                 clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
 123                 clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
 124
 125                 /* Mode is RGMII, all bits clear */
 126                 clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
 127                                          BCSR_UCC2_MODE_MSK);
 128
 129                 /* Turn UCC1 & UCC2 on */
 130                 setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
 131                 setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
 132
 133                 iounmap(bcsr_regs);
 134         }
 135
 136 #endif  /* CONFIG_QUICC_ENGINE */
 137 }
 138
 139 static struct of_device_id mpc85xx_ids[] = {
 140         { .type = "soc", },
 141         { .compatible = "soc", },
 142         { .type = "qe", },
 143         {},
 144 };
 145
 146 static int __init mpc85xx_publish_devices(void)
 147 {
 148         if (!machine_is(mpc85xx_mds))
 149                 return 0;
 150
 151         /* Publish the QE devices */
 152         of_platform_bus_probe(NULL,mpc85xx_ids,NULL);
 153
 154         return 0;
 155 }
 156 device_initcall(mpc85xx_publish_devices);
 157
 158 static void __init mpc85xx_mds_pic_init(void)
 159 {
 160         struct mpic *mpic;
 161         struct resource r;
 162         struct device_node *np = NULL;
 163
 164         np = of_find_node_by_type(NULL, "open-pic");
 165         if (!np)
 166                 return;
 167
 168         if (of_address_to_resource(np, 0, &r)) {
 169                 printk(KERN_ERR "Failed to map mpic register space\n");
 170                 of_node_put(np);
 171                 return;
 172         }
 173
 174         mpic = mpic_alloc(np, r.start,
 175                         MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
 176                         0, 256, " OpenPIC  ");
 177         BUG_ON(mpic == NULL);
 178         of_node_put(np);
 179
 180         mpic_init(mpic);
 181
 182 #ifdef CONFIG_QUICC_ENGINE
 183         np = of_find_node_by_type(NULL, "qeic");
 184         if (!np)
 185                 return;
 186
 187         qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
 188         of_node_put(np);
 189 #endif                          /* CONFIG_QUICC_ENGINE */
 190 }
 191
 192 static int __init mpc85xx_mds_probe(void)
 193 {
 194         unsigned long root = of_get_flat_dt_root();
 195
 196         return of_flat_dt_is_compatible(root, "MPC85xxMDS");
 197 }
 198
 199 define_machine(mpc85xx_mds) {
 200         .name           = "MPC85xx MDS",
 201         .probe          = mpc85xx_mds_probe,
 202         .setup_arch     = mpc85xx_mds_setup_arch,
 203         .init_IRQ       = mpc85xx_mds_pic_init,
 204         .get_irq        = mpic_get_irq,
 205         .restart        = fsl_rstcr_restart,
 206         .calibrate_decr = generic_calibrate_decr,
 207         .progress       = udbg_progress,
 208 #ifdef CONFIG_PCI
 209         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 210 #endif
 211 };