2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
15 * Copyright IBM Corp. 2007
17 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
20 #include <linux/types.h>
21 #include <linux/string.h>
22 #include <linux/kvm.h>
23 #include <linux/kvm_host.h>
24 #include <linux/highmem.h>
26 #include <asm/tlbflush.h>
27 #include <asm/mmu-44x.h>
28 #include <asm/kvm_ppc.h>
29 #include <asm/kvm_44x.h>
33 #ifndef PPC44x_TLBE_SIZE
34 #define PPC44x_TLBE_SIZE PPC44x_TLB_4K
37 #define PAGE_SIZE_4K (1<<12)
38 #define PAGE_MASK_4K (~(PAGE_SIZE_4K - 1))
40 #define PPC44x_TLB_UATTR_MASK \
41 (PPC44x_TLB_U0|PPC44x_TLB_U1|PPC44x_TLB_U2|PPC44x_TLB_U3)
42 #define PPC44x_TLB_USER_PERM_MASK (PPC44x_TLB_UX|PPC44x_TLB_UR|PPC44x_TLB_UW)
43 #define PPC44x_TLB_SUPER_PERM_MASK (PPC44x_TLB_SX|PPC44x_TLB_SR|PPC44x_TLB_SW)
46 void kvmppc_dump_tlbs(struct kvm_vcpu *vcpu)
48 struct kvmppc_44x_tlbe *tlbe;
51 printk("vcpu %d TLB dump:\n", vcpu->vcpu_id);
52 printk("| %2s | %3s | %8s | %8s | %8s |\n",
53 "nr", "tid", "word0", "word1", "word2");
55 for (i = 0; i < ARRAY_SIZE(vcpu_44x->guest_tlb); i++) {
56 tlbe = &vcpu_44x->guest_tlb[i];
57 if (tlbe->word0 & PPC44x_TLB_VALID)
58 printk(" G%2d | %02X | %08X | %08X | %08X |\n",
59 i, tlbe->tid, tlbe->word0, tlbe->word1,
65 static inline void kvmppc_44x_tlbie(unsigned int index)
67 /* 0 <= index < 64, so the V bit is clear and we can use the index as
70 "tlbwe %[index], %[index], 0\n"
76 static inline void kvmppc_44x_tlbre(unsigned int index,
77 struct kvmppc_44x_tlbe *tlbe)
80 "tlbre %[word0], %[index], 0\n"
81 "mfspr %[tid], %[sprn_mmucr]\n"
82 "andi. %[tid], %[tid], 0xff\n"
83 "tlbre %[word1], %[index], 1\n"
84 "tlbre %[word2], %[index], 2\n"
85 : [word0] "=r"(tlbe->word0),
86 [word1] "=r"(tlbe->word1),
87 [word2] "=r"(tlbe->word2),
90 [sprn_mmucr] "i"(SPRN_MMUCR)
95 static inline void kvmppc_44x_tlbwe(unsigned int index,
96 struct kvmppc_44x_tlbe *stlbe)
101 "mfspr %[tmp], %[sprn_mmucr]\n"
102 "rlwimi %[tmp], %[tid], 0, 0xff\n"
103 "mtspr %[sprn_mmucr], %[tmp]\n"
104 "tlbwe %[word0], %[index], 0\n"
105 "tlbwe %[word1], %[index], 1\n"
106 "tlbwe %[word2], %[index], 2\n"
108 : [word0] "r"(stlbe->word0),
109 [word1] "r"(stlbe->word1),
110 [word2] "r"(stlbe->word2),
111 [tid] "r"(stlbe->tid),
113 [sprn_mmucr] "i"(SPRN_MMUCR)
117 static u32 kvmppc_44x_tlb_shadow_attrib(u32 attrib, int usermode)
119 /* We only care about the guest's permission and user bits. */
120 attrib &= PPC44x_TLB_PERM_MASK|PPC44x_TLB_UATTR_MASK;
123 /* Guest is in supervisor mode, so we need to translate guest
124 * supervisor permissions into user permissions. */
125 attrib &= ~PPC44x_TLB_USER_PERM_MASK;
126 attrib |= (attrib & PPC44x_TLB_SUPER_PERM_MASK) << 3;
129 /* Make sure host can always access this memory. */
130 attrib |= PPC44x_TLB_SX|PPC44x_TLB_SR|PPC44x_TLB_SW;
132 /* WIMGE = 0b00100 */
133 attrib |= PPC44x_TLB_M;
138 /* Load shadow TLB back into hardware. */
139 void kvmppc_44x_tlb_load(struct kvm_vcpu *vcpu)
141 struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);
144 for (i = 0; i <= tlb_44x_hwater; i++) {
145 struct kvmppc_44x_tlbe *stlbe = &vcpu_44x->shadow_tlb[i];
147 if (get_tlb_v(stlbe) && get_tlb_ts(stlbe))
148 kvmppc_44x_tlbwe(i, stlbe);
152 static void kvmppc_44x_tlbe_set_modified(struct kvmppc_vcpu_44x *vcpu_44x,
155 vcpu_44x->shadow_tlb_mod[i] = 1;
158 /* Save hardware TLB to the vcpu, and invalidate all guest mappings. */
159 void kvmppc_44x_tlb_put(struct kvm_vcpu *vcpu)
161 struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);
164 for (i = 0; i <= tlb_44x_hwater; i++) {
165 struct kvmppc_44x_tlbe *stlbe = &vcpu_44x->shadow_tlb[i];
167 if (vcpu_44x->shadow_tlb_mod[i])
168 kvmppc_44x_tlbre(i, stlbe);
170 if (get_tlb_v(stlbe) && get_tlb_ts(stlbe))
176 /* Search the guest TLB for a matching entry. */
177 int kvmppc_44x_tlb_index(struct kvm_vcpu *vcpu, gva_t eaddr, unsigned int pid,
180 struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);
183 /* XXX Replace loop with fancy data structures. */
184 for (i = 0; i < ARRAY_SIZE(vcpu_44x->guest_tlb); i++) {
185 struct kvmppc_44x_tlbe *tlbe = &vcpu_44x->guest_tlb[i];
188 if (eaddr < get_tlb_eaddr(tlbe))
191 if (eaddr > get_tlb_end(tlbe))
194 tid = get_tlb_tid(tlbe);
195 if (tid && (tid != pid))
198 if (!get_tlb_v(tlbe))
201 if (get_tlb_ts(tlbe) != as)
210 int kvmppc_44x_itlb_index(struct kvm_vcpu *vcpu, gva_t eaddr)
212 unsigned int as = !!(vcpu->arch.msr & MSR_IS);
214 return kvmppc_44x_tlb_index(vcpu, eaddr, vcpu->arch.pid, as);
217 int kvmppc_44x_dtlb_index(struct kvm_vcpu *vcpu, gva_t eaddr)
219 unsigned int as = !!(vcpu->arch.msr & MSR_DS);
221 return kvmppc_44x_tlb_index(vcpu, eaddr, vcpu->arch.pid, as);
224 static void kvmppc_44x_shadow_release(struct kvmppc_vcpu_44x *vcpu_44x,
225 unsigned int stlb_index)
227 struct kvmppc_44x_shadow_ref *ref = &vcpu_44x->shadow_refs[stlb_index];
232 /* Discard from the TLB. */
233 /* Note: we could actually invalidate a host mapping, if the host overwrote
234 * this TLB entry since we inserted a guest mapping. */
235 kvmppc_44x_tlbie(stlb_index);
237 /* Now release the page. */
239 kvm_release_page_dirty(ref->page);
241 kvm_release_page_clean(ref->page);
245 /* XXX set tlb_44x_index to stlb_index? */
247 KVMTRACE_1D(STLB_INVAL, &vcpu_44x->vcpu, stlb_index, handler);
250 void kvmppc_core_destroy_mmu(struct kvm_vcpu *vcpu)
252 struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);
255 for (i = 0; i <= tlb_44x_hwater; i++)
256 kvmppc_44x_shadow_release(vcpu_44x, i);
260 * kvmppc_mmu_map -- create a host mapping for guest memory
262 * If the guest wanted a larger page than the host supports, only the first
263 * host page is mapped here and the rest are demand faulted.
265 * If the guest wanted a smaller page than the host page size, we map only the
266 * guest-size page (i.e. not a full host page mapping).
268 * Caller must ensure that the specified guest TLB entry is safe to insert into
271 void kvmppc_mmu_map(struct kvm_vcpu *vcpu, u64 gvaddr, gpa_t gpaddr, u64 asid,
272 u32 flags, u32 max_bytes, unsigned int gtlb_index)
274 struct kvmppc_44x_tlbe stlbe;
275 struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);
276 struct kvmppc_44x_shadow_ref *ref;
277 struct page *new_page;
282 /* Select TLB entry to clobber. Indirectly guard against races with the TLB
283 * miss handler by disabling interrupts. */
285 victim = ++tlb_44x_index;
286 if (victim > tlb_44x_hwater)
288 tlb_44x_index = victim;
291 /* Get reference to new page. */
292 gfn = gpaddr >> PAGE_SHIFT;
293 new_page = gfn_to_page(vcpu->kvm, gfn);
294 if (is_error_page(new_page)) {
295 printk(KERN_ERR "Couldn't get guest page for gfn %lx!\n", gfn);
296 kvm_release_page_clean(new_page);
299 hpaddr = page_to_phys(new_page);
301 /* Invalidate any previous shadow mappings. */
302 kvmppc_44x_shadow_release(vcpu_44x, victim);
304 /* XXX Make sure (va, size) doesn't overlap any other
305 * entries. 440x6 user manual says the result would be
308 /* XXX what about AS? */
310 /* Force TS=1 for all guest mappings. */
311 stlbe.word0 = PPC44x_TLB_VALID | PPC44x_TLB_TS;
313 if (max_bytes >= PAGE_SIZE) {
314 /* Guest mapping is larger than or equal to host page size. We can use
315 * a "native" host mapping. */
316 stlbe.word0 |= (gvaddr & PAGE_MASK) | PPC44x_TLBE_SIZE;
318 /* Guest mapping is smaller than host page size. We must restrict the
319 * size of the mapping to be at most the smaller of the two, but for
320 * simplicity we fall back to a 4K mapping (this is probably what the
321 * guest is using anyways). */
322 stlbe.word0 |= (gvaddr & PAGE_MASK_4K) | PPC44x_TLB_4K;
324 /* 'hpaddr' is a host page, which is larger than the mapping we're
325 * inserting here. To compensate, we must add the in-page offset to the
327 hpaddr |= gpaddr & (PAGE_MASK ^ PAGE_MASK_4K);
330 stlbe.word1 = (hpaddr & 0xfffffc00) | ((hpaddr >> 32) & 0xf);
331 stlbe.word2 = kvmppc_44x_tlb_shadow_attrib(flags,
332 vcpu->arch.msr & MSR_PR);
333 stlbe.tid = !(asid & 0xff);
335 /* Keep track of the reference so we can properly release it later. */
336 ref = &vcpu_44x->shadow_refs[victim];
337 ref->page = new_page;
338 ref->gtlb_index = gtlb_index;
339 ref->writeable = !!(stlbe.word2 & PPC44x_TLB_UW);
340 ref->tid = stlbe.tid;
342 /* Insert shadow mapping into hardware TLB. */
343 kvmppc_44x_tlbe_set_modified(vcpu_44x, victim);
344 kvmppc_44x_tlbwe(victim, &stlbe);
345 KVMTRACE_5D(STLB_WRITE, vcpu, victim, stlbe.tid, stlbe.word0, stlbe.word1,
346 stlbe.word2, handler);
349 /* For a particular guest TLB entry, invalidate the corresponding host TLB
350 * mappings and release the host pages. */
351 static void kvmppc_44x_invalidate(struct kvm_vcpu *vcpu,
352 unsigned int gtlb_index)
354 struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);
357 for (i = 0; i < ARRAY_SIZE(vcpu_44x->shadow_refs); i++) {
358 struct kvmppc_44x_shadow_ref *ref = &vcpu_44x->shadow_refs[i];
359 if (ref->gtlb_index == gtlb_index)
360 kvmppc_44x_shadow_release(vcpu_44x, i);
364 void kvmppc_mmu_priv_switch(struct kvm_vcpu *vcpu, int usermode)
366 vcpu->arch.shadow_pid = !usermode;
369 void kvmppc_set_pid(struct kvm_vcpu *vcpu, u32 new_pid)
371 struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);
374 if (unlikely(vcpu->arch.pid == new_pid))
377 vcpu->arch.pid = new_pid;
379 /* Guest userspace runs with TID=0 mappings and PID=0, to make sure it
380 * can't access guest kernel mappings (TID=1). When we switch to a new
381 * guest PID, which will also use host PID=0, we must discard the old guest
382 * userspace mappings. */
383 for (i = 0; i < ARRAY_SIZE(vcpu_44x->shadow_refs); i++) {
384 struct kvmppc_44x_shadow_ref *ref = &vcpu_44x->shadow_refs[i];
387 kvmppc_44x_shadow_release(vcpu_44x, i);
391 static int tlbe_is_host_safe(const struct kvm_vcpu *vcpu,
392 const struct kvmppc_44x_tlbe *tlbe)
396 if (!get_tlb_v(tlbe))
399 /* Does it match current guest AS? */
400 /* XXX what about IS != DS? */
401 if (get_tlb_ts(tlbe) != !!(vcpu->arch.msr & MSR_IS))
404 gpa = get_tlb_raddr(tlbe);
405 if (!gfn_to_memslot(vcpu->kvm, gpa >> PAGE_SHIFT))
406 /* Mapping is not for RAM. */
412 int kvmppc_44x_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws)
414 struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);
415 struct kvmppc_44x_tlbe *tlbe;
416 unsigned int gtlb_index;
418 gtlb_index = vcpu->arch.gpr[ra];
419 if (gtlb_index > KVM44x_GUEST_TLB_SIZE) {
420 printk("%s: index %d\n", __func__, gtlb_index);
421 kvmppc_dump_vcpu(vcpu);
425 tlbe = &vcpu_44x->guest_tlb[gtlb_index];
427 /* Invalidate shadow mappings for the about-to-be-clobbered TLB entry. */
428 if (tlbe->word0 & PPC44x_TLB_VALID)
429 kvmppc_44x_invalidate(vcpu, gtlb_index);
432 case PPC44x_TLB_PAGEID:
433 tlbe->tid = get_mmucr_stid(vcpu);
434 tlbe->word0 = vcpu->arch.gpr[rs];
437 case PPC44x_TLB_XLAT:
438 tlbe->word1 = vcpu->arch.gpr[rs];
441 case PPC44x_TLB_ATTRIB:
442 tlbe->word2 = vcpu->arch.gpr[rs];
449 if (tlbe_is_host_safe(vcpu, tlbe)) {
456 eaddr = get_tlb_eaddr(tlbe);
457 gpaddr = get_tlb_raddr(tlbe);
459 /* Use the advertised page size to mask effective and real addrs. */
460 bytes = get_tlb_bytes(tlbe);
461 eaddr &= ~(bytes - 1);
462 gpaddr &= ~(bytes - 1);
464 asid = (tlbe->word0 & PPC44x_TLB_TS) | tlbe->tid;
465 flags = tlbe->word2 & 0xffff;
467 kvmppc_mmu_map(vcpu, eaddr, gpaddr, asid, flags, bytes, gtlb_index);
470 KVMTRACE_5D(GTLB_WRITE, vcpu, gtlb_index, tlbe->tid, tlbe->word0,
471 tlbe->word1, tlbe->word2, handler);
476 int kvmppc_44x_emul_tlbsx(struct kvm_vcpu *vcpu, u8 rt, u8 ra, u8 rb, u8 rc)
480 unsigned int as = get_mmucr_sts(vcpu);
481 unsigned int pid = get_mmucr_stid(vcpu);
483 ea = vcpu->arch.gpr[rb];
485 ea += vcpu->arch.gpr[ra];
487 gtlb_index = kvmppc_44x_tlb_index(vcpu, ea, pid, as);
490 vcpu->arch.cr &= ~0x20000000;
492 vcpu->arch.cr |= 0x20000000;
494 vcpu->arch.gpr[rt] = gtlb_index;