2 * arch/powerpc/kernel/misc64.S
4 * This file contains miscellaneous low-level functions.
5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
7 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
9 * Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com)
10 * PPC64 updates by Dave Engebretsen (engebret@us.ibm.com)
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
19 #include <linux/config.h>
20 #include <linux/sys.h>
21 #include <asm/unistd.h>
22 #include <asm/errno.h>
23 #include <asm/processor.h>
25 #include <asm/cache.h>
26 #include <asm/ppc_asm.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/cputable.h>
29 #include <asm/thread_info.h>
34 * Returns (address we are running at) - (address we were linked at)
35 * for use before the text and data are mapped to KERNELBASE.
42 LOAD_REG_IMMEDIATE(r4,1b)
48 * add_reloc_offset(x) returns x + reloc_offset().
50 _GLOBAL(add_reloc_offset)
54 LOAD_REG_IMMEDIATE(r4,1b)
80 #ifdef CONFIG_IRQSTACKS
81 _GLOBAL(call_do_softirq)
84 stdu r1,THREAD_SIZE-112(r3)
92 _GLOBAL(call___do_IRQ)
95 stdu r1,THREAD_SIZE-112(r5)
102 #endif /* CONFIG_IRQSTACKS */
106 .tc ppc64_caches[TC],ppc64_caches
110 * Write any modified data cache blocks out to memory
111 * and invalidate the corresponding instruction cache blocks.
113 * flush_icache_range(unsigned long start, unsigned long stop)
115 * flush all bytes from start through stop-1 inclusive
118 _KPROBE(__flush_icache_range)
121 * Flush the data cache to memory
123 * Different systems have different cache line sizes
124 * and in some cases i-cache and d-cache line sizes differ from
127 ld r10,PPC64_CACHES@toc(r2)
128 lwz r7,DCACHEL1LINESIZE(r10)/* Get cache line size */
130 andc r6,r3,r5 /* round low to line bdy */
131 subf r8,r6,r4 /* compute length */
132 add r8,r8,r5 /* ensure we get enough */
133 lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of cache line size */
134 srw. r8,r8,r9 /* compute line count */
135 beqlr /* nothing to do? */
142 /* Now invalidate the instruction cache */
144 lwz r7,ICACHEL1LINESIZE(r10) /* Get Icache line size */
146 andc r6,r3,r5 /* round low to line bdy */
147 subf r8,r6,r4 /* compute length */
149 lwz r9,ICACHEL1LOGLINESIZE(r10) /* Get log-2 of Icache line size */
150 srw. r8,r8,r9 /* compute line count */
151 beqlr /* nothing to do? */
160 * Like above, but only do the D-cache.
162 * flush_dcache_range(unsigned long start, unsigned long stop)
164 * flush all bytes from start to stop-1 inclusive
166 _GLOBAL(flush_dcache_range)
169 * Flush the data cache to memory
171 * Different systems have different cache line sizes
173 ld r10,PPC64_CACHES@toc(r2)
174 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
176 andc r6,r3,r5 /* round low to line bdy */
177 subf r8,r6,r4 /* compute length */
178 add r8,r8,r5 /* ensure we get enough */
179 lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */
180 srw. r8,r8,r9 /* compute line count */
181 beqlr /* nothing to do? */
190 * Like above, but works on non-mapped physical addresses.
191 * Use only for non-LPAR setups ! It also assumes real mode
192 * is cacheable. Used for flushing out the DART before using
193 * it as uncacheable memory
195 * flush_dcache_phys_range(unsigned long start, unsigned long stop)
197 * flush all bytes from start to stop-1 inclusive
199 _GLOBAL(flush_dcache_phys_range)
200 ld r10,PPC64_CACHES@toc(r2)
201 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
203 andc r6,r3,r5 /* round low to line bdy */
204 subf r8,r6,r4 /* compute length */
205 add r8,r8,r5 /* ensure we get enough */
206 lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */
207 srw. r8,r8,r9 /* compute line count */
208 beqlr /* nothing to do? */
209 mfmsr r5 /* Disable MMU Data Relocation */
222 mtmsr r5 /* Re-enable MMU Data Relocation */
227 _GLOBAL(flush_inval_dcache_range)
228 ld r10,PPC64_CACHES@toc(r2)
229 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
231 andc r6,r3,r5 /* round low to line bdy */
232 subf r8,r6,r4 /* compute length */
233 add r8,r8,r5 /* ensure we get enough */
234 lwz r9,DCACHEL1LOGLINESIZE(r10)/* Get log-2 of dcache line size */
235 srw. r8,r8,r9 /* compute line count */
236 beqlr /* nothing to do? */
249 * Flush a particular page from the data cache to RAM.
250 * Note: this is necessary because the instruction cache does *not*
251 * snoop from the data cache.
253 * void __flush_dcache_icache(void *page)
255 _GLOBAL(__flush_dcache_icache)
257 * Flush the data cache to memory
259 * Different systems have different cache line sizes
262 /* Flush the dcache */
263 ld r7,PPC64_CACHES@toc(r2)
264 clrrdi r3,r3,PAGE_SHIFT /* Page align */
265 lwz r4,DCACHEL1LINESPERPAGE(r7) /* Get # dcache lines per page */
266 lwz r5,DCACHEL1LINESIZE(r7) /* Get dcache line size */
274 /* Now invalidate the icache */
276 lwz r4,ICACHEL1LINESPERPAGE(r7) /* Get # icache lines per page */
277 lwz r5,ICACHEL1LINESIZE(r7) /* Get icache line size */
286 * I/O string operations
288 * insb(port, buf, len)
289 * outsb(port, buf, len)
290 * insw(port, buf, len)
291 * outsw(port, buf, len)
292 * insl(port, buf, len)
293 * outsl(port, buf, len)
294 * insw_ns(port, buf, len)
295 * outsw_ns(port, buf, len)
296 * insl_ns(port, buf, len)
297 * outsl_ns(port, buf, len)
299 * The *_ns versions don't do byte-swapping.
373 /* _GLOBAL(ide_insw) now in drivers/ide/ide-iops.c */
387 /* _GLOBAL(ide_outsw) now in drivers/ide/ide-iops.c */
424 * identify_cpu and calls setup_cpu
425 * In: r3 = base of the cpu_specs array
426 * r4 = address of cur_cpu_spec
427 * r5 = relocation offset
429 _GLOBAL(identify_cpu)
432 lwz r8,CPU_SPEC_PVR_MASK(r3)
434 lwz r9,CPU_SPEC_PVR_VALUE(r3)
437 addi r3,r3,CPU_SPEC_ENTRY_SIZE
442 ld r4,CPU_SPEC_SETUP(r3)
449 /* Calling convention for cpu setup is r3=offset, r4=cur_cpu_spec */
455 * do_cpu_ftr_fixups - goes through the list of CPU feature fixups
456 * and writes nop's over sections of code that don't apply for this cpu.
457 * r3 = data offset (not changed)
459 _GLOBAL(do_cpu_ftr_fixups)
460 /* Get CPU 0 features */
461 LOAD_REG_IMMEDIATE(r6,cur_cpu_spec)
465 ld r4,CPU_SPEC_FEATURES(r4)
466 /* Get the fixup table */
467 LOAD_REG_IMMEDIATE(r6,__start___ftr_fixup)
469 LOAD_REG_IMMEDIATE(r7,__stop___ftr_fixup)
475 ld r8,-32(r6) /* mask */
477 ld r9,-24(r6) /* value */
480 ld r8,-16(r6) /* section begin */
481 ld r9,-8(r6) /* section end */
484 /* write nops over the section of code */
485 /* todo: if large section, add a branch at the start of it */
489 lis r0,0x60000000@h /* nop */
491 andi. r10,r4,CPU_FTR_SPLIT_ID_CACHE@l
493 dcbst 0,r8 /* suboptimal, but simpler */
498 sync /* additional sync needed on g4 */
502 #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE)
504 * Do an IO access in real mode
535 * Do an IO access in real mode
564 #endif /* defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) */
567 * SCOM access functions for 970 (FX only for now)
569 * unsigned long scom970_read(unsigned int address);
570 * void scom970_write(unsigned int address, unsigned long value);
572 * The address passed in is the 24 bits register address. This code
573 * is 970 specific and will not check the status bits, so you should
574 * know what you are doing.
576 _GLOBAL(scom970_read)
583 /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
584 * (including parity). On current CPUs they must be 0'd,
585 * and finally or in RW bit
590 /* do the actual scom read */
599 /* XXX: fixup result on some buggy 970's (ouch ! we lost a bit, bah
600 * that's the best we can do). Not implemented yet as we don't use
601 * the scom on any of the bogus CPUs yet, but may have to be done
605 /* restore interrupts */
610 _GLOBAL(scom970_write)
617 /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
618 * (including parity). On current CPUs they must be 0'd.
624 mtspr SPRN_SCOMD,r4 /* write data */
626 mtspr SPRN_SCOMC,r3 /* write command */
631 /* restore interrupts */
637 * Create a kernel thread
638 * kernel_thread(fn, arg, flags)
640 _GLOBAL(kernel_thread)
643 stdu r1,-STACK_FRAME_OVERHEAD(r1)
646 ori r3,r5,CLONE_VM /* flags */
647 oris r3,r3,(CLONE_UNTRACED>>16)
648 li r4,0 /* new sp (unused) */
651 cmpdi 0,r3,0 /* parent or child? */
652 bne 1f /* return if parent */
654 stdu r0,-STACK_FRAME_OVERHEAD(r1)
657 mtlr r29 /* fn addr in lr */
658 mr r3,r30 /* load arg and call fn */
660 li r0,__NR_exit /* exit after child exits */
663 1: addi r1,r1,STACK_FRAME_OVERHEAD
669 * disable_kernel_fp()
672 _GLOBAL(disable_kernel_fp)
674 rldicl r0,r3,(63-MSR_FP_LG),1
675 rldicl r3,r0,(MSR_FP_LG+1),0
676 mtmsrd r3 /* disable use of fpu now */
680 #ifdef CONFIG_ALTIVEC
682 #if 0 /* this has no callers for now */
684 * disable_kernel_altivec()
687 _GLOBAL(disable_kernel_altivec)
689 rldicl r0,r3,(63-MSR_VEC_LG),1
690 rldicl r3,r0,(MSR_VEC_LG+1),0
691 mtmsrd r3 /* disable use of VMX now */
697 * giveup_altivec(tsk)
698 * Disable VMX for the task given as the argument,
699 * and save the vector registers in its thread_struct.
700 * Enables the VMX for use in the kernel on return.
702 _GLOBAL(giveup_altivec)
705 mtmsrd r5 /* enable use of VMX now */
708 beqlr- /* if no previous owner, done */
709 addi r3,r3,THREAD /* want THREAD of task */
717 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
719 andc r4,r4,r3 /* disable FP for previous task */
720 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
724 ld r4,last_task_used_altivec@got(r2)
726 #endif /* CONFIG_SMP */
729 #endif /* CONFIG_ALTIVEC */
738 /* kexec_wait(phys_cpu)
740 * wait for the flag to change, indicating this kernel is going away but
741 * the slave code for the next one is at addresses 0 to 100.
743 * This is used by all slaves.
745 * Physical (hardware) cpu id should be in r3.
750 addi r5,r5,kexec_flag-1b
753 #ifdef CONFIG_KEXEC /* use no memory without kexec */
760 /* this can be in text because we won't change it until we are
761 * running in real anyways
769 /* kexec_smp_wait(void)
771 * call with interrupts off
772 * note: this is a terminal routine, it does not save lr
774 * get phys id from paca
775 * set paca id to -1 to say we got here
776 * switch to real mode
777 * join other cpus in kexec_wait(phys_id)
779 _GLOBAL(kexec_smp_wait)
780 lhz r3,PACAHWCPUID(r13)
782 sth r4,PACAHWCPUID(r13) /* let others know we left */
787 * switch to real mode (turn mmu off)
788 * we use the early kernel trick that the hardware ignores bits
789 * 0 and 1 (big endian) of the effective address in real mode
791 * don't overwrite r3 here, it is live for kexec_wait above.
793 real_mode: /* assume normal blr return */
796 mflr r11 /* return address to SRR0 */
808 * kexec_sequence(newstack, start, image, control, clear_all())
810 * does the grungy work with stack switching and real mode switches
811 * also does simple calls to other code
814 _GLOBAL(kexec_sequence)
818 /* switch stacks to newstack -- &kexec_stack.stack */
819 stdu r1,THREAD_SIZE-112(r3)
825 /* save regs for local vars on new stack.
826 * yes, we won't go back, but ...
838 /* save args into preserved regs */
839 mr r31,r3 /* newstack (both) */
840 mr r30,r4 /* start (real) */
841 mr r29,r5 /* image (virt) */
842 mr r28,r6 /* control, unused */
843 mr r27,r7 /* clear_all() fn desc */
844 mr r26,r8 /* spare */
845 lhz r25,PACAHWCPUID(r13) /* get our phys cpu from paca */
847 /* disable interrupts, we are overwriting kernel data next */
852 /* copy dest pages, flush whole dest image */
854 bl .kexec_copy_flush /* (image) */
859 /* clear out hardware hash page table and tlb */
860 ld r5,0(r27) /* deref function descriptor */
862 bctrl /* ppc_md.hash_clear_all(void); */
865 * kexec image calling is:
866 * the first 0x100 bytes of the entry point are copied to 0
868 * all slaves branch to slave = 0x60 (absolute)
869 * slave(phys_cpu_id);
871 * master goes to start = entry point
872 * start(phys_cpu_id, start, 0);
875 * a wrapper is needed to call existing kernels, here is an approximate
876 * description of one method:
879 * start will be near the boot_block (maybe 0x100 bytes before it?)
880 * it will have a 0x60, which will b to boot_block, where it will wait
881 * and 0 will store phys into struct boot-block and load r3 from there,
882 * copy kernel 0-0x100 and tell slaves to back down to 0x60 again
885 * boot block will have all cpus scanning device tree to see if they
886 * are the boot cpu ?????
887 * other device tree differences (prop sizes, va vs pa, etc)...
890 /* copy 0x100 bytes starting at start to 0 */
895 bl .copy_and_flush /* (dest, src, copy limit, start offset) */
896 1: /* assume normal blr return */
898 /* release other cpus to the new kernel secondary start at 0x60 */
901 stw r6,kexec_flag-1b(5)
902 mr r3,r25 # my phys cpu
903 mr r4,r30 # start, aka phys mem offset
906 blr /* image->start(physid, image->start, 0); */
907 #endif /* CONFIG_KEXEC */