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   1 /*
   2  *  PowerPC version
   3  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
   4  *
   5  *  Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
   6  *    Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
   7  *  Adapted for Power Macintosh by Paul Mackerras.
   8  *  Low-level exception handlers and MMU support
   9  *  rewritten by Paul Mackerras.
  10  *    Copyright (C) 1996 Paul Mackerras.
  11  *
  12  *  Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
  13  *    Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
  14  *
  15  *  This file contains the low-level support and setup for the
  16  *  PowerPC-64 platform, including trap and interrupt dispatch.
  17  *
  18  *  This program is free software; you can redistribute it and/or
  19  *  modify it under the terms of the GNU General Public License
  20  *  as published by the Free Software Foundation; either version
  21  *  2 of the License, or (at your option) any later version.
  22  */
  23
  24 #include <linux/threads.h>
  25 #include <asm/reg.h>
  26 #include <asm/page.h>
  27 #include <asm/mmu.h>
  28 #include <asm/ppc_asm.h>
  29 #include <asm/asm-offsets.h>
  30 #include <asm/bug.h>
  31 #include <asm/cputable.h>
  32 #include <asm/setup.h>
  33 #include <asm/hvcall.h>
  34 #include <asm/iseries/lpar_map.h>
  35 #include <asm/thread_info.h>
  36 #include <asm/firmware.h>
  37
  38 #define DO_SOFT_DISABLE
  39
  40 /*
  41  * We layout physical memory as follows:
  42  * 0x0000 - 0x00ff : Secondary processor spin code
  43  * 0x0100 - 0x2fff : pSeries Interrupt prologs
  44  * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs
  45  * 0x6000 - 0x6fff : Initial (CPU0) segment table
  46  * 0x7000 - 0x7fff : FWNMI data area
  47  * 0x8000 -        : Early init and support code
  48  */
  49
  50 /*
  51  *   SPRG Usage
  52  *
  53  *   Register   Definition
  54  *
  55  *   SPRG0      reserved for hypervisor
  56  *   SPRG1      temp - used to save gpr
  57  *   SPRG2      temp - used to save gpr
  58  *   SPRG3      virt addr of paca
  59  */
  60
  61 /*
  62  * Entering into this code we make the following assumptions:
  63  *  For pSeries:
  64  *   1. The MMU is off & open firmware is running in real mode.
  65  *   2. The kernel is entered at __start
  66  *
  67  *  For iSeries:
  68  *   1. The MMU is on (as it always is for iSeries)
  69  *   2. The kernel is entered at system_reset_iSeries
  70  */
  71
  72         .text
  73         .globl  _stext
  74 _stext:
  75 #ifdef CONFIG_PPC_MULTIPLATFORM
  76 _GLOBAL(__start)
  77         /* NOP this out unconditionally */
  78 BEGIN_FTR_SECTION
  79         b       .__start_initialization_multiplatform
  80 END_FTR_SECTION(0, 1)
  81 #endif /* CONFIG_PPC_MULTIPLATFORM */
  82
  83         /* Catch branch to 0 in real mode */
  84         trap
  85
  86         /* Secondary processors spin on this value until it goes to 1. */
  87         .globl  __secondary_hold_spinloop
  88 __secondary_hold_spinloop:
  89         .llong  0x0
  90
  91         /* Secondary processors write this value with their cpu # */
  92         /* after they enter the spin loop immediately below.      */
  93         .globl  __secondary_hold_acknowledge
  94 __secondary_hold_acknowledge:
  95         .llong  0x0
  96
  97 #ifdef CONFIG_PPC_ISERIES
  98         /*
  99          * At offset 0x20, there is a pointer to iSeries LPAR data.
 100          * This is required by the hypervisor
 101          */
 102         . = 0x20
 103         .llong hvReleaseData-KERNELBASE
 104 #endif /* CONFIG_PPC_ISERIES */
 105
 106         . = 0x60
 107 /*
 108  * The following code is used on pSeries to hold secondary processors
 109  * in a spin loop after they have been freed from OpenFirmware, but
 110  * before the bulk of the kernel has been relocated.  This code
 111  * is relocated to physical address 0x60 before prom_init is run.
 112  * All of it must fit below the first exception vector at 0x100.
 113  */
 114 _GLOBAL(__secondary_hold)
 115         mfmsr   r24
 116         ori     r24,r24,MSR_RI
 117         mtmsrd  r24                     /* RI on */
 118
 119         /* Grab our physical cpu number */
 120         mr      r24,r3
 121
 122         /* Tell the master cpu we're here */
 123         /* Relocation is off & we are located at an address less */
 124         /* than 0x100, so only need to grab low order offset.    */
 125         std     r24,__secondary_hold_acknowledge@l(0)
 126         sync
 127
 128         /* All secondary cpus wait here until told to start. */
 129 100:    ld      r4,__secondary_hold_spinloop@l(0)
 130         cmpdi   0,r4,1
 131         bne     100b
 132
 133 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
 134         LOAD_REG_IMMEDIATE(r4, .generic_secondary_smp_init)
 135         mtctr   r4
 136         mr      r3,r24
 137         bctr
 138 #else
 139         BUG_OPCODE
 140 #endif
 141
 142 /* This value is used to mark exception frames on the stack. */
 143         .section ".toc","aw"
 144 exception_marker:
 145         .tc     ID_72656773_68657265[TC],0x7265677368657265
 146         .text
 147
 148 /*
 149  * The following macros define the code that appears as
 150  * the prologue to each of the exception handlers.  They
 151  * are split into two parts to allow a single kernel binary
 152  * to be used for pSeries and iSeries.
 153  * LOL.  One day... - paulus
 154  */
 155
 156 /*
 157  * We make as much of the exception code common between native
 158  * exception handlers (including pSeries LPAR) and iSeries LPAR
 159  * implementations as possible.
 160  */
 161
 162 /*
 163  * This is the start of the interrupt handlers for pSeries
 164  * This code runs with relocation off.
 165  */
 166 #define EX_R9           0
 167 #define EX_R10          8
 168 #define EX_R11          16
 169 #define EX_R12          24
 170 #define EX_R13          32
 171 #define EX_SRR0         40
 172 #define EX_DAR          48
 173 #define EX_DSISR        56
 174 #define EX_CCR          60
 175 #define EX_R3           64
 176 #define EX_LR           72
 177
 178 /*
 179  * We're short on space and time in the exception prolog, so we can't
 180  * use the normal SET_REG_IMMEDIATE macro. Normally we just need the
 181  * low halfword of the address, but for Kdump we need the whole low
 182  * word.
 183  */
 184 #ifdef CONFIG_CRASH_DUMP
 185 #define LOAD_HANDLER(reg, label)                                        \
 186         oris    reg,reg,(label)@h;      /* virt addr of handler ... */  \
 187         ori     reg,reg,(label)@l;      /* .. and the rest */
 188 #else
 189 #define LOAD_HANDLER(reg, label)                                        \
 190         ori     reg,reg,(label)@l;      /* virt addr of handler ... */
 191 #endif
 192
 193 /*
 194  * Equal to EXCEPTION_PROLOG_PSERIES, except that it forces 64bit mode.
 195  * The firmware calls the registered system_reset_fwnmi and
 196  * machine_check_fwnmi handlers in 32bit mode if the cpu happens to run
 197  * a 32bit application at the time of the event.
 198  * This firmware bug is present on POWER4 and JS20.
 199  */
 200 #define EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(area, label)               \
 201         mfspr   r13,SPRN_SPRG3;         /* get paca address into r13 */ \
 202         std     r9,area+EX_R9(r13);     /* save r9 - r12 */             \
 203         std     r10,area+EX_R10(r13);                                   \
 204         std     r11,area+EX_R11(r13);                                   \
 205         std     r12,area+EX_R12(r13);                                   \
 206         mfspr   r9,SPRN_SPRG1;                                          \
 207         std     r9,area+EX_R13(r13);                                    \
 208         mfcr    r9;                                                     \
 209         clrrdi  r12,r13,32;             /* get high part of &label */   \
 210         mfmsr   r10;                                                    \
 211         /* force 64bit mode */                                          \
 212         li      r11,5;                  /* MSR_SF_LG|MSR_ISF_LG */      \
 213         rldimi  r10,r11,61,0;           /* insert into top 3 bits */    \
 214         /* done 64bit mode */                                           \
 215         mfspr   r11,SPRN_SRR0;          /* save SRR0 */                 \
 216         LOAD_HANDLER(r12,label)                                         \
 217         ori     r10,r10,MSR_IR|MSR_DR|MSR_RI;                           \
 218         mtspr   SPRN_SRR0,r12;                                          \
 219         mfspr   r12,SPRN_SRR1;          /* and SRR1 */                  \
 220         mtspr   SPRN_SRR1,r10;                                          \
 221         rfid;                                                           \
 222         b       .       /* prevent speculative execution */
 223
 224 #define EXCEPTION_PROLOG_PSERIES(area, label)                           \
 225         mfspr   r13,SPRN_SPRG3;         /* get paca address into r13 */ \
 226         std     r9,area+EX_R9(r13);     /* save r9 - r12 */             \
 227         std     r10,area+EX_R10(r13);                                   \
 228         std     r11,area+EX_R11(r13);                                   \
 229         std     r12,area+EX_R12(r13);                                   \
 230         mfspr   r9,SPRN_SPRG1;                                          \
 231         std     r9,area+EX_R13(r13);                                    \
 232         mfcr    r9;                                                     \
 233         clrrdi  r12,r13,32;             /* get high part of &label */   \
 234         mfmsr   r10;                                                    \
 235         mfspr   r11,SPRN_SRR0;          /* save SRR0 */                 \
 236         LOAD_HANDLER(r12,label)                                         \
 237         ori     r10,r10,MSR_IR|MSR_DR|MSR_RI;                           \
 238         mtspr   SPRN_SRR0,r12;                                          \
 239         mfspr   r12,SPRN_SRR1;          /* and SRR1 */                  \
 240         mtspr   SPRN_SRR1,r10;                                          \
 241         rfid;                                                           \
 242         b       .       /* prevent speculative execution */
 243
 244 /*
 245  * This is the start of the interrupt handlers for iSeries
 246  * This code runs with relocation on.
 247  */
 248 #define EXCEPTION_PROLOG_ISERIES_1(area)                                \
 249         mfspr   r13,SPRN_SPRG3;         /* get paca address into r13 */ \
 250         std     r9,area+EX_R9(r13);     /* save r9 - r12 */             \
 251         std     r10,area+EX_R10(r13);                                   \
 252         std     r11,area+EX_R11(r13);                                   \
 253         std     r12,area+EX_R12(r13);                                   \
 254         mfspr   r9,SPRN_SPRG1;                                          \
 255         std     r9,area+EX_R13(r13);                                    \
 256         mfcr    r9
 257
 258 #define EXCEPTION_PROLOG_ISERIES_2                                      \
 259         mfmsr   r10;                                                    \
 260         ld      r12,PACALPPACAPTR(r13);                                 \
 261         ld      r11,LPPACASRR0(r12);                                    \
 262         ld      r12,LPPACASRR1(r12);                                    \
 263         ori     r10,r10,MSR_RI;                                         \
 264         mtmsrd  r10,1
 265
 266 /*
 267  * The common exception prolog is used for all except a few exceptions
 268  * such as a segment miss on a kernel address.  We have to be prepared
 269  * to take another exception from the point where we first touch the
 270  * kernel stack onwards.
 271  *
 272  * On entry r13 points to the paca, r9-r13 are saved in the paca,
 273  * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
 274  * SRR1, and relocation is on.
 275  */
 276 #define EXCEPTION_PROLOG_COMMON(n, area)                                   \
 277         andi.   r10,r12,MSR_PR;         /* See if coming from user      */ \
 278         mr      r10,r1;                 /* Save r1                      */ \
 279         subi    r1,r1,INT_FRAME_SIZE;   /* alloc frame on kernel stack  */ \
 280         beq-    1f;                                                        \
 281         ld      r1,PACAKSAVE(r13);      /* kernel stack to use          */ \
 282 1:      cmpdi   cr1,r1,0;               /* check if r1 is in userspace  */ \
 283         bge-    cr1,bad_stack;          /* abort if it is               */ \
 284         std     r9,_CCR(r1);            /* save CR in stackframe        */ \
 285         std     r11,_NIP(r1);           /* save SRR0 in stackframe      */ \
 286         std     r12,_MSR(r1);           /* save SRR1 in stackframe      */ \
 287         std     r10,0(r1);              /* make stack chain pointer     */ \
 288         std     r0,GPR0(r1);            /* save r0 in stackframe        */ \
 289         std     r10,GPR1(r1);           /* save r1 in stackframe        */ \
 290         ACCOUNT_CPU_USER_ENTRY(r9, r10);                                   \
 291         std     r2,GPR2(r1);            /* save r2 in stackframe        */ \
 292         SAVE_4GPRS(3, r1);              /* save r3 - r6 in stackframe   */ \
 293         SAVE_2GPRS(7, r1);              /* save r7, r8 in stackframe    */ \
 294         ld      r9,area+EX_R9(r13);     /* move r9, r10 to stackframe   */ \
 295         ld      r10,area+EX_R10(r13);                                      \
 296         std     r9,GPR9(r1);                                               \
 297         std     r10,GPR10(r1);                                             \
 298         ld      r9,area+EX_R11(r13);    /* move r11 - r13 to stackframe */ \
 299         ld      r10,area+EX_R12(r13);                                      \
 300         ld      r11,area+EX_R13(r13);                                      \
 301         std     r9,GPR11(r1);                                              \
 302         std     r10,GPR12(r1);                                             \
 303         std     r11,GPR13(r1);                                             \
 304         ld      r2,PACATOC(r13);        /* get kernel TOC into r2       */ \
 305         mflr    r9;                     /* save LR in stackframe        */ \
 306         std     r9,_LINK(r1);                                              \
 307         mfctr   r10;                    /* save CTR in stackframe       */ \
 308         std     r10,_CTR(r1);                                              \
 309         lbz     r10,PACASOFTIRQEN(r13);                            \
 310         mfspr   r11,SPRN_XER;           /* save XER in stackframe       */ \
 311         std     r10,SOFTE(r1);                                             \
 312         std     r11,_XER(r1);                                              \
 313         li      r9,(n)+1;                                                  \
 314         std     r9,_TRAP(r1);           /* set trap number              */ \
 315         li      r10,0;                                                     \
 316         ld      r11,exception_marker@toc(r2);                              \
 317         std     r10,RESULT(r1);         /* clear regs->result           */ \
 318         std     r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame      */
 319
 320 /*
 321  * Exception vectors.
 322  */
 323 #define STD_EXCEPTION_PSERIES(n, label)                 \
 324         . = n;                                          \
 325         .globl label##_pSeries;                         \
 326 label##_pSeries:                                        \
 327         HMT_MEDIUM;                                     \
 328         mtspr   SPRN_SPRG1,r13;         /* save r13 */  \
 329         EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
 330
 331 #define HSTD_EXCEPTION_PSERIES(n, label)                \
 332         . = n;                                          \
 333         .globl label##_pSeries;                         \
 334 label##_pSeries:                                        \
 335         HMT_MEDIUM;                                     \
 336         mtspr   SPRN_SPRG1,r20;         /* save r20 */  \
 337         mfspr   r20,SPRN_HSRR0;         /* copy HSRR0 to SRR0 */ \
 338         mtspr   SPRN_SRR0,r20;                          \
 339         mfspr   r20,SPRN_HSRR1;         /* copy HSRR0 to SRR0 */ \
 340         mtspr   SPRN_SRR1,r20;                          \
 341         mfspr   r20,SPRN_SPRG1;         /* restore r20 */ \
 342         mtspr   SPRN_SPRG1,r13;         /* save r13 */  \
 343         EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
 344
 345
 346 #define MASKABLE_EXCEPTION_PSERIES(n, label)                            \
 347         . = n;                                                          \
 348         .globl label##_pSeries;                                         \
 349 label##_pSeries:                                                        \
 350         HMT_MEDIUM;                                                     \
 351         mtspr   SPRN_SPRG1,r13;         /* save r13 */                  \
 352         mfspr   r13,SPRN_SPRG3;         /* get paca address into r13 */ \
 353         std     r9,PACA_EXGEN+EX_R9(r13);       /* save r9, r10 */      \
 354         std     r10,PACA_EXGEN+EX_R10(r13);                             \
 355         lbz     r10,PACASOFTIRQEN(r13);                                 \
 356         mfcr    r9;                                                     \
 357         cmpwi   r10,0;                                                  \
 358         beq     masked_interrupt;                                       \
 359         mfspr   r10,SPRN_SPRG1;                                         \
 360         std     r10,PACA_EXGEN+EX_R13(r13);                             \
 361         std     r11,PACA_EXGEN+EX_R11(r13);                             \
 362         std     r12,PACA_EXGEN+EX_R12(r13);                             \
 363         clrrdi  r12,r13,32;             /* get high part of &label */   \
 364         mfmsr   r10;                                                    \
 365         mfspr   r11,SPRN_SRR0;          /* save SRR0 */                 \
 366         LOAD_HANDLER(r12,label##_common)                                \
 367         ori     r10,r10,MSR_IR|MSR_DR|MSR_RI;                           \
 368         mtspr   SPRN_SRR0,r12;                                          \
 369         mfspr   r12,SPRN_SRR1;          /* and SRR1 */                  \
 370         mtspr   SPRN_SRR1,r10;                                          \
 371         rfid;                                                           \
 372         b       .       /* prevent speculative execution */
 373
 374 #define STD_EXCEPTION_ISERIES(n, label, area)           \
 375         .globl label##_iSeries;                         \
 376 label##_iSeries:                                        \
 377         HMT_MEDIUM;                                     \
 378         mtspr   SPRN_SPRG1,r13;         /* save r13 */  \
 379         EXCEPTION_PROLOG_ISERIES_1(area);               \
 380         EXCEPTION_PROLOG_ISERIES_2;                     \
 381         b       label##_common
 382
 383 #define MASKABLE_EXCEPTION_ISERIES(n, label)                            \
 384         .globl label##_iSeries;                                         \
 385 label##_iSeries:                                                        \
 386         HMT_MEDIUM;                                                     \
 387         mtspr   SPRN_SPRG1,r13;         /* save r13 */                  \
 388         EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN);                         \
 389         lbz     r10,PACASOFTIRQEN(r13);                                 \
 390         cmpwi   0,r10,0;                                                \
 391         beq-    label##_iSeries_masked;                                 \
 392         EXCEPTION_PROLOG_ISERIES_2;                                     \
 393         b       label##_common;                                         \
 394
 395 #ifdef CONFIG_PPC_ISERIES
 396 #define DISABLE_INTS                            \
 397         li      r11,0;                          \
 398         stb     r11,PACASOFTIRQEN(r13);         \
 399 BEGIN_FW_FTR_SECTION;                           \
 400         stb     r11,PACAHARDIRQEN(r13);         \
 401 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES);   \
 402 BEGIN_FW_FTR_SECTION;                           \
 403         mfmsr   r10;                            \
 404         ori     r10,r10,MSR_EE;                 \
 405         mtmsrd  r10,1;                          \
 406 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
 407
 408 #else
 409 #define DISABLE_INTS                            \
 410         li      r11,0;                          \
 411         stb     r11,PACASOFTIRQEN(r13);         \
 412         stb     r11,PACAHARDIRQEN(r13)
 413
 414 #endif /* CONFIG_PPC_ISERIES */
 415
 416 #define ENABLE_INTS                             \
 417         ld      r12,_MSR(r1);                   \
 418         mfmsr   r11;                            \
 419         rlwimi  r11,r12,0,MSR_EE;               \
 420         mtmsrd  r11,1
 421
 422 #define STD_EXCEPTION_COMMON(trap, label, hdlr)         \
 423         .align  7;                                      \
 424         .globl label##_common;                          \
 425 label##_common:                                         \
 426         EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN);      \
 427         DISABLE_INTS;                                   \
 428         bl      .save_nvgprs;                           \
 429         addi    r3,r1,STACK_FRAME_OVERHEAD;             \
 430         bl      hdlr;                                   \
 431         b       .ret_from_except
 432
 433 /*
 434  * Like STD_EXCEPTION_COMMON, but for exceptions that can occur
 435  * in the idle task and therefore need the special idle handling.
 436  */
 437 #define STD_EXCEPTION_COMMON_IDLE(trap, label, hdlr)    \
 438         .align  7;                                      \
 439         .globl label##_common;                          \
 440 label##_common:                                         \
 441         EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN);      \
 442         FINISH_NAP;                                     \
 443         DISABLE_INTS;                                   \
 444         bl      .save_nvgprs;                           \
 445         addi    r3,r1,STACK_FRAME_OVERHEAD;             \
 446         bl      hdlr;                                   \
 447         b       .ret_from_except
 448
 449 #define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr)    \
 450         .align  7;                                      \
 451         .globl label##_common;                          \
 452 label##_common:                                         \
 453         EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN);      \
 454         FINISH_NAP;                                     \
 455         DISABLE_INTS;                                   \
 456         bl      .ppc64_runlatch_on;                     \
 457         addi    r3,r1,STACK_FRAME_OVERHEAD;             \
 458         bl      hdlr;                                   \
 459         b       .ret_from_except_lite
 460
 461 /*
 462  * When the idle code in power4_idle puts the CPU into NAP mode,
 463  * it has to do so in a loop, and relies on the external interrupt
 464  * and decrementer interrupt entry code to get it out of the loop.
 465  * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags
 466  * to signal that it is in the loop and needs help to get out.
 467  */
 468 #ifdef CONFIG_PPC_970_NAP
 469 #define FINISH_NAP                              \
 470 BEGIN_FTR_SECTION                               \
 471         clrrdi  r11,r1,THREAD_SHIFT;            \
 472         ld      r9,TI_LOCAL_FLAGS(r11);         \
 473         andi.   r10,r9,_TLF_NAPPING;            \
 474         bnel    power4_fixup_nap;               \
 475 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
 476 #else
 477 #define FINISH_NAP
 478 #endif
 479
 480 /*
 481  * Start of pSeries system interrupt routines
 482  */
 483         . = 0x100
 484         .globl __start_interrupts
 485 __start_interrupts:
 486
 487         STD_EXCEPTION_PSERIES(0x100, system_reset)
 488
 489         . = 0x200
 490 _machine_check_pSeries:
 491         HMT_MEDIUM
 492         mtspr   SPRN_SPRG1,r13          /* save r13 */
 493         EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
 494
 495         . = 0x300
 496         .globl data_access_pSeries
 497 data_access_pSeries:
 498         HMT_MEDIUM
 499         mtspr   SPRN_SPRG1,r13
 500 BEGIN_FTR_SECTION
 501         mtspr   SPRN_SPRG2,r12
 502         mfspr   r13,SPRN_DAR
 503         mfspr   r12,SPRN_DSISR
 504         srdi    r13,r13,60
 505         rlwimi  r13,r12,16,0x20
 506         mfcr    r12
 507         cmpwi   r13,0x2c
 508         beq     .do_stab_bolted_pSeries
 509         mtcrf   0x80,r12
 510         mfspr   r12,SPRN_SPRG2
 511 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
 512         EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
 513
 514         . = 0x380
 515         .globl data_access_slb_pSeries
 516 data_access_slb_pSeries:
 517         HMT_MEDIUM
 518         mtspr   SPRN_SPRG1,r13
 519         mfspr   r13,SPRN_SPRG3          /* get paca address into r13 */
 520         std     r3,PACA_EXSLB+EX_R3(r13)
 521         mfspr   r3,SPRN_DAR
 522         std     r9,PACA_EXSLB+EX_R9(r13)        /* save r9 - r12 */
 523         mfcr    r9
 524 #ifdef __DISABLED__
 525         /* Keep that around for when we re-implement dynamic VSIDs */
 526         cmpdi   r3,0
 527         bge     slb_miss_user_pseries
 528 #endif /* __DISABLED__ */
 529         std     r10,PACA_EXSLB+EX_R10(r13)
 530         std     r11,PACA_EXSLB+EX_R11(r13)
 531         std     r12,PACA_EXSLB+EX_R12(r13)
 532         mfspr   r10,SPRN_SPRG1
 533         std     r10,PACA_EXSLB+EX_R13(r13)
 534         mfspr   r12,SPRN_SRR1           /* and SRR1 */
 535         b       .slb_miss_realmode      /* Rel. branch works in real mode */
 536
 537         STD_EXCEPTION_PSERIES(0x400, instruction_access)
 538
 539         . = 0x480
 540         .globl instruction_access_slb_pSeries
 541 instruction_access_slb_pSeries:
 542         HMT_MEDIUM
 543         mtspr   SPRN_SPRG1,r13
 544         mfspr   r13,SPRN_SPRG3          /* get paca address into r13 */
 545         std     r3,PACA_EXSLB+EX_R3(r13)
 546         mfspr   r3,SPRN_SRR0            /* SRR0 is faulting address */
 547         std     r9,PACA_EXSLB+EX_R9(r13)        /* save r9 - r12 */
 548         mfcr    r9
 549 #ifdef __DISABLED__
 550         /* Keep that around for when we re-implement dynamic VSIDs */
 551         cmpdi   r3,0
 552         bge     slb_miss_user_pseries
 553 #endif /* __DISABLED__ */
 554         std     r10,PACA_EXSLB+EX_R10(r13)
 555         std     r11,PACA_EXSLB+EX_R11(r13)
 556         std     r12,PACA_EXSLB+EX_R12(r13)
 557         mfspr   r10,SPRN_SPRG1
 558         std     r10,PACA_EXSLB+EX_R13(r13)
 559         mfspr   r12,SPRN_SRR1           /* and SRR1 */
 560         b       .slb_miss_realmode      /* Rel. branch works in real mode */
 561
 562         MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt)
 563         STD_EXCEPTION_PSERIES(0x600, alignment)
 564         STD_EXCEPTION_PSERIES(0x700, program_check)
 565         STD_EXCEPTION_PSERIES(0x800, fp_unavailable)
 566         MASKABLE_EXCEPTION_PSERIES(0x900, decrementer)
 567         STD_EXCEPTION_PSERIES(0xa00, trap_0a)
 568         STD_EXCEPTION_PSERIES(0xb00, trap_0b)
 569
 570         . = 0xc00
 571         .globl  system_call_pSeries
 572 system_call_pSeries:
 573         HMT_MEDIUM
 574         mr      r9,r13
 575         mfmsr   r10
 576         mfspr   r13,SPRN_SPRG3
 577         mfspr   r11,SPRN_SRR0
 578         clrrdi  r12,r13,32
 579         oris    r12,r12,system_call_common@h
 580         ori     r12,r12,system_call_common@l
 581         mtspr   SPRN_SRR0,r12
 582         ori     r10,r10,MSR_IR|MSR_DR|MSR_RI
 583         mfspr   r12,SPRN_SRR1
 584         mtspr   SPRN_SRR1,r10
 585         rfid
 586         b       .       /* prevent speculative execution */
 587
 588         STD_EXCEPTION_PSERIES(0xd00, single_step)
 589         STD_EXCEPTION_PSERIES(0xe00, trap_0e)
 590
 591         /* We need to deal with the Altivec unavailable exception
 592          * here which is at 0xf20, thus in the middle of the
 593          * prolog code of the PerformanceMonitor one. A little
 594          * trickery is thus necessary
 595          */
 596         . = 0xf00
 597         b       performance_monitor_pSeries
 598
 599         STD_EXCEPTION_PSERIES(0xf20, altivec_unavailable)
 600
 601 #ifdef CONFIG_CBE_RAS
 602         HSTD_EXCEPTION_PSERIES(0x1200, cbe_system_error)
 603 #endif /* CONFIG_CBE_RAS */
 604         STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint)
 605 #ifdef CONFIG_CBE_RAS
 606         HSTD_EXCEPTION_PSERIES(0x1600, cbe_maintenance)
 607 #endif /* CONFIG_CBE_RAS */
 608         STD_EXCEPTION_PSERIES(0x1700, altivec_assist)
 609 #ifdef CONFIG_CBE_RAS
 610         HSTD_EXCEPTION_PSERIES(0x1800, cbe_thermal)
 611 #endif /* CONFIG_CBE_RAS */
 612
 613         . = 0x3000
 614
 615 /*** pSeries interrupt support ***/
 616
 617         /* moved from 0xf00 */
 618         MASKABLE_EXCEPTION_PSERIES(., performance_monitor)
 619
 620 /*
 621  * An interrupt came in while soft-disabled; clear EE in SRR1,
 622  * clear paca->hard_enabled and return.
 623  */
 624 masked_interrupt:
 625         stb     r10,PACAHARDIRQEN(r13)
 626         mtcrf   0x80,r9
 627         ld      r9,PACA_EXGEN+EX_R9(r13)
 628         mfspr   r10,SPRN_SRR1
 629         rldicl  r10,r10,48,1            /* clear MSR_EE */
 630         rotldi  r10,r10,16
 631         mtspr   SPRN_SRR1,r10
 632         ld      r10,PACA_EXGEN+EX_R10(r13)
 633         mfspr   r13,SPRN_SPRG1
 634         rfid
 635         b       .
 636
 637         .align  7
 638 _GLOBAL(do_stab_bolted_pSeries)
 639         mtcrf   0x80,r12
 640         mfspr   r12,SPRN_SPRG2
 641         EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
 642
 643 /*
 644  * We have some room here  we use that to put
 645  * the peries slb miss user trampoline code so it's reasonably
 646  * away from slb_miss_user_common to avoid problems with rfid
 647  *
 648  * This is used for when the SLB miss handler has to go virtual,
 649  * which doesn't happen for now anymore but will once we re-implement
 650  * dynamic VSIDs for shared page tables
 651  */
 652 #ifdef __DISABLED__
 653 slb_miss_user_pseries:
 654         std     r10,PACA_EXGEN+EX_R10(r13)
 655         std     r11,PACA_EXGEN+EX_R11(r13)
 656         std     r12,PACA_EXGEN+EX_R12(r13)
 657         mfspr   r10,SPRG1
 658         ld      r11,PACA_EXSLB+EX_R9(r13)
 659         ld      r12,PACA_EXSLB+EX_R3(r13)
 660         std     r10,PACA_EXGEN+EX_R13(r13)
 661         std     r11,PACA_EXGEN+EX_R9(r13)
 662         std     r12,PACA_EXGEN+EX_R3(r13)
 663         clrrdi  r12,r13,32
 664         mfmsr   r10
 665         mfspr   r11,SRR0                        /* save SRR0 */
 666         ori     r12,r12,slb_miss_user_common@l  /* virt addr of handler */
 667         ori     r10,r10,MSR_IR|MSR_DR|MSR_RI
 668         mtspr   SRR0,r12
 669         mfspr   r12,SRR1                        /* and SRR1 */
 670         mtspr   SRR1,r10
 671         rfid
 672         b       .                               /* prevent spec. execution */
 673 #endif /* __DISABLED__ */
 674
 675 /*
 676  * Vectors for the FWNMI option.  Share common code.
 677  */
 678         .globl system_reset_fwnmi
 679       .align 7
 680 system_reset_fwnmi:
 681         HMT_MEDIUM
 682         mtspr   SPRN_SPRG1,r13          /* save r13 */
 683         EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXGEN, system_reset_common)
 684
 685         .globl machine_check_fwnmi
 686       .align 7
 687 machine_check_fwnmi:
 688         HMT_MEDIUM
 689         mtspr   SPRN_SPRG1,r13          /* save r13 */
 690         EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXMC, machine_check_common)
 691
 692 #ifdef CONFIG_PPC_ISERIES
 693 /***  ISeries-LPAR interrupt handlers ***/
 694
 695         STD_EXCEPTION_ISERIES(0x200, machine_check, PACA_EXMC)
 696
 697         .globl data_access_iSeries
 698 data_access_iSeries:
 699         mtspr   SPRN_SPRG1,r13
 700 BEGIN_FTR_SECTION
 701         mtspr   SPRN_SPRG2,r12
 702         mfspr   r13,SPRN_DAR
 703         mfspr   r12,SPRN_DSISR
 704         srdi    r13,r13,60
 705         rlwimi  r13,r12,16,0x20
 706         mfcr    r12
 707         cmpwi   r13,0x2c
 708         beq     .do_stab_bolted_iSeries
 709         mtcrf   0x80,r12
 710         mfspr   r12,SPRN_SPRG2
 711 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
 712         EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN)
 713         EXCEPTION_PROLOG_ISERIES_2
 714         b       data_access_common
 715
 716 .do_stab_bolted_iSeries:
 717         mtcrf   0x80,r12
 718         mfspr   r12,SPRN_SPRG2
 719         EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
 720         EXCEPTION_PROLOG_ISERIES_2
 721         b       .do_stab_bolted
 722
 723         .globl  data_access_slb_iSeries
 724 data_access_slb_iSeries:
 725         mtspr   SPRN_SPRG1,r13          /* save r13 */
 726         mfspr   r13,SPRN_SPRG3          /* get paca address into r13 */
 727         std     r3,PACA_EXSLB+EX_R3(r13)
 728         mfspr   r3,SPRN_DAR
 729         std     r9,PACA_EXSLB+EX_R9(r13)
 730         mfcr    r9
 731 #ifdef __DISABLED__
 732         cmpdi   r3,0
 733         bge     slb_miss_user_iseries
 734 #endif
 735         std     r10,PACA_EXSLB+EX_R10(r13)
 736         std     r11,PACA_EXSLB+EX_R11(r13)
 737         std     r12,PACA_EXSLB+EX_R12(r13)
 738         mfspr   r10,SPRN_SPRG1
 739         std     r10,PACA_EXSLB+EX_R13(r13)
 740         ld      r12,PACALPPACAPTR(r13)
 741         ld      r12,LPPACASRR1(r12)
 742         b       .slb_miss_realmode
 743
 744         STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN)
 745
 746         .globl  instruction_access_slb_iSeries
 747 instruction_access_slb_iSeries:
 748         mtspr   SPRN_SPRG1,r13          /* save r13 */
 749         mfspr   r13,SPRN_SPRG3          /* get paca address into r13 */
 750         std     r3,PACA_EXSLB+EX_R3(r13)
 751         ld      r3,PACALPPACAPTR(r13)
 752         ld      r3,LPPACASRR0(r3)       /* get SRR0 value */
 753         std     r9,PACA_EXSLB+EX_R9(r13)
 754         mfcr    r9
 755 #ifdef __DISABLED__
 756         cmpdi   r3,0
 757         bge     .slb_miss_user_iseries
 758 #endif
 759         std     r10,PACA_EXSLB+EX_R10(r13)
 760         std     r11,PACA_EXSLB+EX_R11(r13)
 761         std     r12,PACA_EXSLB+EX_R12(r13)
 762         mfspr   r10,SPRN_SPRG1
 763         std     r10,PACA_EXSLB+EX_R13(r13)
 764         ld      r12,PACALPPACAPTR(r13)
 765         ld      r12,LPPACASRR1(r12)
 766         b       .slb_miss_realmode
 767
 768 #ifdef __DISABLED__
 769 slb_miss_user_iseries:
 770         std     r10,PACA_EXGEN+EX_R10(r13)
 771         std     r11,PACA_EXGEN+EX_R11(r13)
 772         std     r12,PACA_EXGEN+EX_R12(r13)
 773         mfspr   r10,SPRG1
 774         ld      r11,PACA_EXSLB+EX_R9(r13)
 775         ld      r12,PACA_EXSLB+EX_R3(r13)
 776         std     r10,PACA_EXGEN+EX_R13(r13)
 777         std     r11,PACA_EXGEN+EX_R9(r13)
 778         std     r12,PACA_EXGEN+EX_R3(r13)
 779         EXCEPTION_PROLOG_ISERIES_2
 780         b       slb_miss_user_common
 781 #endif
 782
 783         MASKABLE_EXCEPTION_ISERIES(0x500, hardware_interrupt)
 784         STD_EXCEPTION_ISERIES(0x600, alignment, PACA_EXGEN)
 785         STD_EXCEPTION_ISERIES(0x700, program_check, PACA_EXGEN)
 786         STD_EXCEPTION_ISERIES(0x800, fp_unavailable, PACA_EXGEN)
 787         MASKABLE_EXCEPTION_ISERIES(0x900, decrementer)
 788         STD_EXCEPTION_ISERIES(0xa00, trap_0a, PACA_EXGEN)
 789         STD_EXCEPTION_ISERIES(0xb00, trap_0b, PACA_EXGEN)
 790
 791         .globl  system_call_iSeries
 792 system_call_iSeries:
 793         mr      r9,r13
 794         mfspr   r13,SPRN_SPRG3
 795         EXCEPTION_PROLOG_ISERIES_2
 796         b       system_call_common
 797
 798         STD_EXCEPTION_ISERIES( 0xd00, single_step, PACA_EXGEN)
 799         STD_EXCEPTION_ISERIES( 0xe00, trap_0e, PACA_EXGEN)
 800         STD_EXCEPTION_ISERIES( 0xf00, performance_monitor, PACA_EXGEN)
 801
 802         .globl system_reset_iSeries
 803 system_reset_iSeries:
 804         mfspr   r13,SPRN_SPRG3          /* Get paca address */
 805         mfmsr   r24
 806         ori     r24,r24,MSR_RI
 807         mtmsrd  r24                     /* RI on */
 808         lhz     r24,PACAPACAINDEX(r13)  /* Get processor # */
 809         cmpwi   0,r24,0                 /* Are we processor 0? */
 810         beq     .__start_initialization_iSeries /* Start up the first processor */
 811         mfspr   r4,SPRN_CTRLF
 812         li      r5,CTRL_RUNLATCH        /* Turn off the run light */
 813         andc    r4,r4,r5
 814         mtspr   SPRN_CTRLT,r4
 815
 816 1:
 817         HMT_LOW
 818 #ifdef CONFIG_SMP
 819         lbz     r23,PACAPROCSTART(r13)  /* Test if this processor
 820                                          * should start */
 821         sync
 822         LOAD_REG_IMMEDIATE(r3,current_set)
 823         sldi    r28,r24,3               /* get current_set[cpu#] */
 824         ldx     r3,r3,r28
 825         addi    r1,r3,THREAD_SIZE
 826         subi    r1,r1,STACK_FRAME_OVERHEAD
 827
 828         cmpwi   0,r23,0
 829         beq     iSeries_secondary_smp_loop      /* Loop until told to go */
 830         bne     .__secondary_start              /* Loop until told to go */
 831 iSeries_secondary_smp_loop:
 832         /* Let the Hypervisor know we are alive */
 833         /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
 834         lis     r3,0x8002
 835         rldicr  r3,r3,32,15             /* r0 = (r3 << 32) & 0xffff000000000000 */
 836 #else /* CONFIG_SMP */
 837         /* Yield the processor.  This is required for non-SMP kernels
 838                 which are running on multi-threaded machines. */
 839         lis     r3,0x8000
 840         rldicr  r3,r3,32,15             /* r3 = (r3 << 32) & 0xffff000000000000 */
 841         addi    r3,r3,18                /* r3 = 0x8000000000000012 which is "yield" */
 842         li      r4,0                    /* "yield timed" */
 843         li      r5,-1                   /* "yield forever" */
 844 #endif /* CONFIG_SMP */
 845         li      r0,-1                   /* r0=-1 indicates a Hypervisor call */
 846         sc                              /* Invoke the hypervisor via a system call */
 847         mfspr   r13,SPRN_SPRG3          /* Put r13 back ???? */
 848         b       1b                      /* If SMP not configured, secondaries
 849                                          * loop forever */
 850
 851         .globl decrementer_iSeries_masked
 852 decrementer_iSeries_masked:
 853         /* We may not have a valid TOC pointer in here. */
 854         li      r11,1
 855         ld      r12,PACALPPACAPTR(r13)
 856         stb     r11,LPPACADECRINT(r12)
 857         LOAD_REG_IMMEDIATE(r12, tb_ticks_per_jiffy)
 858         lwz     r12,0(r12)
 859         mtspr   SPRN_DEC,r12
 860         /* fall through */
 861
 862         .globl hardware_interrupt_iSeries_masked
 863 hardware_interrupt_iSeries_masked:
 864         mtcrf   0x80,r9         /* Restore regs */
 865         ld      r12,PACALPPACAPTR(r13)
 866         ld      r11,LPPACASRR0(r12)
 867         ld      r12,LPPACASRR1(r12)
 868         mtspr   SPRN_SRR0,r11
 869         mtspr   SPRN_SRR1,r12
 870         ld      r9,PACA_EXGEN+EX_R9(r13)
 871         ld      r10,PACA_EXGEN+EX_R10(r13)
 872         ld      r11,PACA_EXGEN+EX_R11(r13)
 873         ld      r12,PACA_EXGEN+EX_R12(r13)
 874         ld      r13,PACA_EXGEN+EX_R13(r13)
 875         rfid
 876         b       .       /* prevent speculative execution */
 877 #endif /* CONFIG_PPC_ISERIES */
 878
 879 /*** Common interrupt handlers ***/
 880
 881         STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception)
 882
 883         /*
 884          * Machine check is different because we use a different
 885          * save area: PACA_EXMC instead of PACA_EXGEN.
 886          */
 887         .align  7
 888         .globl machine_check_common
 889 machine_check_common:
 890         EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
 891         FINISH_NAP
 892         DISABLE_INTS
 893         bl      .save_nvgprs
 894         addi    r3,r1,STACK_FRAME_OVERHEAD
 895         bl      .machine_check_exception
 896         b       .ret_from_except
 897
 898         STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt)
 899         STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception)
 900         STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
 901         STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
 902         STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
 903         STD_EXCEPTION_COMMON_IDLE(0xf00, performance_monitor, .performance_monitor_exception)
 904         STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
 905 #ifdef CONFIG_ALTIVEC
 906         STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
 907 #else
 908         STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception)
 909 #endif
 910 #ifdef CONFIG_CBE_RAS
 911         STD_EXCEPTION_COMMON(0x1200, cbe_system_error, .cbe_system_error_exception)
 912         STD_EXCEPTION_COMMON(0x1600, cbe_maintenance, .cbe_maintenance_exception)
 913         STD_EXCEPTION_COMMON(0x1800, cbe_thermal, .cbe_thermal_exception)
 914 #endif /* CONFIG_CBE_RAS */
 915
 916 /*
 917  * Here we have detected that the kernel stack pointer is bad.
 918  * R9 contains the saved CR, r13 points to the paca,
 919  * r10 contains the (bad) kernel stack pointer,
 920  * r11 and r12 contain the saved SRR0 and SRR1.
 921  * We switch to using an emergency stack, save the registers there,
 922  * and call kernel_bad_stack(), which panics.
 923  */
 924 bad_stack:
 925         ld      r1,PACAEMERGSP(r13)
 926         subi    r1,r1,64+INT_FRAME_SIZE
 927         std     r9,_CCR(r1)
 928         std     r10,GPR1(r1)
 929         std     r11,_NIP(r1)
 930         std     r12,_MSR(r1)
 931         mfspr   r11,SPRN_DAR
 932         mfspr   r12,SPRN_DSISR
 933         std     r11,_DAR(r1)
 934         std     r12,_DSISR(r1)
 935         mflr    r10
 936         mfctr   r11
 937         mfxer   r12
 938         std     r10,_LINK(r1)
 939         std     r11,_CTR(r1)
 940         std     r12,_XER(r1)
 941         SAVE_GPR(0,r1)
 942         SAVE_GPR(2,r1)
 943         SAVE_4GPRS(3,r1)
 944         SAVE_2GPRS(7,r1)
 945         SAVE_10GPRS(12,r1)
 946         SAVE_10GPRS(22,r1)
 947         addi    r11,r1,INT_FRAME_SIZE
 948         std     r11,0(r1)
 949         li      r12,0
 950         std     r12,0(r11)
 951         ld      r2,PACATOC(r13)
 952 1:      addi    r3,r1,STACK_FRAME_OVERHEAD
 953         bl      .kernel_bad_stack
 954         b       1b
 955
 956 /*
 957  * Return from an exception with minimal checks.
 958  * The caller is assumed to have done EXCEPTION_PROLOG_COMMON.
 959  * If interrupts have been enabled, or anything has been
 960  * done that might have changed the scheduling status of
 961  * any task or sent any task a signal, you should use
 962  * ret_from_except or ret_from_except_lite instead of this.
 963  */
 964 fast_exc_return_irq:                    /* restores irq state too */
 965         ld      r3,SOFTE(r1)
 966         ld      r12,_MSR(r1)
 967         stb     r3,PACASOFTIRQEN(r13)   /* restore paca->soft_enabled */
 968         rldicl  r4,r12,49,63            /* get MSR_EE to LSB */
 969         stb     r4,PACAHARDIRQEN(r13)   /* restore paca->hard_enabled */
 970         b       1f
 971
 972         .globl  fast_exception_return
 973 fast_exception_return:
 974         ld      r12,_MSR(r1)
 975 1:      ld      r11,_NIP(r1)
 976         andi.   r3,r12,MSR_RI           /* check if RI is set */
 977         beq-    unrecov_fer
 978
 979 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
 980         andi.   r3,r12,MSR_PR
 981         beq     2f
 982         ACCOUNT_CPU_USER_EXIT(r3, r4)
 983 2:
 984 #endif
 985
 986         ld      r3,_CCR(r1)
 987         ld      r4,_LINK(r1)
 988         ld      r5,_CTR(r1)
 989         ld      r6,_XER(r1)
 990         mtcr    r3
 991         mtlr    r4
 992         mtctr   r5
 993         mtxer   r6
 994         REST_GPR(0, r1)
 995         REST_8GPRS(2, r1)
 996
 997         mfmsr   r10
 998         rldicl  r10,r10,48,1            /* clear EE */
 999         rldicr  r10,r10,16,61           /* clear RI (LE is 0 already) */
1000         mtmsrd  r10,1
1001
1002         mtspr   SPRN_SRR1,r12
1003         mtspr   SPRN_SRR0,r11
1004         REST_4GPRS(10, r1)
1005         ld      r1,GPR1(r1)
1006         rfid
1007         b       .       /* prevent speculative execution */
1008
1009 unrecov_fer:
1010         bl      .save_nvgprs
1011 1:      addi    r3,r1,STACK_FRAME_OVERHEAD
1012         bl      .unrecoverable_exception
1013         b       1b
1014
1015 /*
1016  * Here r13 points to the paca, r9 contains the saved CR,
1017  * SRR0 and SRR1 are saved in r11 and r12,
1018  * r9 - r13 are saved in paca->exgen.
1019  */
1020         .align  7
1021         .globl data_access_common
1022 data_access_common:
1023         mfspr   r10,SPRN_DAR
1024         std     r10,PACA_EXGEN+EX_DAR(r13)
1025         mfspr   r10,SPRN_DSISR
1026         stw     r10,PACA_EXGEN+EX_DSISR(r13)
1027         EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
1028         ld      r3,PACA_EXGEN+EX_DAR(r13)
1029         lwz     r4,PACA_EXGEN+EX_DSISR(r13)
1030         li      r5,0x300
1031         b       .do_hash_page           /* Try to handle as hpte fault */
1032
1033         .align  7
1034         .globl instruction_access_common
1035 instruction_access_common:
1036         EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
1037         ld      r3,_NIP(r1)
1038         andis.  r4,r12,0x5820
1039         li      r5,0x400
1040         b       .do_hash_page           /* Try to handle as hpte fault */
1041
1042 /*
1043  * Here is the common SLB miss user that is used when going to virtual
1044  * mode for SLB misses, that is currently not used
1045  */
1046 #ifdef __DISABLED__
1047         .align  7
1048         .globl  slb_miss_user_common
1049 slb_miss_user_common:
1050         mflr    r10
1051         std     r3,PACA_EXGEN+EX_DAR(r13)
1052         stw     r9,PACA_EXGEN+EX_CCR(r13)
1053         std     r10,PACA_EXGEN+EX_LR(r13)
1054         std     r11,PACA_EXGEN+EX_SRR0(r13)
1055         bl      .slb_allocate_user
1056
1057         ld      r10,PACA_EXGEN+EX_LR(r13)
1058         ld      r3,PACA_EXGEN+EX_R3(r13)
1059         lwz     r9,PACA_EXGEN+EX_CCR(r13)
1060         ld      r11,PACA_EXGEN+EX_SRR0(r13)
1061         mtlr    r10
1062         beq-    slb_miss_fault
1063
1064         andi.   r10,r12,MSR_RI          /* check for unrecoverable exception */
1065         beq-    unrecov_user_slb
1066         mfmsr   r10
1067
1068 .machine push
1069 .machine "power4"
1070         mtcrf   0x80,r9
1071 .machine pop
1072
1073         clrrdi  r10,r10,2               /* clear RI before setting SRR0/1 */
1074         mtmsrd  r10,1
1075
1076         mtspr   SRR0,r11
1077         mtspr   SRR1,r12
1078
1079         ld      r9,PACA_EXGEN+EX_R9(r13)
1080         ld      r10,PACA_EXGEN+EX_R10(r13)
1081         ld      r11,PACA_EXGEN+EX_R11(r13)
1082         ld      r12,PACA_EXGEN+EX_R12(r13)
1083         ld      r13,PACA_EXGEN+EX_R13(r13)
1084         rfid
1085         b       .
1086
1087 slb_miss_fault:
1088         EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN)
1089         ld      r4,PACA_EXGEN+EX_DAR(r13)
1090         li      r5,0
1091         std     r4,_DAR(r1)
1092         std     r5,_DSISR(r1)
1093         b       .handle_page_fault
1094
1095 unrecov_user_slb:
1096         EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN)
1097         DISABLE_INTS
1098         bl      .save_nvgprs
1099 1:      addi    r3,r1,STACK_FRAME_OVERHEAD
1100         bl      .unrecoverable_exception
1101         b       1b
1102
1103 #endif /* __DISABLED__ */
1104
1105
1106 /*
1107  * r13 points to the PACA, r9 contains the saved CR,
1108  * r12 contain the saved SRR1, SRR0 is still ready for return
1109  * r3 has the faulting address
1110  * r9 - r13 are saved in paca->exslb.
1111  * r3 is saved in paca->slb_r3
1112  * We assume we aren't going to take any exceptions during this procedure.
1113  */
1114 _GLOBAL(slb_miss_realmode)
1115         mflr    r10
1116
1117         stw     r9,PACA_EXSLB+EX_CCR(r13)       /* save CR in exc. frame */
1118         std     r10,PACA_EXSLB+EX_LR(r13)       /* save LR */
1119
1120         bl      .slb_allocate_realmode
1121
1122         /* All done -- return from exception. */
1123
1124         ld      r10,PACA_EXSLB+EX_LR(r13)
1125         ld      r3,PACA_EXSLB+EX_R3(r13)
1126         lwz     r9,PACA_EXSLB+EX_CCR(r13)       /* get saved CR */
1127 #ifdef CONFIG_PPC_ISERIES
1128 BEGIN_FW_FTR_SECTION
1129         ld      r11,PACALPPACAPTR(r13)
1130         ld      r11,LPPACASRR0(r11)             /* get SRR0 value */
1131 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1132 #endif /* CONFIG_PPC_ISERIES */
1133
1134         mtlr    r10
1135
1136         andi.   r10,r12,MSR_RI  /* check for unrecoverable exception */
1137         beq-    unrecov_slb
1138
1139 .machine        push
1140 .machine        "power4"
1141         mtcrf   0x80,r9
1142         mtcrf   0x01,r9         /* slb_allocate uses cr0 and cr7 */
1143 .machine        pop
1144
1145 #ifdef CONFIG_PPC_ISERIES
1146 BEGIN_FW_FTR_SECTION
1147         mtspr   SPRN_SRR0,r11
1148         mtspr   SPRN_SRR1,r12
1149 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1150 #endif /* CONFIG_PPC_ISERIES */
1151         ld      r9,PACA_EXSLB+EX_R9(r13)
1152         ld      r10,PACA_EXSLB+EX_R10(r13)
1153         ld      r11,PACA_EXSLB+EX_R11(r13)
1154         ld      r12,PACA_EXSLB+EX_R12(r13)
1155         ld      r13,PACA_EXSLB+EX_R13(r13)
1156         rfid
1157         b       .       /* prevent speculative execution */
1158
1159 unrecov_slb:
1160         EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
1161         DISABLE_INTS
1162         bl      .save_nvgprs
1163 1:      addi    r3,r1,STACK_FRAME_OVERHEAD
1164         bl      .unrecoverable_exception
1165         b       1b
1166
1167         .align  7
1168         .globl hardware_interrupt_common
1169         .globl hardware_interrupt_entry
1170 hardware_interrupt_common:
1171         EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN)
1172         FINISH_NAP
1173 hardware_interrupt_entry:
1174         DISABLE_INTS
1175         bl      .ppc64_runlatch_on
1176         addi    r3,r1,STACK_FRAME_OVERHEAD
1177         bl      .do_IRQ
1178         b       .ret_from_except_lite
1179
1180 #ifdef CONFIG_PPC_970_NAP
1181 power4_fixup_nap:
1182         andc    r9,r9,r10
1183         std     r9,TI_LOCAL_FLAGS(r11)
1184         ld      r10,_LINK(r1)           /* make idle task do the */
1185         std     r10,_NIP(r1)            /* equivalent of a blr */
1186         blr
1187 #endif
1188
1189         .align  7
1190         .globl alignment_common
1191 alignment_common:
1192         mfspr   r10,SPRN_DAR
1193         std     r10,PACA_EXGEN+EX_DAR(r13)
1194         mfspr   r10,SPRN_DSISR
1195         stw     r10,PACA_EXGEN+EX_DSISR(r13)
1196         EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
1197         ld      r3,PACA_EXGEN+EX_DAR(r13)
1198         lwz     r4,PACA_EXGEN+EX_DSISR(r13)
1199         std     r3,_DAR(r1)
1200         std     r4,_DSISR(r1)
1201         bl      .save_nvgprs
1202         addi    r3,r1,STACK_FRAME_OVERHEAD
1203         ENABLE_INTS
1204         bl      .alignment_exception
1205         b       .ret_from_except
1206
1207         .align  7
1208         .globl program_check_common
1209 program_check_common:
1210         EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
1211         bl      .save_nvgprs
1212         addi    r3,r1,STACK_FRAME_OVERHEAD
1213         ENABLE_INTS
1214         bl      .program_check_exception
1215         b       .ret_from_except
1216
1217         .align  7
1218         .globl fp_unavailable_common
1219 fp_unavailable_common:
1220         EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
1221         bne     .load_up_fpu            /* if from user, just load it up */
1222         bl      .save_nvgprs
1223         addi    r3,r1,STACK_FRAME_OVERHEAD
1224         ENABLE_INTS
1225         bl      .kernel_fp_unavailable_exception
1226         BUG_OPCODE
1227
1228         .align  7
1229         .globl altivec_unavailable_common
1230 altivec_unavailable_common:
1231         EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
1232 #ifdef CONFIG_ALTIVEC
1233 BEGIN_FTR_SECTION
1234         bne     .load_up_altivec        /* if from user, just load it up */
1235 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1236 #endif
1237         bl      .save_nvgprs
1238         addi    r3,r1,STACK_FRAME_OVERHEAD
1239         ENABLE_INTS
1240         bl      .altivec_unavailable_exception
1241         b       .ret_from_except
1242
1243 #ifdef CONFIG_ALTIVEC
1244 /*
1245  * load_up_altivec(unused, unused, tsk)
1246  * Disable VMX for the task which had it previously,
1247  * and save its vector registers in its thread_struct.
1248  * Enables the VMX for use in the kernel on return.
1249  * On SMP we know the VMX is free, since we give it up every
1250  * switch (ie, no lazy save of the vector registers).
1251  * On entry: r13 == 'current' && last_task_used_altivec != 'current'
1252  */
1253 _STATIC(load_up_altivec)
1254         mfmsr   r5                      /* grab the current MSR */
1255         oris    r5,r5,MSR_VEC@h
1256         mtmsrd  r5                      /* enable use of VMX now */
1257         isync
1258
1259 /*
1260  * For SMP, we don't do lazy VMX switching because it just gets too
1261  * horrendously complex, especially when a task switches from one CPU
1262  * to another.  Instead we call giveup_altvec in switch_to.
1263  * VRSAVE isn't dealt with here, that is done in the normal context
1264  * switch code. Note that we could rely on vrsave value to eventually
1265  * avoid saving all of the VREGs here...
1266  */
1267 #ifndef CONFIG_SMP
1268         ld      r3,last_task_used_altivec@got(r2)
1269         ld      r4,0(r3)
1270         cmpdi   0,r4,0
1271         beq     1f
1272         /* Save VMX state to last_task_used_altivec's THREAD struct */
1273         addi    r4,r4,THREAD
1274         SAVE_32VRS(0,r5,r4)
1275         mfvscr  vr0
1276         li      r10,THREAD_VSCR
1277         stvx    vr0,r10,r4
1278         /* Disable VMX for last_task_used_altivec */
1279         ld      r5,PT_REGS(r4)
1280         ld      r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1281         lis     r6,MSR_VEC@h
1282         andc    r4,r4,r6
1283         std     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1284 1:
1285 #endif /* CONFIG_SMP */
1286         /* Hack: if we get an altivec unavailable trap with VRSAVE
1287          * set to all zeros, we assume this is a broken application
1288          * that fails to set it properly, and thus we switch it to
1289          * all 1's
1290          */
1291         mfspr   r4,SPRN_VRSAVE
1292         cmpdi   0,r4,0
1293         bne+    1f
1294         li      r4,-1
1295         mtspr   SPRN_VRSAVE,r4
1296 1:
1297         /* enable use of VMX after return */
1298         ld      r4,PACACURRENT(r13)
1299         addi    r5,r4,THREAD            /* Get THREAD */
1300         oris    r12,r12,MSR_VEC@h
1301         std     r12,_MSR(r1)
1302         li      r4,1
1303         li      r10,THREAD_VSCR
1304         stw     r4,THREAD_USED_VR(r5)
1305         lvx     vr0,r10,r5
1306         mtvscr  vr0
1307         REST_32VRS(0,r4,r5)
1308 #ifndef CONFIG_SMP
1309         /* Update last_task_used_math to 'current' */
1310         subi    r4,r5,THREAD            /* Back to 'current' */
1311         std     r4,0(r3)
1312 #endif /* CONFIG_SMP */
1313         /* restore registers and return */
1314         b       fast_exception_return
1315 #endif /* CONFIG_ALTIVEC */
1316
1317 /*
1318  * Hash table stuff
1319  */
1320         .align  7
1321 _GLOBAL(do_hash_page)
1322         std     r3,_DAR(r1)
1323         std     r4,_DSISR(r1)
1324
1325         andis.  r0,r4,0xa450            /* weird error? */
1326         bne-    .handle_page_fault      /* if not, try to insert a HPTE */
1327 BEGIN_FTR_SECTION
1328         andis.  r0,r4,0x0020            /* Is it a segment table fault? */
1329         bne-    .do_ste_alloc           /* If so handle it */
1330 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
1331
1332         /*
1333          * We need to set the _PAGE_USER bit if MSR_PR is set or if we are
1334          * accessing a userspace segment (even from the kernel). We assume
1335          * kernel addresses always have the high bit set.
1336          */
1337         rlwinm  r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */
1338         rotldi  r0,r3,15                /* Move high bit into MSR_PR posn */
1339         orc     r0,r12,r0               /* MSR_PR | ~high_bit */
1340         rlwimi  r4,r0,32-13,30,30       /* becomes _PAGE_USER access bit */
1341         ori     r4,r4,1                 /* add _PAGE_PRESENT */
1342         rlwimi  r4,r5,22+2,31-2,31-2    /* Set _PAGE_EXEC if trap is 0x400 */
1343
1344         /*
1345          * On iSeries, we soft-disable interrupts here, then
1346          * hard-enable interrupts so that the hash_page code can spin on
1347          * the hash_table_lock without problems on a shared processor.
1348          */
1349         DISABLE_INTS
1350
1351         /*
1352          * r3 contains the faulting address
1353          * r4 contains the required access permissions
1354          * r5 contains the trap number
1355          *
1356          * at return r3 = 0 for success
1357          */
1358         bl      .hash_page              /* build HPTE if possible */
1359         cmpdi   r3,0                    /* see if hash_page succeeded */
1360
1361 #ifdef DO_SOFT_DISABLE
1362 BEGIN_FW_FTR_SECTION
1363         /*
1364          * If we had interrupts soft-enabled at the point where the
1365          * DSI/ISI occurred, and an interrupt came in during hash_page,
1366          * handle it now.
1367          * We jump to ret_from_except_lite rather than fast_exception_return
1368          * because ret_from_except_lite will check for and handle pending
1369          * interrupts if necessary.
1370          */
1371         beq     .ret_from_except_lite
1372 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1373 #endif
1374 BEGIN_FW_FTR_SECTION
1375         /*
1376          * Here we have interrupts hard-disabled, so it is sufficient
1377          * to restore paca->{soft,hard}_enable and get out.
1378          */
1379         beq     fast_exc_return_irq     /* Return from exception on success */
1380 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
1381
1382         /* For a hash failure, we don't bother re-enabling interrupts */
1383         ble-    12f
1384
1385         /*
1386          * hash_page couldn't handle it, set soft interrupt enable back
1387          * to what it was before the trap.  Note that .local_irq_restore
1388          * handles any interrupts pending at this point.
1389          */
1390         ld      r3,SOFTE(r1)
1391         bl      .local_irq_restore
1392         b       11f
1393
1394 /* Here we have a page fault that hash_page can't handle. */
1395 _GLOBAL(handle_page_fault)
1396         ENABLE_INTS
1397 11:     ld      r4,_DAR(r1)
1398         ld      r5,_DSISR(r1)
1399         addi    r3,r1,STACK_FRAME_OVERHEAD
1400         bl      .do_page_fault
1401         cmpdi   r3,0
1402         beq+    .ret_from_except_lite
1403         bl      .save_nvgprs
1404         mr      r5,r3
1405         addi    r3,r1,STACK_FRAME_OVERHEAD
1406         lwz     r4,_DAR(r1)
1407         bl      .bad_page_fault
1408         b       .ret_from_except
1409
1410 /* We have a page fault that hash_page could handle but HV refused
1411  * the PTE insertion
1412  */
1413 12:     bl      .save_nvgprs
1414         addi    r3,r1,STACK_FRAME_OVERHEAD
1415         lwz     r4,_DAR(r1)
1416         bl      .low_hash_fault
1417         b       .ret_from_except
1418
1419         /* here we have a segment miss */
1420 _GLOBAL(do_ste_alloc)
1421         bl      .ste_allocate           /* try to insert stab entry */
1422         cmpdi   r3,0
1423         beq+    fast_exception_return
1424         b       .handle_page_fault
1425
1426 /*
1427  * r13 points to the PACA, r9 contains the saved CR,
1428  * r11 and r12 contain the saved SRR0 and SRR1.
1429  * r9 - r13 are saved in paca->exslb.
1430  * We assume we aren't going to take any exceptions during this procedure.
1431  * We assume (DAR >> 60) == 0xc.
1432  */
1433         .align  7
1434 _GLOBAL(do_stab_bolted)
1435         stw     r9,PACA_EXSLB+EX_CCR(r13)       /* save CR in exc. frame */
1436         std     r11,PACA_EXSLB+EX_SRR0(r13)     /* save SRR0 in exc. frame */
1437
1438         /* Hash to the primary group */
1439         ld      r10,PACASTABVIRT(r13)
1440         mfspr   r11,SPRN_DAR
1441         srdi    r11,r11,28
1442         rldimi  r10,r11,7,52    /* r10 = first ste of the group */
1443
1444         /* Calculate VSID */
1445         /* This is a kernel address, so protovsid = ESID */
1446         ASM_VSID_SCRAMBLE(r11, r9)
1447         rldic   r9,r11,12,16    /* r9 = vsid << 12 */
1448
1449         /* Search the primary group for a free entry */
1450 1:      ld      r11,0(r10)      /* Test valid bit of the current ste    */
1451         andi.   r11,r11,0x80
1452         beq     2f
1453         addi    r10,r10,16
1454         andi.   r11,r10,0x70
1455         bne     1b
1456
1457         /* Stick for only searching the primary group for now.          */
1458         /* At least for now, we use a very simple random castout scheme */
1459         /* Use the TB as a random number ;  OR in 1 to avoid entry 0    */
1460         mftb    r11
1461         rldic   r11,r11,4,57    /* r11 = (r11 << 4) & 0x70 */
1462         ori     r11,r11,0x10
1463
1464         /* r10 currently points to an ste one past the group of interest */
1465         /* make it point to the randomly selected entry                 */
1466         subi    r10,r10,128
1467         or      r10,r10,r11     /* r10 is the entry to invalidate       */
1468
1469         isync                   /* mark the entry invalid               */
1470         ld      r11,0(r10)
1471         rldicl  r11,r11,56,1    /* clear the valid bit */
1472         rotldi  r11,r11,8
1473         std     r11,0(r10)
1474         sync
1475
1476         clrrdi  r11,r11,28      /* Get the esid part of the ste         */
1477         slbie   r11
1478
1479 2:      std     r9,8(r10)       /* Store the vsid part of the ste       */
1480         eieio
1481
1482         mfspr   r11,SPRN_DAR            /* Get the new esid                     */
1483         clrrdi  r11,r11,28      /* Permits a full 32b of ESID           */
1484         ori     r11,r11,0x90    /* Turn on valid and kp                 */
1485         std     r11,0(r10)      /* Put new entry back into the stab     */
1486
1487         sync
1488
1489         /* All done -- return from exception. */
1490         lwz     r9,PACA_EXSLB+EX_CCR(r13)       /* get saved CR */
1491         ld      r11,PACA_EXSLB+EX_SRR0(r13)     /* get saved SRR0 */
1492
1493         andi.   r10,r12,MSR_RI
1494         beq-    unrecov_slb
1495
1496         mtcrf   0x80,r9                 /* restore CR */
1497
1498         mfmsr   r10
1499         clrrdi  r10,r10,2
1500         mtmsrd  r10,1
1501
1502         mtspr   SPRN_SRR0,r11
1503         mtspr   SPRN_SRR1,r12
1504         ld      r9,PACA_EXSLB+EX_R9(r13)
1505         ld      r10,PACA_EXSLB+EX_R10(r13)
1506         ld      r11,PACA_EXSLB+EX_R11(r13)
1507         ld      r12,PACA_EXSLB+EX_R12(r13)
1508         ld      r13,PACA_EXSLB+EX_R13(r13)
1509         rfid
1510         b       .       /* prevent speculative execution */
1511
1512 /*
1513  * Space for CPU0's segment table.
1514  *
1515  * On iSeries, the hypervisor must fill in at least one entry before
1516  * we get control (with relocate on).  The address is give to the hv
1517  * as a page number (see xLparMap in lpardata.c), so this must be at a
1518  * fixed address (the linker can't compute (u64)&initial_stab >>
1519  * PAGE_SHIFT).
1520  */
1521         . = STAB0_OFFSET        /* 0x6000 */
1522         .globl initial_stab
1523 initial_stab:
1524         .space  4096
1525
1526 /*
1527  * Data area reserved for FWNMI option.
1528  * This address (0x7000) is fixed by the RPA.
1529  */
1530         .= 0x7000
1531         .globl fwnmi_data_area
1532 fwnmi_data_area:
1533
1534         /* iSeries does not use the FWNMI stuff, so it is safe to put
1535          * this here, even if we later allow kernels that will boot on
1536          * both pSeries and iSeries */
1537 #ifdef CONFIG_PPC_ISERIES
1538         . = LPARMAP_PHYS
1539 #include "lparmap.s"
1540 /*
1541  * This ".text" is here for old compilers that generate a trailing
1542  * .note section when compiling .c files to .s
1543  */
1544         .text
1545 #endif /* CONFIG_PPC_ISERIES */
1546
1547         . = 0x8000
1548
1549 /*
1550  * On pSeries and most other platforms, secondary processors spin
1551  * in the following code.
1552  * At entry, r3 = this processor's number (physical cpu id)
1553  */
1554 _GLOBAL(generic_secondary_smp_init)
1555         mr      r24,r3
1556
1557         /* turn on 64-bit mode */
1558         bl      .enable_64b_mode
1559         isync
1560
1561         /* Set up a paca value for this processor. Since we have the
1562          * physical cpu id in r24, we need to search the pacas to find
1563          * which logical id maps to our physical one.
1564          */
1565         LOAD_REG_IMMEDIATE(r13, paca)   /* Get base vaddr of paca array  */
1566         li      r5,0                    /* logical cpu id                */
1567 1:      lhz     r6,PACAHWCPUID(r13)     /* Load HW procid from paca      */
1568         cmpw    r6,r24                  /* Compare to our id             */
1569         beq     2f
1570         addi    r13,r13,PACA_SIZE       /* Loop to next PACA on miss     */
1571         addi    r5,r5,1
1572         cmpwi   r5,NR_CPUS
1573         blt     1b
1574
1575         mr      r3,r24                  /* not found, copy phys to r3    */
1576         b       .kexec_wait             /* next kernel might do better   */
1577
1578 2:      mtspr   SPRN_SPRG3,r13          /* Save vaddr of paca in SPRG3   */
1579         /* From now on, r24 is expected to be logical cpuid */
1580         mr      r24,r5
1581 3:      HMT_LOW
1582         lbz     r23,PACAPROCSTART(r13)  /* Test if this processor should */
1583                                         /* start.                        */
1584         sync
1585
1586 #ifndef CONFIG_SMP
1587         b       3b                      /* Never go on non-SMP           */
1588 #else
1589         cmpwi   0,r23,0
1590         beq     3b                      /* Loop until told to go         */
1591
1592         /* See if we need to call a cpu state restore handler */
1593         LOAD_REG_IMMEDIATE(r23, cur_cpu_spec)
1594         ld      r23,0(r23)
1595         ld      r23,CPU_SPEC_RESTORE(r23)
1596         cmpdi   0,r23,0
1597         beq     4f
1598         ld      r23,0(r23)
1599         mtctr   r23
1600         bctrl
1601
1602 4:      /* Create a temp kernel stack for use before relocation is on.  */
1603         ld      r1,PACAEMERGSP(r13)
1604         subi    r1,r1,STACK_FRAME_OVERHEAD
1605
1606         b       .__secondary_start
1607 #endif
1608
1609 #ifdef CONFIG_PPC_ISERIES
1610 _STATIC(__start_initialization_iSeries)
1611         /* Clear out the BSS */
1612         LOAD_REG_IMMEDIATE(r11,__bss_stop)
1613         LOAD_REG_IMMEDIATE(r8,__bss_start)
1614         sub     r11,r11,r8              /* bss size                     */
1615         addi    r11,r11,7               /* round up to an even double word */
1616         rldicl. r11,r11,61,3            /* shift right by 3             */
1617         beq     4f
1618         addi    r8,r8,-8
1619         li      r0,0
1620         mtctr   r11                     /* zero this many doublewords   */
1621 3:      stdu    r0,8(r8)
1622         bdnz    3b
1623 4:
1624         LOAD_REG_IMMEDIATE(r1,init_thread_union)
1625         addi    r1,r1,THREAD_SIZE
1626         li      r0,0
1627         stdu    r0,-STACK_FRAME_OVERHEAD(r1)
1628
1629         LOAD_REG_IMMEDIATE(r3,cpu_specs)
1630         LOAD_REG_IMMEDIATE(r4,cur_cpu_spec)
1631         li      r5,0
1632         bl      .identify_cpu
1633
1634         LOAD_REG_IMMEDIATE(r2,__toc_start)
1635         addi    r2,r2,0x4000
1636         addi    r2,r2,0x4000
1637
1638         bl      .iSeries_early_setup
1639         bl      .early_setup
1640
1641         /* relocation is on at this point */
1642
1643         b       .start_here_common
1644 #endif /* CONFIG_PPC_ISERIES */
1645
1646 #ifdef CONFIG_PPC_MULTIPLATFORM
1647
1648 _STATIC(__mmu_off)
1649         mfmsr   r3
1650         andi.   r0,r3,MSR_IR|MSR_DR
1651         beqlr
1652         andc    r3,r3,r0
1653         mtspr   SPRN_SRR0,r4
1654         mtspr   SPRN_SRR1,r3
1655         sync
1656         rfid
1657         b       .       /* prevent speculative execution */
1658
1659
1660 /*
1661  * Here is our main kernel entry point. We support currently 2 kind of entries
1662  * depending on the value of r5.
1663  *
1664  *   r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
1665  *                 in r3...r7
1666  *
1667  *   r5 == NULL -> kexec style entry. r3 is a physical pointer to the
1668  *                 DT block, r4 is a physical pointer to the kernel itself
1669  *
1670  */
1671 _GLOBAL(__start_initialization_multiplatform)
1672 #ifdef CONFIG_PPC_MULTIPLATFORM
1673         /*
1674          * Are we booted from a PROM Of-type client-interface ?
1675          */
1676         cmpldi  cr0,r5,0
1677         bne     .__boot_from_prom               /* yes -> prom */
1678 #endif
1679
1680         /* Save parameters */
1681         mr      r31,r3
1682         mr      r30,r4
1683
1684         /* Make sure we are running in 64 bits mode */
1685         bl      .enable_64b_mode
1686
1687         /* Setup some critical 970 SPRs before switching MMU off */
1688         mfspr   r0,SPRN_PVR
1689         srwi    r0,r0,16
1690         cmpwi   r0,0x39         /* 970 */
1691         beq     1f
1692         cmpwi   r0,0x3c         /* 970FX */
1693         beq     1f
1694         cmpwi   r0,0x44         /* 970MP */
1695         bne     2f
1696 1:      bl      .__cpu_preinit_ppc970
1697 2:
1698
1699         /* Switch off MMU if not already */
1700         LOAD_REG_IMMEDIATE(r4, .__after_prom_start - KERNELBASE)
1701         add     r4,r4,r30
1702         bl      .__mmu_off
1703         b       .__after_prom_start
1704
1705 #ifdef CONFIG_PPC_MULTIPLATFORM
1706 _STATIC(__boot_from_prom)
1707         /* Save parameters */
1708         mr      r31,r3
1709         mr      r30,r4
1710         mr      r29,r5
1711         mr      r28,r6
1712         mr      r27,r7
1713
1714         /*
1715          * Align the stack to 16-byte boundary
1716          * Depending on the size and layout of the ELF sections in the initial
1717          * boot binary, the stack pointer will be unalignet on PowerMac
1718          */
1719         rldicr  r1,r1,0,59
1720
1721         /* Make sure we are running in 64 bits mode */
1722         bl      .enable_64b_mode
1723
1724         /* put a relocation offset into r3 */
1725         bl      .reloc_offset
1726
1727         LOAD_REG_IMMEDIATE(r2,__toc_start)
1728         addi    r2,r2,0x4000
1729         addi    r2,r2,0x4000
1730
1731         /* Relocate the TOC from a virt addr to a real addr */
1732         add     r2,r2,r3
1733
1734         /* Restore parameters */
1735         mr      r3,r31
1736         mr      r4,r30
1737         mr      r5,r29
1738         mr      r6,r28
1739         mr      r7,r27
1740
1741         /* Do all of the interaction with OF client interface */
1742         bl      .prom_init
1743         /* We never return */
1744         trap
1745 #endif
1746
1747 /*
1748  * At this point, r3 contains the physical address we are running at,
1749  * returned by prom_init()
1750  */
1751 _STATIC(__after_prom_start)
1752
1753 /*
1754  * We need to run with __start at physical address PHYSICAL_START.
1755  * This will leave some code in the first 256B of
1756  * real memory, which are reserved for software use.
1757  * The remainder of the first page is loaded with the fixed
1758  * interrupt vectors.  The next two pages are filled with
1759  * unknown exception placeholders.
1760  *
1761  * Note: This process overwrites the OF exception vectors.
1762  *      r26 == relocation offset
1763  *      r27 == KERNELBASE
1764  */
1765         bl      .reloc_offset
1766         mr      r26,r3
1767         LOAD_REG_IMMEDIATE(r27, KERNELBASE)
1768
1769         LOAD_REG_IMMEDIATE(r3, PHYSICAL_START)  /* target addr */
1770
1771         // XXX FIXME: Use phys returned by OF (r30)
1772         add     r4,r27,r26              /* source addr                   */
1773                                         /* current address of _start     */
1774                                         /*   i.e. where we are running   */
1775                                         /*      the source addr          */
1776
1777         cmpdi   r4,0                    /* In some cases the loader may  */
1778         beq     .start_here_multiplatform /* have already put us at zero */
1779                                         /* so we can skip the copy.      */
1780         LOAD_REG_IMMEDIATE(r5,copy_to_here) /* # bytes of memory to copy */
1781         sub     r5,r5,r27
1782
1783         li      r6,0x100                /* Start offset, the first 0x100 */
1784                                         /* bytes were copied earlier.    */
1785
1786         bl      .copy_and_flush         /* copy the first n bytes        */
1787                                         /* this includes the code being  */
1788                                         /* executed here.                */
1789
1790         LOAD_REG_IMMEDIATE(r0, 4f)      /* Jump to the copy of this code */
1791         mtctr   r0                      /* that we just made/relocated   */
1792         bctr
1793
1794 4:      LOAD_REG_IMMEDIATE(r5,klimit)
1795         add     r5,r5,r26
1796         ld      r5,0(r5)                /* get the value of klimit */
1797         sub     r5,r5,r27
1798         bl      .copy_and_flush         /* copy the rest */
1799         b       .start_here_multiplatform
1800
1801 #endif /* CONFIG_PPC_MULTIPLATFORM */
1802
1803 /*
1804  * Copy routine used to copy the kernel to start at physical address 0
1805  * and flush and invalidate the caches as needed.
1806  * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
1807  * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
1808  *
1809  * Note: this routine *only* clobbers r0, r6 and lr
1810  */
1811 _GLOBAL(copy_and_flush)
1812         addi    r5,r5,-8
1813         addi    r6,r6,-8
1814 4:      li      r0,8                    /* Use the smallest common      */
1815                                         /* denominator cache line       */
1816                                         /* size.  This results in       */
1817                                         /* extra cache line flushes     */
1818                                         /* but operation is correct.    */
1819                                         /* Can't get cache line size    */
1820                                         /* from NACA as it is being     */
1821                                         /* moved too.                   */
1822
1823         mtctr   r0                      /* put # words/line in ctr      */
1824 3:      addi    r6,r6,8                 /* copy a cache line            */
1825         ldx     r0,r6,r4
1826         stdx    r0,r6,r3
1827         bdnz    3b
1828         dcbst   r6,r3                   /* write it to memory           */
1829         sync
1830         icbi    r6,r3                   /* flush the icache line        */
1831         cmpld   0,r6,r5
1832         blt     4b
1833         sync
1834         addi    r5,r5,8
1835         addi    r6,r6,8
1836         blr
1837
1838 .align 8
1839 copy_to_here:
1840
1841 #ifdef CONFIG_SMP
1842 #ifdef CONFIG_PPC_PMAC
1843 /*
1844  * On PowerMac, secondary processors starts from the reset vector, which
1845  * is temporarily turned into a call to one of the functions below.
1846  */
1847         .section ".text";
1848         .align 2 ;
1849
1850         .globl  __secondary_start_pmac_0
1851 __secondary_start_pmac_0:
1852         /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
1853         li      r24,0
1854         b       1f
1855         li      r24,1
1856         b       1f
1857         li      r24,2
1858         b       1f
1859         li      r24,3
1860 1:
1861
1862 _GLOBAL(pmac_secondary_start)
1863         /* turn on 64-bit mode */
1864         bl      .enable_64b_mode
1865         isync
1866
1867         /* Copy some CPU settings from CPU 0 */
1868         bl      .__restore_cpu_ppc970
1869
1870         /* pSeries do that early though I don't think we really need it */
1871         mfmsr   r3
1872         ori     r3,r3,MSR_RI
1873         mtmsrd  r3                      /* RI on */
1874
1875         /* Set up a paca value for this processor. */
1876         LOAD_REG_IMMEDIATE(r4, paca)    /* Get base vaddr of paca array */
1877         mulli   r13,r24,PACA_SIZE        /* Calculate vaddr of right paca */
1878         add     r13,r13,r4              /* for this processor.          */
1879         mtspr   SPRN_SPRG3,r13           /* Save vaddr of paca in SPRG3 */
1880
1881         /* Create a temp kernel stack for use before relocation is on.  */
1882         ld      r1,PACAEMERGSP(r13)
1883         subi    r1,r1,STACK_FRAME_OVERHEAD
1884
1885         b       .__secondary_start
1886
1887 #endif /* CONFIG_PPC_PMAC */
1888
1889 /*
1890  * This function is called after the master CPU has released the
1891  * secondary processors.  The execution environment is relocation off.
1892  * The paca for this processor has the following fields initialized at
1893  * this point:
1894  *   1. Processor number
1895  *   2. Segment table pointer (virtual address)
1896  * On entry the following are set:
1897  *   r1 = stack pointer.  vaddr for iSeries, raddr (temp stack) for pSeries
1898  *   r24   = cpu# (in Linux terms)
1899  *   r13   = paca virtual address
1900  *   SPRG3 = paca virtual address
1901  */
1902 _GLOBAL(__secondary_start)
1903         /* Set thread priority to MEDIUM */
1904         HMT_MEDIUM
1905
1906         /* Load TOC */
1907         ld      r2,PACATOC(r13)
1908
1909         /* Do early setup for that CPU (stab, slb, hash table pointer) */
1910         bl      .early_setup_secondary
1911
1912         /* Initialize the kernel stack.  Just a repeat for iSeries.      */
1913         LOAD_REG_ADDR(r3, current_set)
1914         sldi    r28,r24,3               /* get current_set[cpu#]         */
1915         ldx     r1,r3,r28
1916         addi    r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1917         std     r1,PACAKSAVE(r13)
1918
1919         /* Clear backchain so we get nice backtraces */
1920         li      r7,0
1921         mtlr    r7
1922
1923         /* enable MMU and jump to start_secondary */
1924         LOAD_REG_ADDR(r3, .start_secondary_prolog)
1925         LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
1926 #ifdef CONFIG_PPC_ISERIES
1927 BEGIN_FW_FTR_SECTION
1928         ori     r4,r4,MSR_EE
1929 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1930 #endif
1931 BEGIN_FW_FTR_SECTION
1932         stb     r7,PACASOFTIRQEN(r13)
1933         stb     r7,PACAHARDIRQEN(r13)
1934 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
1935
1936         mtspr   SPRN_SRR0,r3
1937         mtspr   SPRN_SRR1,r4
1938         rfid
1939         b       .       /* prevent speculative execution */
1940
1941 /*
1942  * Running with relocation on at this point.  All we want to do is
1943  * zero the stack back-chain pointer before going into C code.
1944  */
1945 _GLOBAL(start_secondary_prolog)
1946         li      r3,0
1947         std     r3,0(r1)                /* Zero the stack frame pointer */
1948         bl      .start_secondary
1949         b       .
1950 #endif
1951
1952 /*
1953  * This subroutine clobbers r11 and r12
1954  */
1955 _GLOBAL(enable_64b_mode)
1956         mfmsr   r11                     /* grab the current MSR */
1957         li      r12,1
1958         rldicr  r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
1959         or      r11,r11,r12
1960         li      r12,1
1961         rldicr  r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
1962         or      r11,r11,r12
1963         mtmsrd  r11
1964         isync
1965         blr
1966
1967 #ifdef CONFIG_PPC_MULTIPLATFORM
1968 /*
1969  * This is where the main kernel code starts.
1970  */
1971 _STATIC(start_here_multiplatform)
1972         /* get a new offset, now that the kernel has moved. */
1973         bl      .reloc_offset
1974         mr      r26,r3
1975
1976         /* Clear out the BSS. It may have been done in prom_init,
1977          * already but that's irrelevant since prom_init will soon
1978          * be detached from the kernel completely. Besides, we need
1979          * to clear it now for kexec-style entry.
1980          */
1981         LOAD_REG_IMMEDIATE(r11,__bss_stop)
1982         LOAD_REG_IMMEDIATE(r8,__bss_start)
1983         sub     r11,r11,r8              /* bss size                     */
1984         addi    r11,r11,7               /* round up to an even double word */
1985         rldicl. r11,r11,61,3            /* shift right by 3             */
1986         beq     4f
1987         addi    r8,r8,-8
1988         li      r0,0
1989         mtctr   r11                     /* zero this many doublewords   */
1990 3:      stdu    r0,8(r8)
1991         bdnz    3b
1992 4:
1993
1994         mfmsr   r6
1995         ori     r6,r6,MSR_RI
1996         mtmsrd  r6                      /* RI on */
1997
1998         /* The following gets the stack and TOC set up with the regs */
1999         /* pointing to the real addr of the kernel stack.  This is   */
2000         /* all done to support the C function call below which sets  */
2001         /* up the htab.  This is done because we have relocated the  */
2002         /* kernel but are still running in real mode. */
2003
2004         LOAD_REG_IMMEDIATE(r3,init_thread_union)
2005         add     r3,r3,r26
2006
2007         /* set up a stack pointer (physical address) */
2008         addi    r1,r3,THREAD_SIZE
2009         li      r0,0
2010         stdu    r0,-STACK_FRAME_OVERHEAD(r1)
2011
2012         /* set up the TOC (physical address) */
2013         LOAD_REG_IMMEDIATE(r2,__toc_start)
2014         addi    r2,r2,0x4000
2015         addi    r2,r2,0x4000
2016         add     r2,r2,r26
2017
2018         LOAD_REG_IMMEDIATE(r3, cpu_specs)
2019         add     r3,r3,r26
2020         LOAD_REG_IMMEDIATE(r4,cur_cpu_spec)
2021         add     r4,r4,r26
2022         mr      r5,r26
2023         bl      .identify_cpu
2024
2025         /* Do very early kernel initializations, including initial hash table,
2026          * stab and slb setup before we turn on relocation.     */
2027
2028         /* Restore parameters passed from prom_init/kexec */
2029         mr      r3,r31
2030         bl      .early_setup
2031
2032         LOAD_REG_IMMEDIATE(r3, .start_here_common)
2033         LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
2034         mtspr   SPRN_SRR0,r3
2035         mtspr   SPRN_SRR1,r4
2036         rfid
2037         b       .       /* prevent speculative execution */
2038 #endif /* CONFIG_PPC_MULTIPLATFORM */
2039
2040         /* This is where all platforms converge execution */
2041 _STATIC(start_here_common)
2042         /* relocation is on at this point */
2043
2044         /* The following code sets up the SP and TOC now that we are */
2045         /* running with translation enabled. */
2046
2047         LOAD_REG_IMMEDIATE(r3,init_thread_union)
2048
2049         /* set up the stack */
2050         addi    r1,r3,THREAD_SIZE
2051         li      r0,0
2052         stdu    r0,-STACK_FRAME_OVERHEAD(r1)
2053
2054         /* Apply the CPUs-specific fixups (nop out sections not relevant
2055          * to this CPU
2056          */
2057         li      r3,0
2058         bl      .do_cpu_ftr_fixups
2059         bl      .do_fw_ftr_fixups
2060
2061         /* ptr to current */
2062         LOAD_REG_IMMEDIATE(r4, init_task)
2063         std     r4,PACACURRENT(r13)
2064
2065         /* Load the TOC */
2066         ld      r2,PACATOC(r13)
2067         std     r1,PACAKSAVE(r13)
2068
2069         bl      .setup_system
2070
2071         /* Load up the kernel context */
2072 5:
2073         li      r5,0
2074         stb     r5,PACASOFTIRQEN(r13)   /* Soft Disabled */
2075 #ifdef CONFIG_PPC_ISERIES
2076 BEGIN_FW_FTR_SECTION
2077         mfmsr   r5
2078         ori     r5,r5,MSR_EE            /* Hard Enabled */
2079         mtmsrd  r5
2080 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
2081 #endif
2082 BEGIN_FW_FTR_SECTION
2083         stb     r5,PACAHARDIRQEN(r13)
2084 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
2085
2086         bl .start_kernel
2087
2088         /* Not reached */
2089         BUG_OPCODE
2090
2091 /*
2092  * We put a few things here that have to be page-aligned.
2093  * This stuff goes at the beginning of the bss, which is page-aligned.
2094  */
2095         .section ".bss"
2096
2097         .align  PAGE_SHIFT
2098
2099         .globl  empty_zero_page
2100 empty_zero_page:
2101         .space  PAGE_SIZE
2102
2103         .globl  swapper_pg_dir
2104 swapper_pg_dir:
2105         .space  PAGE_SIZE
2106
2107 /*
2108  * This space gets a copy of optional info passed to us by the bootstrap
2109  * Used to pass parameters into the kernel like root=/dev/sda1, etc.
2110  */
2111         .globl  cmd_line
2112 cmd_line:
2113         .space  COMMAND_LINE_SIZE