3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
12 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
13 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
15 * This file contains the low-level support and setup for the
16 * PowerPC-64 platform, including trap and interrupt dispatch.
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version
21 * 2 of the License, or (at your option) any later version.
24 #include <linux/threads.h>
28 #include <asm/ppc_asm.h>
29 #include <asm/asm-offsets.h>
31 #include <asm/cputable.h>
32 #include <asm/setup.h>
33 #include <asm/hvcall.h>
34 #include <asm/iseries/lpar_map.h>
35 #include <asm/thread_info.h>
36 #include <asm/firmware.h>
37 #include <asm/page_64.h>
38 #include <asm/exception.h>
39 #include <asm/irqflags.h>
42 * We layout physical memory as follows:
43 * 0x0000 - 0x00ff : Secondary processor spin code
44 * 0x0100 - 0x2fff : pSeries Interrupt prologs
45 * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs
46 * 0x6000 - 0x6fff : Initial (CPU0) segment table
47 * 0x7000 - 0x7fff : FWNMI data area
48 * 0x8000 - : Early init and support code
56 * SPRG0 reserved for hypervisor
57 * SPRG1 temp - used to save gpr
58 * SPRG2 temp - used to save gpr
59 * SPRG3 virt addr of paca
63 * Entering into this code we make the following assumptions:
65 * 1. The MMU is off & open firmware is running in real mode.
66 * 2. The kernel is entered at __start
69 * 1. The MMU is on (as it always is for iSeries)
70 * 2. The kernel is entered at system_reset_iSeries
77 /* NOP this out unconditionally */
79 b .__start_initialization_multiplatform
82 /* Catch branch to 0 in real mode */
85 /* Secondary processors spin on this value until it goes to 1. */
86 .globl __secondary_hold_spinloop
87 __secondary_hold_spinloop:
90 /* Secondary processors write this value with their cpu # */
91 /* after they enter the spin loop immediately below. */
92 .globl __secondary_hold_acknowledge
93 __secondary_hold_acknowledge:
96 #ifdef CONFIG_PPC_ISERIES
98 * At offset 0x20, there is a pointer to iSeries LPAR data.
99 * This is required by the hypervisor
102 .llong hvReleaseData-KERNELBASE
103 #endif /* CONFIG_PPC_ISERIES */
107 * The following code is used to hold secondary processors
108 * in a spin loop after they have entered the kernel, but
109 * before the bulk of the kernel has been relocated. This code
110 * is relocated to physical address 0x60 before prom_init is run.
111 * All of it must fit below the first exception vector at 0x100.
113 _GLOBAL(__secondary_hold)
116 mtmsrd r24 /* RI on */
118 /* Grab our physical cpu number */
121 /* Tell the master cpu we're here */
122 /* Relocation is off & we are located at an address less */
123 /* than 0x100, so only need to grab low order offset. */
124 std r24,__secondary_hold_acknowledge@l(0)
127 /* All secondary cpus wait here until told to start. */
128 100: ld r4,__secondary_hold_spinloop@l(0)
132 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
133 LOAD_REG_IMMEDIATE(r4, .generic_secondary_smp_init)
141 /* This value is used to mark exception frames on the stack. */
144 .tc ID_72656773_68657265[TC],0x7265677368657265
148 * This is the start of the interrupt handlers for pSeries
149 * This code runs with relocation off.
152 .globl __start_interrupts
155 STD_EXCEPTION_PSERIES(0x100, system_reset)
158 _machine_check_pSeries:
160 mtspr SPRN_SPRG1,r13 /* save r13 */
161 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
164 .globl data_access_pSeries
173 rlwimi r13,r12,16,0x20
176 beq do_stab_bolted_pSeries
179 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
180 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
183 .globl data_access_slb_pSeries
184 data_access_slb_pSeries:
187 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
188 std r3,PACA_EXSLB+EX_R3(r13)
190 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
193 /* Keep that around for when we re-implement dynamic VSIDs */
195 bge slb_miss_user_pseries
196 #endif /* __DISABLED__ */
197 std r10,PACA_EXSLB+EX_R10(r13)
198 std r11,PACA_EXSLB+EX_R11(r13)
199 std r12,PACA_EXSLB+EX_R12(r13)
201 std r10,PACA_EXSLB+EX_R13(r13)
202 mfspr r12,SPRN_SRR1 /* and SRR1 */
203 b .slb_miss_realmode /* Rel. branch works in real mode */
205 STD_EXCEPTION_PSERIES(0x400, instruction_access)
208 .globl instruction_access_slb_pSeries
209 instruction_access_slb_pSeries:
212 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
213 std r3,PACA_EXSLB+EX_R3(r13)
214 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
215 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
218 /* Keep that around for when we re-implement dynamic VSIDs */
220 bge slb_miss_user_pseries
221 #endif /* __DISABLED__ */
222 std r10,PACA_EXSLB+EX_R10(r13)
223 std r11,PACA_EXSLB+EX_R11(r13)
224 std r12,PACA_EXSLB+EX_R12(r13)
226 std r10,PACA_EXSLB+EX_R13(r13)
227 mfspr r12,SPRN_SRR1 /* and SRR1 */
228 b .slb_miss_realmode /* Rel. branch works in real mode */
230 MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt)
231 STD_EXCEPTION_PSERIES(0x600, alignment)
232 STD_EXCEPTION_PSERIES(0x700, program_check)
233 STD_EXCEPTION_PSERIES(0x800, fp_unavailable)
234 MASKABLE_EXCEPTION_PSERIES(0x900, decrementer)
235 STD_EXCEPTION_PSERIES(0xa00, trap_0a)
236 STD_EXCEPTION_PSERIES(0xb00, trap_0b)
239 .globl system_call_pSeries
245 END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE)
251 oris r12,r12,system_call_common@h
252 ori r12,r12,system_call_common@l
254 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
258 b . /* prevent speculative execution */
260 /* Fast LE/BE switch system call */
261 1: mfspr r12,SPRN_SRR1
264 rfid /* return to userspace */
267 STD_EXCEPTION_PSERIES(0xd00, single_step)
268 STD_EXCEPTION_PSERIES(0xe00, trap_0e)
270 /* We need to deal with the Altivec unavailable exception
271 * here which is at 0xf20, thus in the middle of the
272 * prolog code of the PerformanceMonitor one. A little
273 * trickery is thus necessary
276 b performance_monitor_pSeries
279 b altivec_unavailable_pSeries
281 #ifdef CONFIG_CBE_RAS
282 HSTD_EXCEPTION_PSERIES(0x1200, cbe_system_error)
283 #endif /* CONFIG_CBE_RAS */
284 STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint)
285 #ifdef CONFIG_CBE_RAS
286 HSTD_EXCEPTION_PSERIES(0x1600, cbe_maintenance)
287 #endif /* CONFIG_CBE_RAS */
288 STD_EXCEPTION_PSERIES(0x1700, altivec_assist)
289 #ifdef CONFIG_CBE_RAS
290 HSTD_EXCEPTION_PSERIES(0x1800, cbe_thermal)
291 #endif /* CONFIG_CBE_RAS */
295 /*** pSeries interrupt support ***/
297 /* moved from 0xf00 */
298 STD_EXCEPTION_PSERIES(., performance_monitor)
299 STD_EXCEPTION_PSERIES(., altivec_unavailable)
302 * An interrupt came in while soft-disabled; clear EE in SRR1,
303 * clear paca->hard_enabled and return.
306 stb r10,PACAHARDIRQEN(r13)
308 ld r9,PACA_EXGEN+EX_R9(r13)
310 rldicl r10,r10,48,1 /* clear MSR_EE */
313 ld r10,PACA_EXGEN+EX_R10(r13)
319 do_stab_bolted_pSeries:
322 EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
325 * We have some room here we use that to put
326 * the peries slb miss user trampoline code so it's reasonably
327 * away from slb_miss_user_common to avoid problems with rfid
329 * This is used for when the SLB miss handler has to go virtual,
330 * which doesn't happen for now anymore but will once we re-implement
331 * dynamic VSIDs for shared page tables
334 slb_miss_user_pseries:
335 std r10,PACA_EXGEN+EX_R10(r13)
336 std r11,PACA_EXGEN+EX_R11(r13)
337 std r12,PACA_EXGEN+EX_R12(r13)
339 ld r11,PACA_EXSLB+EX_R9(r13)
340 ld r12,PACA_EXSLB+EX_R3(r13)
341 std r10,PACA_EXGEN+EX_R13(r13)
342 std r11,PACA_EXGEN+EX_R9(r13)
343 std r12,PACA_EXGEN+EX_R3(r13)
346 mfspr r11,SRR0 /* save SRR0 */
347 ori r12,r12,slb_miss_user_common@l /* virt addr of handler */
348 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
350 mfspr r12,SRR1 /* and SRR1 */
353 b . /* prevent spec. execution */
354 #endif /* __DISABLED__ */
356 #ifdef CONFIG_PPC_PSERIES
358 * Vectors for the FWNMI option. Share common code.
360 .globl system_reset_fwnmi
364 mtspr SPRN_SPRG1,r13 /* save r13 */
365 EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXGEN, system_reset_common)
367 .globl machine_check_fwnmi
371 mtspr SPRN_SPRG1,r13 /* save r13 */
372 EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXMC, machine_check_common)
374 #endif /* CONFIG_PPC_PSERIES */
376 /*** Common interrupt handlers ***/
378 STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception)
381 * Machine check is different because we use a different
382 * save area: PACA_EXMC instead of PACA_EXGEN.
385 .globl machine_check_common
386 machine_check_common:
387 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
391 addi r3,r1,STACK_FRAME_OVERHEAD
392 bl .machine_check_exception
395 STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt)
396 STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception)
397 STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
398 STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
399 STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
400 STD_EXCEPTION_COMMON_IDLE(0xf00, performance_monitor, .performance_monitor_exception)
401 STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
402 #ifdef CONFIG_ALTIVEC
403 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
405 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception)
407 #ifdef CONFIG_CBE_RAS
408 STD_EXCEPTION_COMMON(0x1200, cbe_system_error, .cbe_system_error_exception)
409 STD_EXCEPTION_COMMON(0x1600, cbe_maintenance, .cbe_maintenance_exception)
410 STD_EXCEPTION_COMMON(0x1800, cbe_thermal, .cbe_thermal_exception)
411 #endif /* CONFIG_CBE_RAS */
414 * Here we have detected that the kernel stack pointer is bad.
415 * R9 contains the saved CR, r13 points to the paca,
416 * r10 contains the (bad) kernel stack pointer,
417 * r11 and r12 contain the saved SRR0 and SRR1.
418 * We switch to using an emergency stack, save the registers there,
419 * and call kernel_bad_stack(), which panics.
422 ld r1,PACAEMERGSP(r13)
423 subi r1,r1,64+INT_FRAME_SIZE
444 lhz r12,PACA_TRAP_SAVE(r13)
446 addi r11,r1,INT_FRAME_SIZE
451 1: addi r3,r1,STACK_FRAME_OVERHEAD
456 * Return from an exception with minimal checks.
457 * The caller is assumed to have done EXCEPTION_PROLOG_COMMON.
458 * If interrupts have been enabled, or anything has been
459 * done that might have changed the scheduling status of
460 * any task or sent any task a signal, you should use
461 * ret_from_except or ret_from_except_lite instead of this.
463 fast_exc_return_irq: /* restores irq state too */
465 TRACE_AND_RESTORE_IRQ(r3);
467 rldicl r4,r12,49,63 /* get MSR_EE to LSB */
468 stb r4,PACAHARDIRQEN(r13) /* restore paca->hard_enabled */
471 .globl fast_exception_return
472 fast_exception_return:
475 andi. r3,r12,MSR_RI /* check if RI is set */
478 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
481 ACCOUNT_CPU_USER_EXIT(r3, r4)
497 rldicl r10,r10,48,1 /* clear EE */
498 rldicr r10,r10,16,61 /* clear RI (LE is 0 already) */
506 b . /* prevent speculative execution */
510 1: addi r3,r1,STACK_FRAME_OVERHEAD
511 bl .unrecoverable_exception
515 * Here r13 points to the paca, r9 contains the saved CR,
516 * SRR0 and SRR1 are saved in r11 and r12,
517 * r9 - r13 are saved in paca->exgen.
520 .globl data_access_common
523 std r10,PACA_EXGEN+EX_DAR(r13)
525 stw r10,PACA_EXGEN+EX_DSISR(r13)
526 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
527 ld r3,PACA_EXGEN+EX_DAR(r13)
528 lwz r4,PACA_EXGEN+EX_DSISR(r13)
530 b .do_hash_page /* Try to handle as hpte fault */
533 .globl instruction_access_common
534 instruction_access_common:
535 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
539 b .do_hash_page /* Try to handle as hpte fault */
542 * Here is the common SLB miss user that is used when going to virtual
543 * mode for SLB misses, that is currently not used
547 .globl slb_miss_user_common
548 slb_miss_user_common:
550 std r3,PACA_EXGEN+EX_DAR(r13)
551 stw r9,PACA_EXGEN+EX_CCR(r13)
552 std r10,PACA_EXGEN+EX_LR(r13)
553 std r11,PACA_EXGEN+EX_SRR0(r13)
554 bl .slb_allocate_user
556 ld r10,PACA_EXGEN+EX_LR(r13)
557 ld r3,PACA_EXGEN+EX_R3(r13)
558 lwz r9,PACA_EXGEN+EX_CCR(r13)
559 ld r11,PACA_EXGEN+EX_SRR0(r13)
563 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
564 beq- unrecov_user_slb
572 clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */
578 ld r9,PACA_EXGEN+EX_R9(r13)
579 ld r10,PACA_EXGEN+EX_R10(r13)
580 ld r11,PACA_EXGEN+EX_R11(r13)
581 ld r12,PACA_EXGEN+EX_R12(r13)
582 ld r13,PACA_EXGEN+EX_R13(r13)
587 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN)
588 ld r4,PACA_EXGEN+EX_DAR(r13)
595 EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN)
598 1: addi r3,r1,STACK_FRAME_OVERHEAD
599 bl .unrecoverable_exception
602 #endif /* __DISABLED__ */
606 * r13 points to the PACA, r9 contains the saved CR,
607 * r12 contain the saved SRR1, SRR0 is still ready for return
608 * r3 has the faulting address
609 * r9 - r13 are saved in paca->exslb.
610 * r3 is saved in paca->slb_r3
611 * We assume we aren't going to take any exceptions during this procedure.
613 _GLOBAL(slb_miss_realmode)
616 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
617 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
619 bl .slb_allocate_realmode
621 /* All done -- return from exception. */
623 ld r10,PACA_EXSLB+EX_LR(r13)
624 ld r3,PACA_EXSLB+EX_R3(r13)
625 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
626 #ifdef CONFIG_PPC_ISERIES
628 ld r11,PACALPPACAPTR(r13)
629 ld r11,LPPACASRR0(r11) /* get SRR0 value */
630 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
631 #endif /* CONFIG_PPC_ISERIES */
635 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
641 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
644 #ifdef CONFIG_PPC_ISERIES
648 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
649 #endif /* CONFIG_PPC_ISERIES */
650 ld r9,PACA_EXSLB+EX_R9(r13)
651 ld r10,PACA_EXSLB+EX_R10(r13)
652 ld r11,PACA_EXSLB+EX_R11(r13)
653 ld r12,PACA_EXSLB+EX_R12(r13)
654 ld r13,PACA_EXSLB+EX_R13(r13)
656 b . /* prevent speculative execution */
659 #ifdef CONFIG_PPC_ISERIES
662 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
663 #endif /* CONFIG_PPC_ISERIES */
666 LOAD_HANDLER(r10,unrecov_slb)
669 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
675 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
678 1: addi r3,r1,STACK_FRAME_OVERHEAD
679 bl .unrecoverable_exception
683 .globl hardware_interrupt_common
684 .globl hardware_interrupt_entry
685 hardware_interrupt_common:
686 EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN)
688 hardware_interrupt_entry:
691 bl .ppc64_runlatch_on
692 END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
693 addi r3,r1,STACK_FRAME_OVERHEAD
695 b .ret_from_except_lite
697 #ifdef CONFIG_PPC_970_NAP
700 std r9,TI_LOCAL_FLAGS(r11)
701 ld r10,_LINK(r1) /* make idle task do the */
702 std r10,_NIP(r1) /* equivalent of a blr */
707 .globl alignment_common
710 std r10,PACA_EXGEN+EX_DAR(r13)
712 stw r10,PACA_EXGEN+EX_DSISR(r13)
713 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
714 ld r3,PACA_EXGEN+EX_DAR(r13)
715 lwz r4,PACA_EXGEN+EX_DSISR(r13)
719 addi r3,r1,STACK_FRAME_OVERHEAD
721 bl .alignment_exception
725 .globl program_check_common
726 program_check_common:
727 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
729 addi r3,r1,STACK_FRAME_OVERHEAD
731 bl .program_check_exception
735 .globl fp_unavailable_common
736 fp_unavailable_common:
737 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
738 bne 1f /* if from user, just load it up */
740 addi r3,r1,STACK_FRAME_OVERHEAD
742 bl .kernel_fp_unavailable_exception
747 .globl altivec_unavailable_common
748 altivec_unavailable_common:
749 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
750 #ifdef CONFIG_ALTIVEC
752 bne .load_up_altivec /* if from user, just load it up */
753 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
756 addi r3,r1,STACK_FRAME_OVERHEAD
758 bl .altivec_unavailable_exception
761 #ifdef CONFIG_ALTIVEC
763 * load_up_altivec(unused, unused, tsk)
764 * Disable VMX for the task which had it previously,
765 * and save its vector registers in its thread_struct.
766 * Enables the VMX for use in the kernel on return.
767 * On SMP we know the VMX is free, since we give it up every
768 * switch (ie, no lazy save of the vector registers).
769 * On entry: r13 == 'current' && last_task_used_altivec != 'current'
771 _STATIC(load_up_altivec)
772 mfmsr r5 /* grab the current MSR */
774 mtmsrd r5 /* enable use of VMX now */
778 * For SMP, we don't do lazy VMX switching because it just gets too
779 * horrendously complex, especially when a task switches from one CPU
780 * to another. Instead we call giveup_altvec in switch_to.
781 * VRSAVE isn't dealt with here, that is done in the normal context
782 * switch code. Note that we could rely on vrsave value to eventually
783 * avoid saving all of the VREGs here...
786 ld r3,last_task_used_altivec@got(r2)
790 /* Save VMX state to last_task_used_altivec's THREAD struct */
796 /* Disable VMX for last_task_used_altivec */
798 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
801 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
803 #endif /* CONFIG_SMP */
804 /* Hack: if we get an altivec unavailable trap with VRSAVE
805 * set to all zeros, we assume this is a broken application
806 * that fails to set it properly, and thus we switch it to
815 /* enable use of VMX after return */
816 ld r4,PACACURRENT(r13)
817 addi r5,r4,THREAD /* Get THREAD */
818 oris r12,r12,MSR_VEC@h
822 stw r4,THREAD_USED_VR(r5)
827 /* Update last_task_used_math to 'current' */
828 subi r4,r5,THREAD /* Back to 'current' */
830 #endif /* CONFIG_SMP */
831 /* restore registers and return */
832 b fast_exception_return
833 #endif /* CONFIG_ALTIVEC */
839 _STATIC(do_hash_page)
843 andis. r0,r4,0xa450 /* weird error? */
844 bne- handle_page_fault /* if not, try to insert a HPTE */
846 andis. r0,r4,0x0020 /* Is it a segment table fault? */
847 bne- do_ste_alloc /* If so handle it */
848 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
851 * On iSeries, we soft-disable interrupts here, then
852 * hard-enable interrupts so that the hash_page code can spin on
853 * the hash_table_lock without problems on a shared processor.
858 * Currently, trace_hardirqs_off() will be called by DISABLE_INTS
859 * and will clobber volatile registers when irq tracing is enabled
860 * so we need to reload them. It may be possible to be smarter here
861 * and move the irq tracing elsewhere but let's keep it simple for
864 #ifdef CONFIG_TRACE_IRQFLAGS
870 #endif /* CONFIG_TRACE_IRQFLAGS */
872 * We need to set the _PAGE_USER bit if MSR_PR is set or if we are
873 * accessing a userspace segment (even from the kernel). We assume
874 * kernel addresses always have the high bit set.
876 rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */
877 rotldi r0,r3,15 /* Move high bit into MSR_PR posn */
878 orc r0,r12,r0 /* MSR_PR | ~high_bit */
879 rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */
880 ori r4,r4,1 /* add _PAGE_PRESENT */
881 rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */
884 * r3 contains the faulting address
885 * r4 contains the required access permissions
886 * r5 contains the trap number
888 * at return r3 = 0 for success
890 bl .hash_page /* build HPTE if possible */
891 cmpdi r3,0 /* see if hash_page succeeded */
895 * If we had interrupts soft-enabled at the point where the
896 * DSI/ISI occurred, and an interrupt came in during hash_page,
898 * We jump to ret_from_except_lite rather than fast_exception_return
899 * because ret_from_except_lite will check for and handle pending
900 * interrupts if necessary.
903 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
907 * Here we have interrupts hard-disabled, so it is sufficient
908 * to restore paca->{soft,hard}_enable and get out.
910 beq fast_exc_return_irq /* Return from exception on success */
911 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
913 /* For a hash failure, we don't bother re-enabling interrupts */
917 * hash_page couldn't handle it, set soft interrupt enable back
918 * to what it was before the trap. Note that .raw_local_irq_restore
919 * handles any interrupts pending at this point.
922 TRACE_AND_RESTORE_IRQ_PARTIAL(r3, 11f)
923 bl .raw_local_irq_restore
926 /* Here we have a page fault that hash_page can't handle. */
931 addi r3,r1,STACK_FRAME_OVERHEAD
937 addi r3,r1,STACK_FRAME_OVERHEAD
942 13: b .ret_from_except_lite
944 /* We have a page fault that hash_page could handle but HV refused
949 addi r3,r1,STACK_FRAME_OVERHEAD
954 /* here we have a segment miss */
956 bl .ste_allocate /* try to insert stab entry */
958 bne- handle_page_fault
959 b fast_exception_return
962 * r13 points to the PACA, r9 contains the saved CR,
963 * r11 and r12 contain the saved SRR0 and SRR1.
964 * r9 - r13 are saved in paca->exslb.
965 * We assume we aren't going to take any exceptions during this procedure.
966 * We assume (DAR >> 60) == 0xc.
969 _GLOBAL(do_stab_bolted)
970 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
971 std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */
973 /* Hash to the primary group */
974 ld r10,PACASTABVIRT(r13)
977 rldimi r10,r11,7,52 /* r10 = first ste of the group */
980 /* This is a kernel address, so protovsid = ESID */
981 ASM_VSID_SCRAMBLE(r11, r9, 256M)
982 rldic r9,r11,12,16 /* r9 = vsid << 12 */
984 /* Search the primary group for a free entry */
985 1: ld r11,0(r10) /* Test valid bit of the current ste */
992 /* Stick for only searching the primary group for now. */
993 /* At least for now, we use a very simple random castout scheme */
994 /* Use the TB as a random number ; OR in 1 to avoid entry 0 */
996 rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */
999 /* r10 currently points to an ste one past the group of interest */
1000 /* make it point to the randomly selected entry */
1002 or r10,r10,r11 /* r10 is the entry to invalidate */
1004 isync /* mark the entry invalid */
1006 rldicl r11,r11,56,1 /* clear the valid bit */
1011 clrrdi r11,r11,28 /* Get the esid part of the ste */
1014 2: std r9,8(r10) /* Store the vsid part of the ste */
1017 mfspr r11,SPRN_DAR /* Get the new esid */
1018 clrrdi r11,r11,28 /* Permits a full 32b of ESID */
1019 ori r11,r11,0x90 /* Turn on valid and kp */
1020 std r11,0(r10) /* Put new entry back into the stab */
1024 /* All done -- return from exception. */
1025 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1026 ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */
1028 andi. r10,r12,MSR_RI
1031 mtcrf 0x80,r9 /* restore CR */
1039 ld r9,PACA_EXSLB+EX_R9(r13)
1040 ld r10,PACA_EXSLB+EX_R10(r13)
1041 ld r11,PACA_EXSLB+EX_R11(r13)
1042 ld r12,PACA_EXSLB+EX_R12(r13)
1043 ld r13,PACA_EXSLB+EX_R13(r13)
1045 b . /* prevent speculative execution */
1048 * Space for CPU0's segment table.
1050 * On iSeries, the hypervisor must fill in at least one entry before
1051 * we get control (with relocate on). The address is given to the hv
1052 * as a page number (see xLparMap below), so this must be at a
1053 * fixed address (the linker can't compute (u64)&initial_stab >>
1056 . = STAB0_OFFSET /* 0x6000 */
1061 #ifdef CONFIG_PPC_PSERIES
1063 * Data area reserved for FWNMI option.
1064 * This address (0x7000) is fixed by the RPA.
1067 .globl fwnmi_data_area
1069 #endif /* CONFIG_PPC_PSERIES */
1071 /* iSeries does not use the FWNMI stuff, so it is safe to put
1072 * this here, even if we later allow kernels that will boot on
1073 * both pSeries and iSeries */
1074 #ifdef CONFIG_PPC_ISERIES
1078 .quad HvEsidsToMap /* xNumberEsids */
1079 .quad HvRangesToMap /* xNumberRanges */
1080 .quad STAB0_PAGE /* xSegmentTableOffs */
1081 .zero 40 /* xRsvd */
1082 /* xEsids (HvEsidsToMap entries of 2 quads) */
1083 .quad PAGE_OFFSET_ESID /* xKernelEsid */
1084 .quad PAGE_OFFSET_VSID /* xKernelVsid */
1085 .quad VMALLOC_START_ESID /* xKernelEsid */
1086 .quad VMALLOC_START_VSID /* xKernelVsid */
1087 /* xRanges (HvRangesToMap entries of 3 quads) */
1088 .quad HvPagesToMap /* xPages */
1089 .quad 0 /* xOffset */
1090 .quad PAGE_OFFSET_VSID << (SID_SHIFT - HW_PAGE_SHIFT) /* xVPN */
1092 #endif /* CONFIG_PPC_ISERIES */
1094 #ifdef CONFIG_PPC_PSERIES
1096 #endif /* CONFIG_PPC_PSERIES */
1099 * On pSeries and most other platforms, secondary processors spin
1100 * in the following code.
1101 * At entry, r3 = this processor's number (physical cpu id)
1103 _GLOBAL(generic_secondary_smp_init)
1106 /* turn on 64-bit mode */
1109 /* Set up a paca value for this processor. Since we have the
1110 * physical cpu id in r24, we need to search the pacas to find
1111 * which logical id maps to our physical one.
1113 LOAD_REG_IMMEDIATE(r13, paca) /* Get base vaddr of paca array */
1114 li r5,0 /* logical cpu id */
1115 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
1116 cmpw r6,r24 /* Compare to our id */
1118 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */
1123 mr r3,r24 /* not found, copy phys to r3 */
1124 b .kexec_wait /* next kernel might do better */
1126 2: mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1127 /* From now on, r24 is expected to be logical cpuid */
1130 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
1135 b 3b /* Never go on non-SMP */
1138 beq 3b /* Loop until told to go */
1140 /* See if we need to call a cpu state restore handler */
1141 LOAD_REG_IMMEDIATE(r23, cur_cpu_spec)
1143 ld r23,CPU_SPEC_RESTORE(r23)
1150 4: /* Create a temp kernel stack for use before relocation is on. */
1151 ld r1,PACAEMERGSP(r13)
1152 subi r1,r1,STACK_FRAME_OVERHEAD
1159 andi. r0,r3,MSR_IR|MSR_DR
1166 b . /* prevent speculative execution */
1170 * Here is our main kernel entry point. We support currently 2 kind of entries
1171 * depending on the value of r5.
1173 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
1176 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
1177 * DT block, r4 is a physical pointer to the kernel itself
1180 _GLOBAL(__start_initialization_multiplatform)
1182 * Are we booted from a PROM Of-type client-interface ?
1186 b .__boot_from_prom /* yes -> prom */
1188 /* Save parameters */
1192 /* Make sure we are running in 64 bits mode */
1195 /* Setup some critical 970 SPRs before switching MMU off */
1198 cmpwi r0,0x39 /* 970 */
1200 cmpwi r0,0x3c /* 970FX */
1202 cmpwi r0,0x44 /* 970MP */
1204 cmpwi r0,0x45 /* 970GX */
1206 1: bl .__cpu_preinit_ppc970
1209 /* Switch off MMU if not already */
1210 LOAD_REG_IMMEDIATE(r4, .__after_prom_start - KERNELBASE)
1213 b .__after_prom_start
1215 _INIT_STATIC(__boot_from_prom)
1216 /* Save parameters */
1224 * Align the stack to 16-byte boundary
1225 * Depending on the size and layout of the ELF sections in the initial
1226 * boot binary, the stack pointer will be unalignet on PowerMac
1230 /* Make sure we are running in 64 bits mode */
1233 /* put a relocation offset into r3 */
1236 LOAD_REG_IMMEDIATE(r2,__toc_start)
1240 /* Relocate the TOC from a virt addr to a real addr */
1243 /* Restore parameters */
1250 /* Do all of the interaction with OF client interface */
1252 /* We never return */
1255 _STATIC(__after_prom_start)
1258 * We need to run with __start at physical address PHYSICAL_START.
1259 * This will leave some code in the first 256B of
1260 * real memory, which are reserved for software use.
1261 * The remainder of the first page is loaded with the fixed
1262 * interrupt vectors. The next two pages are filled with
1263 * unknown exception placeholders.
1265 * Note: This process overwrites the OF exception vectors.
1266 * r26 == relocation offset
1271 LOAD_REG_IMMEDIATE(r27, KERNELBASE)
1273 LOAD_REG_IMMEDIATE(r3, PHYSICAL_START) /* target addr */
1275 // XXX FIXME: Use phys returned by OF (r30)
1276 add r4,r27,r26 /* source addr */
1277 /* current address of _start */
1278 /* i.e. where we are running */
1279 /* the source addr */
1281 cmpdi r4,0 /* In some cases the loader may */
1283 b .start_here_multiplatform /* have already put us at zero */
1284 /* so we can skip the copy. */
1285 1: LOAD_REG_IMMEDIATE(r5,copy_to_here) /* # bytes of memory to copy */
1288 li r6,0x100 /* Start offset, the first 0x100 */
1289 /* bytes were copied earlier. */
1291 bl .copy_and_flush /* copy the first n bytes */
1292 /* this includes the code being */
1293 /* executed here. */
1295 LOAD_REG_IMMEDIATE(r0, 4f) /* Jump to the copy of this code */
1296 mtctr r0 /* that we just made/relocated */
1299 4: LOAD_REG_IMMEDIATE(r5,klimit)
1301 ld r5,0(r5) /* get the value of klimit */
1303 bl .copy_and_flush /* copy the rest */
1304 b .start_here_multiplatform
1307 * Copy routine used to copy the kernel to start at physical address 0
1308 * and flush and invalidate the caches as needed.
1309 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
1310 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
1312 * Note: this routine *only* clobbers r0, r6 and lr
1314 _GLOBAL(copy_and_flush)
1317 4: li r0,8 /* Use the smallest common */
1318 /* denominator cache line */
1319 /* size. This results in */
1320 /* extra cache line flushes */
1321 /* but operation is correct. */
1322 /* Can't get cache line size */
1323 /* from NACA as it is being */
1326 mtctr r0 /* put # words/line in ctr */
1327 3: addi r6,r6,8 /* copy a cache line */
1331 dcbst r6,r3 /* write it to memory */
1333 icbi r6,r3 /* flush the icache line */
1345 #ifdef CONFIG_PPC_PMAC
1347 * On PowerMac, secondary processors starts from the reset vector, which
1348 * is temporarily turned into a call to one of the functions below.
1353 .globl __secondary_start_pmac_0
1354 __secondary_start_pmac_0:
1355 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
1365 _GLOBAL(pmac_secondary_start)
1366 /* turn on 64-bit mode */
1369 /* Copy some CPU settings from CPU 0 */
1370 bl .__restore_cpu_ppc970
1372 /* pSeries do that early though I don't think we really need it */
1375 mtmsrd r3 /* RI on */
1377 /* Set up a paca value for this processor. */
1378 LOAD_REG_IMMEDIATE(r4, paca) /* Get base vaddr of paca array */
1379 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
1380 add r13,r13,r4 /* for this processor. */
1381 mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1383 /* Create a temp kernel stack for use before relocation is on. */
1384 ld r1,PACAEMERGSP(r13)
1385 subi r1,r1,STACK_FRAME_OVERHEAD
1389 #endif /* CONFIG_PPC_PMAC */
1392 * This function is called after the master CPU has released the
1393 * secondary processors. The execution environment is relocation off.
1394 * The paca for this processor has the following fields initialized at
1396 * 1. Processor number
1397 * 2. Segment table pointer (virtual address)
1398 * On entry the following are set:
1399 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries
1400 * r24 = cpu# (in Linux terms)
1401 * r13 = paca virtual address
1402 * SPRG3 = paca virtual address
1404 .globl __secondary_start
1406 /* Set thread priority to MEDIUM */
1412 /* Do early setup for that CPU (stab, slb, hash table pointer) */
1413 bl .early_setup_secondary
1415 /* Initialize the kernel stack. Just a repeat for iSeries. */
1416 LOAD_REG_ADDR(r3, current_set)
1417 sldi r28,r24,3 /* get current_set[cpu#] */
1419 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1420 std r1,PACAKSAVE(r13)
1422 /* Clear backchain so we get nice backtraces */
1426 /* enable MMU and jump to start_secondary */
1427 LOAD_REG_ADDR(r3, .start_secondary_prolog)
1428 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
1429 #ifdef CONFIG_PPC_ISERIES
1430 BEGIN_FW_FTR_SECTION
1433 stb r8,PACAHARDIRQEN(r13)
1434 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1436 BEGIN_FW_FTR_SECTION
1437 stb r7,PACAHARDIRQEN(r13)
1438 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
1439 stb r7,PACASOFTIRQEN(r13)
1444 b . /* prevent speculative execution */
1447 * Running with relocation on at this point. All we want to do is
1448 * zero the stack back-chain pointer before going into C code.
1450 _GLOBAL(start_secondary_prolog)
1452 std r3,0(r1) /* Zero the stack frame pointer */
1458 * This subroutine clobbers r11 and r12
1460 _GLOBAL(enable_64b_mode)
1461 mfmsr r11 /* grab the current MSR */
1463 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
1466 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
1473 * This is where the main kernel code starts.
1475 _INIT_STATIC(start_here_multiplatform)
1476 /* get a new offset, now that the kernel has moved. */
1480 /* Clear out the BSS. It may have been done in prom_init,
1481 * already but that's irrelevant since prom_init will soon
1482 * be detached from the kernel completely. Besides, we need
1483 * to clear it now for kexec-style entry.
1485 LOAD_REG_IMMEDIATE(r11,__bss_stop)
1486 LOAD_REG_IMMEDIATE(r8,__bss_start)
1487 sub r11,r11,r8 /* bss size */
1488 addi r11,r11,7 /* round up to an even double word */
1489 rldicl. r11,r11,61,3 /* shift right by 3 */
1493 mtctr r11 /* zero this many doublewords */
1500 mtmsrd r6 /* RI on */
1502 /* The following gets the stack and TOC set up with the regs */
1503 /* pointing to the real addr of the kernel stack. This is */
1504 /* all done to support the C function call below which sets */
1505 /* up the htab. This is done because we have relocated the */
1506 /* kernel but are still running in real mode. */
1508 LOAD_REG_IMMEDIATE(r3,init_thread_union)
1511 /* set up a stack pointer (physical address) */
1512 addi r1,r3,THREAD_SIZE
1514 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1516 /* set up the TOC (physical address) */
1517 LOAD_REG_IMMEDIATE(r2,__toc_start)
1522 /* Do very early kernel initializations, including initial hash table,
1523 * stab and slb setup before we turn on relocation. */
1525 /* Restore parameters passed from prom_init/kexec */
1529 LOAD_REG_IMMEDIATE(r3, .start_here_common)
1530 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
1534 b . /* prevent speculative execution */
1536 /* This is where all platforms converge execution */
1537 _INIT_GLOBAL(start_here_common)
1538 /* relocation is on at this point */
1540 /* The following code sets up the SP and TOC now that we are */
1541 /* running with translation enabled. */
1543 LOAD_REG_IMMEDIATE(r3,init_thread_union)
1545 /* set up the stack */
1546 addi r1,r3,THREAD_SIZE
1548 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1552 std r1,PACAKSAVE(r13)
1556 /* Load up the kernel context */
1559 stb r5,PACASOFTIRQEN(r13) /* Soft Disabled */
1560 #ifdef CONFIG_PPC_ISERIES
1561 BEGIN_FW_FTR_SECTION
1563 ori r5,r5,MSR_EE /* Hard Enabled on iSeries*/
1566 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1568 stb r5,PACAHARDIRQEN(r13) /* Hard Disabled on others */
1576 * We put a few things here that have to be page-aligned.
1577 * This stuff goes at the beginning of the bss, which is page-aligned.
1583 .globl empty_zero_page
1587 .globl swapper_pg_dir
1589 .space PGD_TABLE_SIZE