3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
12 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
13 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
15 * This file contains the low-level support and setup for the
16 * PowerPC-64 platform, including trap and interrupt dispatch.
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version
21 * 2 of the License, or (at your option) any later version.
24 #include <linux/threads.h>
28 #include <asm/ppc_asm.h>
29 #include <asm/asm-offsets.h>
31 #include <asm/cputable.h>
32 #include <asm/setup.h>
33 #include <asm/hvcall.h>
34 #include <asm/iseries/lpar_map.h>
35 #include <asm/thread_info.h>
36 #include <asm/firmware.h>
37 #include <asm/page_64.h>
38 #include <asm/exception.h>
39 #include <asm/irqflags.h>
42 * We layout physical memory as follows:
43 * 0x0000 - 0x00ff : Secondary processor spin code
44 * 0x0100 - 0x2fff : pSeries Interrupt prologs
45 * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs
46 * 0x6000 - 0x6fff : Initial (CPU0) segment table
47 * 0x7000 - 0x7fff : FWNMI data area
48 * 0x8000 - : Early init and support code
56 * SPRG0 reserved for hypervisor
57 * SPRG1 temp - used to save gpr
58 * SPRG2 temp - used to save gpr
59 * SPRG3 virt addr of paca
63 * Entering into this code we make the following assumptions:
65 * 1. The MMU is off & open firmware is running in real mode.
66 * 2. The kernel is entered at __start
69 * 1. The MMU is on (as it always is for iSeries)
70 * 2. The kernel is entered at system_reset_iSeries
77 /* NOP this out unconditionally */
79 b .__start_initialization_multiplatform
82 /* Catch branch to 0 in real mode */
85 /* Secondary processors spin on this value until it goes to 1. */
86 .globl __secondary_hold_spinloop
87 __secondary_hold_spinloop:
90 /* Secondary processors write this value with their cpu # */
91 /* after they enter the spin loop immediately below. */
92 .globl __secondary_hold_acknowledge
93 __secondary_hold_acknowledge:
96 #ifdef CONFIG_PPC_ISERIES
98 * At offset 0x20, there is a pointer to iSeries LPAR data.
99 * This is required by the hypervisor
102 .llong hvReleaseData-KERNELBASE
103 #endif /* CONFIG_PPC_ISERIES */
107 * The following code is used to hold secondary processors
108 * in a spin loop after they have entered the kernel, but
109 * before the bulk of the kernel has been relocated. This code
110 * is relocated to physical address 0x60 before prom_init is run.
111 * All of it must fit below the first exception vector at 0x100.
113 _GLOBAL(__secondary_hold)
116 mtmsrd r24 /* RI on */
118 /* Grab our physical cpu number */
121 /* Tell the master cpu we're here */
122 /* Relocation is off & we are located at an address less */
123 /* than 0x100, so only need to grab low order offset. */
124 std r24,__secondary_hold_acknowledge@l(0)
127 /* All secondary cpus wait here until told to start. */
128 100: ld r4,__secondary_hold_spinloop@l(0)
132 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
133 LOAD_REG_IMMEDIATE(r4, .generic_secondary_smp_init)
141 /* This value is used to mark exception frames on the stack. */
144 .tc ID_72656773_68657265[TC],0x7265677368657265
148 * This is the start of the interrupt handlers for pSeries
149 * This code runs with relocation off.
152 .globl __start_interrupts
155 STD_EXCEPTION_PSERIES(0x100, system_reset)
158 _machine_check_pSeries:
160 mtspr SPRN_SPRG1,r13 /* save r13 */
161 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
164 .globl data_access_pSeries
173 rlwimi r13,r12,16,0x20
176 beq do_stab_bolted_pSeries
179 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
180 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
183 .globl data_access_slb_pSeries
184 data_access_slb_pSeries:
187 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
188 std r3,PACA_EXSLB+EX_R3(r13)
190 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
193 /* Keep that around for when we re-implement dynamic VSIDs */
195 bge slb_miss_user_pseries
196 #endif /* __DISABLED__ */
197 std r10,PACA_EXSLB+EX_R10(r13)
198 std r11,PACA_EXSLB+EX_R11(r13)
199 std r12,PACA_EXSLB+EX_R12(r13)
201 std r10,PACA_EXSLB+EX_R13(r13)
202 mfspr r12,SPRN_SRR1 /* and SRR1 */
203 b .slb_miss_realmode /* Rel. branch works in real mode */
205 STD_EXCEPTION_PSERIES(0x400, instruction_access)
208 .globl instruction_access_slb_pSeries
209 instruction_access_slb_pSeries:
212 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
213 std r3,PACA_EXSLB+EX_R3(r13)
214 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
215 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
218 /* Keep that around for when we re-implement dynamic VSIDs */
220 bge slb_miss_user_pseries
221 #endif /* __DISABLED__ */
222 std r10,PACA_EXSLB+EX_R10(r13)
223 std r11,PACA_EXSLB+EX_R11(r13)
224 std r12,PACA_EXSLB+EX_R12(r13)
226 std r10,PACA_EXSLB+EX_R13(r13)
227 mfspr r12,SPRN_SRR1 /* and SRR1 */
228 b .slb_miss_realmode /* Rel. branch works in real mode */
230 MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt)
231 STD_EXCEPTION_PSERIES(0x600, alignment)
232 STD_EXCEPTION_PSERIES(0x700, program_check)
233 STD_EXCEPTION_PSERIES(0x800, fp_unavailable)
234 MASKABLE_EXCEPTION_PSERIES(0x900, decrementer)
235 STD_EXCEPTION_PSERIES(0xa00, trap_0a)
236 STD_EXCEPTION_PSERIES(0xb00, trap_0b)
239 .globl system_call_pSeries
245 END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE)
251 oris r12,r12,system_call_common@h
252 ori r12,r12,system_call_common@l
254 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
258 b . /* prevent speculative execution */
260 /* Fast LE/BE switch system call */
261 1: mfspr r12,SPRN_SRR1
264 rfid /* return to userspace */
267 STD_EXCEPTION_PSERIES(0xd00, single_step)
268 STD_EXCEPTION_PSERIES(0xe00, trap_0e)
270 /* We need to deal with the Altivec unavailable exception
271 * here which is at 0xf20, thus in the middle of the
272 * prolog code of the PerformanceMonitor one. A little
273 * trickery is thus necessary
276 b performance_monitor_pSeries
279 b altivec_unavailable_pSeries
282 b vsx_unavailable_pSeries
284 #ifdef CONFIG_CBE_RAS
285 HSTD_EXCEPTION_PSERIES(0x1200, cbe_system_error)
286 #endif /* CONFIG_CBE_RAS */
287 STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint)
288 #ifdef CONFIG_CBE_RAS
289 HSTD_EXCEPTION_PSERIES(0x1600, cbe_maintenance)
290 #endif /* CONFIG_CBE_RAS */
291 STD_EXCEPTION_PSERIES(0x1700, altivec_assist)
292 #ifdef CONFIG_CBE_RAS
293 HSTD_EXCEPTION_PSERIES(0x1800, cbe_thermal)
294 #endif /* CONFIG_CBE_RAS */
298 /*** pSeries interrupt support ***/
300 /* moved from 0xf00 */
301 STD_EXCEPTION_PSERIES(., performance_monitor)
302 STD_EXCEPTION_PSERIES(., altivec_unavailable)
303 STD_EXCEPTION_PSERIES(., vsx_unavailable)
306 * An interrupt came in while soft-disabled; clear EE in SRR1,
307 * clear paca->hard_enabled and return.
310 stb r10,PACAHARDIRQEN(r13)
312 ld r9,PACA_EXGEN+EX_R9(r13)
314 rldicl r10,r10,48,1 /* clear MSR_EE */
317 ld r10,PACA_EXGEN+EX_R10(r13)
323 do_stab_bolted_pSeries:
326 EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
328 #ifdef CONFIG_PPC_PSERIES
330 * Vectors for the FWNMI option. Share common code.
332 .globl system_reset_fwnmi
336 mtspr SPRN_SPRG1,r13 /* save r13 */
337 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common)
339 .globl machine_check_fwnmi
343 mtspr SPRN_SPRG1,r13 /* save r13 */
344 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
346 #endif /* CONFIG_PPC_PSERIES */
350 * This is used for when the SLB miss handler has to go virtual,
351 * which doesn't happen for now anymore but will once we re-implement
352 * dynamic VSIDs for shared page tables
354 slb_miss_user_pseries:
355 std r10,PACA_EXGEN+EX_R10(r13)
356 std r11,PACA_EXGEN+EX_R11(r13)
357 std r12,PACA_EXGEN+EX_R12(r13)
359 ld r11,PACA_EXSLB+EX_R9(r13)
360 ld r12,PACA_EXSLB+EX_R3(r13)
361 std r10,PACA_EXGEN+EX_R13(r13)
362 std r11,PACA_EXGEN+EX_R9(r13)
363 std r12,PACA_EXGEN+EX_R3(r13)
366 mfspr r11,SRR0 /* save SRR0 */
367 ori r12,r12,slb_miss_user_common@l /* virt addr of handler */
368 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
370 mfspr r12,SRR1 /* and SRR1 */
373 b . /* prevent spec. execution */
374 #endif /* __DISABLED__ */
377 .globl __end_interrupts
381 * Code from here down to __end_handlers is invoked from the
382 * exception prologs above.
385 /*** Common interrupt handlers ***/
387 STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception)
390 * Machine check is different because we use a different
391 * save area: PACA_EXMC instead of PACA_EXGEN.
394 .globl machine_check_common
395 machine_check_common:
396 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
400 addi r3,r1,STACK_FRAME_OVERHEAD
401 bl .machine_check_exception
404 STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt)
405 STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception)
406 STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
407 STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
408 STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
409 STD_EXCEPTION_COMMON_IDLE(0xf00, performance_monitor, .performance_monitor_exception)
410 STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
411 #ifdef CONFIG_ALTIVEC
412 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
414 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception)
416 #ifdef CONFIG_CBE_RAS
417 STD_EXCEPTION_COMMON(0x1200, cbe_system_error, .cbe_system_error_exception)
418 STD_EXCEPTION_COMMON(0x1600, cbe_maintenance, .cbe_maintenance_exception)
419 STD_EXCEPTION_COMMON(0x1800, cbe_thermal, .cbe_thermal_exception)
420 #endif /* CONFIG_CBE_RAS */
423 * Here we have detected that the kernel stack pointer is bad.
424 * R9 contains the saved CR, r13 points to the paca,
425 * r10 contains the (bad) kernel stack pointer,
426 * r11 and r12 contain the saved SRR0 and SRR1.
427 * We switch to using an emergency stack, save the registers there,
428 * and call kernel_bad_stack(), which panics.
431 ld r1,PACAEMERGSP(r13)
432 subi r1,r1,64+INT_FRAME_SIZE
453 lhz r12,PACA_TRAP_SAVE(r13)
455 addi r11,r1,INT_FRAME_SIZE
460 1: addi r3,r1,STACK_FRAME_OVERHEAD
465 * Here r13 points to the paca, r9 contains the saved CR,
466 * SRR0 and SRR1 are saved in r11 and r12,
467 * r9 - r13 are saved in paca->exgen.
470 .globl data_access_common
473 std r10,PACA_EXGEN+EX_DAR(r13)
475 stw r10,PACA_EXGEN+EX_DSISR(r13)
476 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
477 ld r3,PACA_EXGEN+EX_DAR(r13)
478 lwz r4,PACA_EXGEN+EX_DSISR(r13)
480 b .do_hash_page /* Try to handle as hpte fault */
483 .globl instruction_access_common
484 instruction_access_common:
485 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
489 b .do_hash_page /* Try to handle as hpte fault */
492 * Here is the common SLB miss user that is used when going to virtual
493 * mode for SLB misses, that is currently not used
497 .globl slb_miss_user_common
498 slb_miss_user_common:
500 std r3,PACA_EXGEN+EX_DAR(r13)
501 stw r9,PACA_EXGEN+EX_CCR(r13)
502 std r10,PACA_EXGEN+EX_LR(r13)
503 std r11,PACA_EXGEN+EX_SRR0(r13)
504 bl .slb_allocate_user
506 ld r10,PACA_EXGEN+EX_LR(r13)
507 ld r3,PACA_EXGEN+EX_R3(r13)
508 lwz r9,PACA_EXGEN+EX_CCR(r13)
509 ld r11,PACA_EXGEN+EX_SRR0(r13)
513 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
514 beq- unrecov_user_slb
522 clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */
528 ld r9,PACA_EXGEN+EX_R9(r13)
529 ld r10,PACA_EXGEN+EX_R10(r13)
530 ld r11,PACA_EXGEN+EX_R11(r13)
531 ld r12,PACA_EXGEN+EX_R12(r13)
532 ld r13,PACA_EXGEN+EX_R13(r13)
537 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN)
538 ld r4,PACA_EXGEN+EX_DAR(r13)
545 EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN)
548 1: addi r3,r1,STACK_FRAME_OVERHEAD
549 bl .unrecoverable_exception
552 #endif /* __DISABLED__ */
556 * r13 points to the PACA, r9 contains the saved CR,
557 * r12 contain the saved SRR1, SRR0 is still ready for return
558 * r3 has the faulting address
559 * r9 - r13 are saved in paca->exslb.
560 * r3 is saved in paca->slb_r3
561 * We assume we aren't going to take any exceptions during this procedure.
563 _GLOBAL(slb_miss_realmode)
566 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
567 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
569 bl .slb_allocate_realmode
571 /* All done -- return from exception. */
573 ld r10,PACA_EXSLB+EX_LR(r13)
574 ld r3,PACA_EXSLB+EX_R3(r13)
575 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
576 #ifdef CONFIG_PPC_ISERIES
578 ld r11,PACALPPACAPTR(r13)
579 ld r11,LPPACASRR0(r11) /* get SRR0 value */
580 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
581 #endif /* CONFIG_PPC_ISERIES */
585 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
591 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
594 #ifdef CONFIG_PPC_ISERIES
598 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
599 #endif /* CONFIG_PPC_ISERIES */
600 ld r9,PACA_EXSLB+EX_R9(r13)
601 ld r10,PACA_EXSLB+EX_R10(r13)
602 ld r11,PACA_EXSLB+EX_R11(r13)
603 ld r12,PACA_EXSLB+EX_R12(r13)
604 ld r13,PACA_EXSLB+EX_R13(r13)
606 b . /* prevent speculative execution */
609 #ifdef CONFIG_PPC_ISERIES
612 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
613 #endif /* CONFIG_PPC_ISERIES */
616 LOAD_HANDLER(r10,unrecov_slb)
619 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
625 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
628 1: addi r3,r1,STACK_FRAME_OVERHEAD
629 bl .unrecoverable_exception
633 .globl hardware_interrupt_common
634 .globl hardware_interrupt_entry
635 hardware_interrupt_common:
636 EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN)
638 hardware_interrupt_entry:
641 bl .ppc64_runlatch_on
642 END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
643 addi r3,r1,STACK_FRAME_OVERHEAD
645 b .ret_from_except_lite
647 #ifdef CONFIG_PPC_970_NAP
650 std r9,TI_LOCAL_FLAGS(r11)
651 ld r10,_LINK(r1) /* make idle task do the */
652 std r10,_NIP(r1) /* equivalent of a blr */
657 .globl alignment_common
660 std r10,PACA_EXGEN+EX_DAR(r13)
662 stw r10,PACA_EXGEN+EX_DSISR(r13)
663 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
664 ld r3,PACA_EXGEN+EX_DAR(r13)
665 lwz r4,PACA_EXGEN+EX_DSISR(r13)
669 addi r3,r1,STACK_FRAME_OVERHEAD
671 bl .alignment_exception
675 .globl program_check_common
676 program_check_common:
677 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
679 addi r3,r1,STACK_FRAME_OVERHEAD
681 bl .program_check_exception
685 .globl fp_unavailable_common
686 fp_unavailable_common:
687 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
688 bne 1f /* if from user, just load it up */
690 addi r3,r1,STACK_FRAME_OVERHEAD
692 bl .kernel_fp_unavailable_exception
695 b fast_exception_return
698 .globl altivec_unavailable_common
699 altivec_unavailable_common:
700 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
701 #ifdef CONFIG_ALTIVEC
705 b fast_exception_return
707 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
710 addi r3,r1,STACK_FRAME_OVERHEAD
712 bl .altivec_unavailable_exception
716 .globl vsx_unavailable_common
717 vsx_unavailable_common:
718 EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN)
723 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
726 addi r3,r1,STACK_FRAME_OVERHEAD
728 bl .vsx_unavailable_exception
732 .globl __end_handlers
736 * Return from an exception with minimal checks.
737 * The caller is assumed to have done EXCEPTION_PROLOG_COMMON.
738 * If interrupts have been enabled, or anything has been
739 * done that might have changed the scheduling status of
740 * any task or sent any task a signal, you should use
741 * ret_from_except or ret_from_except_lite instead of this.
743 fast_exc_return_irq: /* restores irq state too */
745 TRACE_AND_RESTORE_IRQ(r3);
747 rldicl r4,r12,49,63 /* get MSR_EE to LSB */
748 stb r4,PACAHARDIRQEN(r13) /* restore paca->hard_enabled */
751 .globl fast_exception_return
752 fast_exception_return:
755 andi. r3,r12,MSR_RI /* check if RI is set */
758 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
761 ACCOUNT_CPU_USER_EXIT(r3, r4)
777 rldicl r10,r10,48,1 /* clear EE */
778 rldicr r10,r10,16,61 /* clear RI (LE is 0 already) */
786 b . /* prevent speculative execution */
790 1: addi r3,r1,STACK_FRAME_OVERHEAD
791 bl .unrecoverable_exception
794 #ifdef CONFIG_ALTIVEC
796 * load_up_altivec(unused, unused, tsk)
797 * Disable VMX for the task which had it previously,
798 * and save its vector registers in its thread_struct.
799 * Enables the VMX for use in the kernel on return.
800 * On SMP we know the VMX is free, since we give it up every
801 * switch (ie, no lazy save of the vector registers).
802 * On entry: r13 == 'current' && last_task_used_altivec != 'current'
804 _STATIC(load_up_altivec)
805 mfmsr r5 /* grab the current MSR */
807 mtmsrd r5 /* enable use of VMX now */
811 * For SMP, we don't do lazy VMX switching because it just gets too
812 * horrendously complex, especially when a task switches from one CPU
813 * to another. Instead we call giveup_altvec in switch_to.
814 * VRSAVE isn't dealt with here, that is done in the normal context
815 * switch code. Note that we could rely on vrsave value to eventually
816 * avoid saving all of the VREGs here...
819 ld r3,last_task_used_altivec@got(r2)
823 /* Save VMX state to last_task_used_altivec's THREAD struct */
829 /* Disable VMX for last_task_used_altivec */
831 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
834 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
836 #endif /* CONFIG_SMP */
837 /* Hack: if we get an altivec unavailable trap with VRSAVE
838 * set to all zeros, we assume this is a broken application
839 * that fails to set it properly, and thus we switch it to
848 /* enable use of VMX after return */
849 ld r4,PACACURRENT(r13)
850 addi r5,r4,THREAD /* Get THREAD */
851 oris r12,r12,MSR_VEC@h
855 stw r4,THREAD_USED_VR(r5)
860 /* Update last_task_used_math to 'current' */
861 subi r4,r5,THREAD /* Back to 'current' */
863 #endif /* CONFIG_SMP */
864 /* restore registers and return */
866 #endif /* CONFIG_ALTIVEC */
870 * load_up_vsx(unused, unused, tsk)
871 * Disable VSX for the task which had it previously,
872 * and save its vector registers in its thread_struct.
873 * Reuse the fp and vsx saves, but first check to see if they have
874 * been saved already.
875 * On entry: r13 == 'current' && last_task_used_vsx != 'current'
878 /* Load FP and VSX registers if they haven't been done yet */
880 beql+ load_up_fpu /* skip if already loaded */
881 andis. r5,r12,MSR_VEC@h
882 beql+ load_up_altivec /* skip if already loaded */
885 ld r3,last_task_used_vsx@got(r2)
889 /* Disable VSX for last_task_used_vsx */
892 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
895 std r6,_MSR-STACK_FRAME_OVERHEAD(r5)
897 #endif /* CONFIG_SMP */
898 ld r4,PACACURRENT(r13)
899 addi r4,r4,THREAD /* Get THREAD */
901 stw r6,THREAD_USED_VSR(r4) /* ... also set thread used vsr */
902 /* enable use of VSX after return */
903 oris r12,r12,MSR_VSX@h
906 /* Update last_task_used_math to 'current' */
907 ld r4,PACACURRENT(r13)
909 #endif /* CONFIG_SMP */
910 b fast_exception_return
911 #endif /* CONFIG_VSX */
917 _STATIC(do_hash_page)
921 andis. r0,r4,0xa450 /* weird error? */
922 bne- handle_page_fault /* if not, try to insert a HPTE */
924 andis. r0,r4,0x0020 /* Is it a segment table fault? */
925 bne- do_ste_alloc /* If so handle it */
926 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
929 * On iSeries, we soft-disable interrupts here, then
930 * hard-enable interrupts so that the hash_page code can spin on
931 * the hash_table_lock without problems on a shared processor.
936 * Currently, trace_hardirqs_off() will be called by DISABLE_INTS
937 * and will clobber volatile registers when irq tracing is enabled
938 * so we need to reload them. It may be possible to be smarter here
939 * and move the irq tracing elsewhere but let's keep it simple for
942 #ifdef CONFIG_TRACE_IRQFLAGS
948 #endif /* CONFIG_TRACE_IRQFLAGS */
950 * We need to set the _PAGE_USER bit if MSR_PR is set or if we are
951 * accessing a userspace segment (even from the kernel). We assume
952 * kernel addresses always have the high bit set.
954 rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */
955 rotldi r0,r3,15 /* Move high bit into MSR_PR posn */
956 orc r0,r12,r0 /* MSR_PR | ~high_bit */
957 rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */
958 ori r4,r4,1 /* add _PAGE_PRESENT */
959 rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */
962 * r3 contains the faulting address
963 * r4 contains the required access permissions
964 * r5 contains the trap number
966 * at return r3 = 0 for success
968 bl .hash_page /* build HPTE if possible */
969 cmpdi r3,0 /* see if hash_page succeeded */
973 * If we had interrupts soft-enabled at the point where the
974 * DSI/ISI occurred, and an interrupt came in during hash_page,
976 * We jump to ret_from_except_lite rather than fast_exception_return
977 * because ret_from_except_lite will check for and handle pending
978 * interrupts if necessary.
981 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
985 * Here we have interrupts hard-disabled, so it is sufficient
986 * to restore paca->{soft,hard}_enable and get out.
988 beq fast_exc_return_irq /* Return from exception on success */
989 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
991 /* For a hash failure, we don't bother re-enabling interrupts */
995 * hash_page couldn't handle it, set soft interrupt enable back
996 * to what it was before the trap. Note that .raw_local_irq_restore
997 * handles any interrupts pending at this point.
1000 TRACE_AND_RESTORE_IRQ_PARTIAL(r3, 11f)
1001 bl .raw_local_irq_restore
1004 /* Here we have a page fault that hash_page can't handle. */
1009 addi r3,r1,STACK_FRAME_OVERHEAD
1015 addi r3,r1,STACK_FRAME_OVERHEAD
1020 13: b .ret_from_except_lite
1022 /* We have a page fault that hash_page could handle but HV refused
1027 addi r3,r1,STACK_FRAME_OVERHEAD
1032 /* here we have a segment miss */
1034 bl .ste_allocate /* try to insert stab entry */
1036 bne- handle_page_fault
1037 b fast_exception_return
1040 * r13 points to the PACA, r9 contains the saved CR,
1041 * r11 and r12 contain the saved SRR0 and SRR1.
1042 * r9 - r13 are saved in paca->exslb.
1043 * We assume we aren't going to take any exceptions during this procedure.
1044 * We assume (DAR >> 60) == 0xc.
1047 _GLOBAL(do_stab_bolted)
1048 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1049 std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */
1051 /* Hash to the primary group */
1052 ld r10,PACASTABVIRT(r13)
1055 rldimi r10,r11,7,52 /* r10 = first ste of the group */
1057 /* Calculate VSID */
1058 /* This is a kernel address, so protovsid = ESID */
1059 ASM_VSID_SCRAMBLE(r11, r9, 256M)
1060 rldic r9,r11,12,16 /* r9 = vsid << 12 */
1062 /* Search the primary group for a free entry */
1063 1: ld r11,0(r10) /* Test valid bit of the current ste */
1070 /* Stick for only searching the primary group for now. */
1071 /* At least for now, we use a very simple random castout scheme */
1072 /* Use the TB as a random number ; OR in 1 to avoid entry 0 */
1074 rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */
1077 /* r10 currently points to an ste one past the group of interest */
1078 /* make it point to the randomly selected entry */
1080 or r10,r10,r11 /* r10 is the entry to invalidate */
1082 isync /* mark the entry invalid */
1084 rldicl r11,r11,56,1 /* clear the valid bit */
1089 clrrdi r11,r11,28 /* Get the esid part of the ste */
1092 2: std r9,8(r10) /* Store the vsid part of the ste */
1095 mfspr r11,SPRN_DAR /* Get the new esid */
1096 clrrdi r11,r11,28 /* Permits a full 32b of ESID */
1097 ori r11,r11,0x90 /* Turn on valid and kp */
1098 std r11,0(r10) /* Put new entry back into the stab */
1102 /* All done -- return from exception. */
1103 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1104 ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */
1106 andi. r10,r12,MSR_RI
1109 mtcrf 0x80,r9 /* restore CR */
1117 ld r9,PACA_EXSLB+EX_R9(r13)
1118 ld r10,PACA_EXSLB+EX_R10(r13)
1119 ld r11,PACA_EXSLB+EX_R11(r13)
1120 ld r12,PACA_EXSLB+EX_R12(r13)
1121 ld r13,PACA_EXSLB+EX_R13(r13)
1123 b . /* prevent speculative execution */
1126 * Space for CPU0's segment table.
1128 * On iSeries, the hypervisor must fill in at least one entry before
1129 * we get control (with relocate on). The address is given to the hv
1130 * as a page number (see xLparMap below), so this must be at a
1131 * fixed address (the linker can't compute (u64)&initial_stab >>
1134 . = STAB0_OFFSET /* 0x6000 */
1139 #ifdef CONFIG_PPC_PSERIES
1141 * Data area reserved for FWNMI option.
1142 * This address (0x7000) is fixed by the RPA.
1145 .globl fwnmi_data_area
1147 #endif /* CONFIG_PPC_PSERIES */
1149 /* iSeries does not use the FWNMI stuff, so it is safe to put
1150 * this here, even if we later allow kernels that will boot on
1151 * both pSeries and iSeries */
1152 #ifdef CONFIG_PPC_ISERIES
1156 .quad HvEsidsToMap /* xNumberEsids */
1157 .quad HvRangesToMap /* xNumberRanges */
1158 .quad STAB0_PAGE /* xSegmentTableOffs */
1159 .zero 40 /* xRsvd */
1160 /* xEsids (HvEsidsToMap entries of 2 quads) */
1161 .quad PAGE_OFFSET_ESID /* xKernelEsid */
1162 .quad PAGE_OFFSET_VSID /* xKernelVsid */
1163 .quad VMALLOC_START_ESID /* xKernelEsid */
1164 .quad VMALLOC_START_VSID /* xKernelVsid */
1165 /* xRanges (HvRangesToMap entries of 3 quads) */
1166 .quad HvPagesToMap /* xPages */
1167 .quad 0 /* xOffset */
1168 .quad PAGE_OFFSET_VSID << (SID_SHIFT - HW_PAGE_SHIFT) /* xVPN */
1170 #endif /* CONFIG_PPC_ISERIES */
1172 #ifdef CONFIG_PPC_PSERIES
1174 #endif /* CONFIG_PPC_PSERIES */
1177 * On pSeries and most other platforms, secondary processors spin
1178 * in the following code.
1179 * At entry, r3 = this processor's number (physical cpu id)
1181 _GLOBAL(generic_secondary_smp_init)
1184 /* turn on 64-bit mode */
1187 /* Set up a paca value for this processor. Since we have the
1188 * physical cpu id in r24, we need to search the pacas to find
1189 * which logical id maps to our physical one.
1191 LOAD_REG_IMMEDIATE(r13, paca) /* Get base vaddr of paca array */
1192 li r5,0 /* logical cpu id */
1193 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
1194 cmpw r6,r24 /* Compare to our id */
1196 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */
1201 mr r3,r24 /* not found, copy phys to r3 */
1202 b .kexec_wait /* next kernel might do better */
1204 2: mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1205 /* From now on, r24 is expected to be logical cpuid */
1208 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
1212 b 3b /* Never go on non-SMP */
1215 beq 3b /* Loop until told to go */
1217 sync /* order paca.run and cur_cpu_spec */
1219 /* See if we need to call a cpu state restore handler */
1220 LOAD_REG_IMMEDIATE(r23, cur_cpu_spec)
1222 ld r23,CPU_SPEC_RESTORE(r23)
1229 4: /* Create a temp kernel stack for use before relocation is on. */
1230 ld r1,PACAEMERGSP(r13)
1231 subi r1,r1,STACK_FRAME_OVERHEAD
1238 andi. r0,r3,MSR_IR|MSR_DR
1245 b . /* prevent speculative execution */
1249 * Here is our main kernel entry point. We support currently 2 kind of entries
1250 * depending on the value of r5.
1252 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
1255 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
1256 * DT block, r4 is a physical pointer to the kernel itself
1259 _GLOBAL(__start_initialization_multiplatform)
1261 * Are we booted from a PROM Of-type client-interface ?
1265 b .__boot_from_prom /* yes -> prom */
1267 /* Save parameters */
1271 /* Make sure we are running in 64 bits mode */
1274 /* Setup some critical 970 SPRs before switching MMU off */
1277 cmpwi r0,0x39 /* 970 */
1279 cmpwi r0,0x3c /* 970FX */
1281 cmpwi r0,0x44 /* 970MP */
1283 cmpwi r0,0x45 /* 970GX */
1285 1: bl .__cpu_preinit_ppc970
1288 /* Switch off MMU if not already */
1289 LOAD_REG_IMMEDIATE(r4, .__after_prom_start - KERNELBASE)
1292 b .__after_prom_start
1294 _INIT_STATIC(__boot_from_prom)
1295 /* Save parameters */
1303 * Align the stack to 16-byte boundary
1304 * Depending on the size and layout of the ELF sections in the initial
1305 * boot binary, the stack pointer will be unalignet on PowerMac
1309 /* Make sure we are running in 64 bits mode */
1312 /* put a relocation offset into r3 */
1315 LOAD_REG_IMMEDIATE(r2,__toc_start)
1319 /* Relocate the TOC from a virt addr to a real addr */
1322 /* Restore parameters */
1329 /* Do all of the interaction with OF client interface */
1331 /* We never return */
1334 _STATIC(__after_prom_start)
1337 * We need to run with __start at physical address PHYSICAL_START.
1338 * This will leave some code in the first 256B of
1339 * real memory, which are reserved for software use.
1340 * The remainder of the first page is loaded with the fixed
1341 * interrupt vectors. The next two pages are filled with
1342 * unknown exception placeholders.
1344 * Note: This process overwrites the OF exception vectors.
1345 * r26 == relocation offset
1350 LOAD_REG_IMMEDIATE(r27, KERNELBASE)
1352 LOAD_REG_IMMEDIATE(r3, PHYSICAL_START) /* target addr */
1354 // XXX FIXME: Use phys returned by OF (r30)
1355 add r4,r27,r26 /* source addr */
1356 /* current address of _start */
1357 /* i.e. where we are running */
1358 /* the source addr */
1360 cmpdi r4,0 /* In some cases the loader may */
1362 b .start_here_multiplatform /* have already put us at zero */
1363 /* so we can skip the copy. */
1364 1: LOAD_REG_IMMEDIATE(r5,copy_to_here) /* # bytes of memory to copy */
1367 li r6,0x100 /* Start offset, the first 0x100 */
1368 /* bytes were copied earlier. */
1370 bl .copy_and_flush /* copy the first n bytes */
1371 /* this includes the code being */
1372 /* executed here. */
1374 LOAD_REG_IMMEDIATE(r0, 4f) /* Jump to the copy of this code */
1375 mtctr r0 /* that we just made/relocated */
1378 4: LOAD_REG_IMMEDIATE(r5,klimit)
1380 ld r5,0(r5) /* get the value of klimit */
1382 bl .copy_and_flush /* copy the rest */
1383 b .start_here_multiplatform
1386 * Copy routine used to copy the kernel to start at physical address 0
1387 * and flush and invalidate the caches as needed.
1388 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
1389 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
1391 * Note: this routine *only* clobbers r0, r6 and lr
1393 _GLOBAL(copy_and_flush)
1396 4: li r0,8 /* Use the smallest common */
1397 /* denominator cache line */
1398 /* size. This results in */
1399 /* extra cache line flushes */
1400 /* but operation is correct. */
1401 /* Can't get cache line size */
1402 /* from NACA as it is being */
1405 mtctr r0 /* put # words/line in ctr */
1406 3: addi r6,r6,8 /* copy a cache line */
1410 dcbst r6,r3 /* write it to memory */
1412 icbi r6,r3 /* flush the icache line */
1424 #ifdef CONFIG_PPC_PMAC
1426 * On PowerMac, secondary processors starts from the reset vector, which
1427 * is temporarily turned into a call to one of the functions below.
1432 .globl __secondary_start_pmac_0
1433 __secondary_start_pmac_0:
1434 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
1444 _GLOBAL(pmac_secondary_start)
1445 /* turn on 64-bit mode */
1448 /* Copy some CPU settings from CPU 0 */
1449 bl .__restore_cpu_ppc970
1451 /* pSeries do that early though I don't think we really need it */
1454 mtmsrd r3 /* RI on */
1456 /* Set up a paca value for this processor. */
1457 LOAD_REG_IMMEDIATE(r4, paca) /* Get base vaddr of paca array */
1458 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
1459 add r13,r13,r4 /* for this processor. */
1460 mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1462 /* Create a temp kernel stack for use before relocation is on. */
1463 ld r1,PACAEMERGSP(r13)
1464 subi r1,r1,STACK_FRAME_OVERHEAD
1468 #endif /* CONFIG_PPC_PMAC */
1471 * This function is called after the master CPU has released the
1472 * secondary processors. The execution environment is relocation off.
1473 * The paca for this processor has the following fields initialized at
1475 * 1. Processor number
1476 * 2. Segment table pointer (virtual address)
1477 * On entry the following are set:
1478 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries
1479 * r24 = cpu# (in Linux terms)
1480 * r13 = paca virtual address
1481 * SPRG3 = paca virtual address
1483 .globl __secondary_start
1485 /* Set thread priority to MEDIUM */
1491 /* Do early setup for that CPU (stab, slb, hash table pointer) */
1492 bl .early_setup_secondary
1494 /* Initialize the kernel stack. Just a repeat for iSeries. */
1495 LOAD_REG_ADDR(r3, current_set)
1496 sldi r28,r24,3 /* get current_set[cpu#] */
1498 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1499 std r1,PACAKSAVE(r13)
1501 /* Clear backchain so we get nice backtraces */
1505 /* enable MMU and jump to start_secondary */
1506 LOAD_REG_ADDR(r3, .start_secondary_prolog)
1507 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
1508 #ifdef CONFIG_PPC_ISERIES
1509 BEGIN_FW_FTR_SECTION
1512 stb r8,PACAHARDIRQEN(r13)
1513 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1515 BEGIN_FW_FTR_SECTION
1516 stb r7,PACAHARDIRQEN(r13)
1517 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
1518 stb r7,PACASOFTIRQEN(r13)
1523 b . /* prevent speculative execution */
1526 * Running with relocation on at this point. All we want to do is
1527 * zero the stack back-chain pointer before going into C code.
1529 _GLOBAL(start_secondary_prolog)
1531 std r3,0(r1) /* Zero the stack frame pointer */
1537 * This subroutine clobbers r11 and r12
1539 _GLOBAL(enable_64b_mode)
1540 mfmsr r11 /* grab the current MSR */
1542 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
1545 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
1552 * This is where the main kernel code starts.
1554 _INIT_STATIC(start_here_multiplatform)
1555 /* get a new offset, now that the kernel has moved. */
1559 /* Clear out the BSS. It may have been done in prom_init,
1560 * already but that's irrelevant since prom_init will soon
1561 * be detached from the kernel completely. Besides, we need
1562 * to clear it now for kexec-style entry.
1564 LOAD_REG_IMMEDIATE(r11,__bss_stop)
1565 LOAD_REG_IMMEDIATE(r8,__bss_start)
1566 sub r11,r11,r8 /* bss size */
1567 addi r11,r11,7 /* round up to an even double word */
1568 rldicl. r11,r11,61,3 /* shift right by 3 */
1572 mtctr r11 /* zero this many doublewords */
1579 mtmsrd r6 /* RI on */
1581 /* The following gets the stack and TOC set up with the regs */
1582 /* pointing to the real addr of the kernel stack. This is */
1583 /* all done to support the C function call below which sets */
1584 /* up the htab. This is done because we have relocated the */
1585 /* kernel but are still running in real mode. */
1587 LOAD_REG_IMMEDIATE(r3,init_thread_union)
1590 /* set up a stack pointer (physical address) */
1591 addi r1,r3,THREAD_SIZE
1593 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1595 /* set up the TOC (physical address) */
1596 LOAD_REG_IMMEDIATE(r2,__toc_start)
1601 /* Do very early kernel initializations, including initial hash table,
1602 * stab and slb setup before we turn on relocation. */
1604 /* Restore parameters passed from prom_init/kexec */
1608 LOAD_REG_IMMEDIATE(r3, .start_here_common)
1609 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
1613 b . /* prevent speculative execution */
1615 /* This is where all platforms converge execution */
1616 _INIT_GLOBAL(start_here_common)
1617 /* relocation is on at this point */
1619 /* The following code sets up the SP and TOC now that we are */
1620 /* running with translation enabled. */
1622 LOAD_REG_IMMEDIATE(r3,init_thread_union)
1624 /* set up the stack */
1625 addi r1,r3,THREAD_SIZE
1627 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1631 std r1,PACAKSAVE(r13)
1635 /* Load up the kernel context */
1638 stb r5,PACASOFTIRQEN(r13) /* Soft Disabled */
1639 #ifdef CONFIG_PPC_ISERIES
1640 BEGIN_FW_FTR_SECTION
1642 ori r5,r5,MSR_EE /* Hard Enabled on iSeries*/
1645 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1647 stb r5,PACAHARDIRQEN(r13) /* Hard Disabled on others */
1655 * We put a few things here that have to be page-aligned.
1656 * This stuff goes at the beginning of the bss, which is page-aligned.
1662 .globl empty_zero_page
1666 .globl swapper_pg_dir
1668 .space PGD_TABLE_SIZE