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   1 /*
   2  * MPC8569E MDS Device Tree Source
   3  *
   4  * Copyright (C) 2009 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 / {
  15         model = "MPC8569EMDS";
  16         compatible = "fsl,MPC8569EMDS";
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         aliases {
  21                 serial0 = &serial0;
  22                 serial1 = &serial1;
  23                 ethernet0 = &enet0;
  24                 ethernet1 = &enet1;
  25                 ethernet2 = &enet2;
  26                 ethernet3 = &enet3;
  27                 ethernet5 = &enet5;
  28                 ethernet7 = &enet7;
  29                 pci1 = &pci1;
  30                 rapidio0 = &rio0;
  31         };
  32
  33         cpus {
  34                 #address-cells = <1>;
  35                 #size-cells = <0>;
  36
  37                 PowerPC,8569@0 {
  38                         device_type = "cpu";
  39                         reg = <0x0>;
  40                         d-cache-line-size = <32>;       // 32 bytes
  41                         i-cache-line-size = <32>;       // 32 bytes
  42                         d-cache-size = <0x8000>;                // L1, 32K
  43                         i-cache-size = <0x8000>;                // L1, 32K
  44                         timebase-frequency = <0>;
  45                         bus-frequency = <0>;
  46                         clock-frequency = <0>;
  47                         next-level-cache = <&L2>;
  48                 };
  49         };
  50
  51         memory {
  52                 device_type = "memory";
  53         };
  54
  55         localbus@e0005000 {
  56                 #address-cells = <2>;
  57                 #size-cells = <1>;
  58                 compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus";
  59                 reg = <0xe0005000 0x1000>;
  60                 interrupts = <19 2>;
  61                 interrupt-parent = <&mpic>;
  62
  63                 ranges = <0x0 0x0 0xfe000000 0x02000000
  64                           0x1 0x0 0xf8000000 0x00008000
  65                           0x2 0x0 0xf0000000 0x04000000
  66                           0x3 0x0 0xfc000000 0x00008000
  67                           0x4 0x0 0xf8008000 0x00008000
  68                           0x5 0x0 0xf8010000 0x00008000>;
  69
  70                 nor@0,0 {
  71                         #address-cells = <1>;
  72                         #size-cells = <1>;
  73                         compatible = "cfi-flash";
  74                         reg = <0x0 0x0 0x02000000>;
  75                         bank-width = <2>;
  76                         device-width = <1>;
  77                 };
  78
  79                 bcsr@1,0 {
  80                         compatible = "fsl,mpc8569mds-bcsr";
  81                         reg = <1 0 0x8000>;
  82                 };
  83
  84                 nand@3,0 {
  85                         compatible = "fsl,mpc8569-fcm-nand",
  86                                      "fsl,elbc-fcm-nand";
  87                         reg = <3 0 0x8000>;
  88                 };
  89
  90                 pib@4,0 {
  91                         compatible = "fsl,mpc8569mds-pib";
  92                         reg = <4 0 0x8000>;
  93                 };
  94
  95                 pib@5,0 {
  96                         compatible = "fsl,mpc8569mds-pib";
  97                         reg = <5 0 0x8000>;
  98                 };
  99         };
 100
 101         soc@e0000000 {
 102                 #address-cells = <1>;
 103                 #size-cells = <1>;
 104                 device_type = "soc";
 105                 compatible = "fsl,mpc8569-immr", "simple-bus";
 106                 ranges = <0x0 0xe0000000 0x100000>;
 107                 bus-frequency = <0>;
 108
 109                 ecm-law@0 {
 110                         compatible = "fsl,ecm-law";
 111                         reg = <0x0 0x1000>;
 112                         fsl,num-laws = <10>;
 113                 };
 114
 115                 ecm@1000 {
 116                         compatible = "fsl,mpc8569-ecm", "fsl,ecm";
 117                         reg = <0x1000 0x1000>;
 118                         interrupts = <17 2>;
 119                         interrupt-parent = <&mpic>;
 120                 };
 121
 122                 memory-controller@2000 {
 123                         compatible = "fsl,mpc8569-memory-controller";
 124                         reg = <0x2000 0x1000>;
 125                         interrupt-parent = <&mpic>;
 126                         interrupts = <18 2>;
 127                 };
 128
 129                 i2c@3000 {
 130                         #address-cells = <1>;
 131                         #size-cells = <0>;
 132                         cell-index = <0>;
 133                         compatible = "fsl-i2c";
 134                         reg = <0x3000 0x100>;
 135                         interrupts = <43 2>;
 136                         interrupt-parent = <&mpic>;
 137                         dfsrr;
 138
 139                         rtc@68 {
 140                                 compatible = "dallas,ds1374";
 141                                 reg = <0x68>;
 142                         };
 143                 };
 144
 145                 i2c@3100 {
 146                         #address-cells = <1>;
 147                         #size-cells = <0>;
 148                         cell-index = <1>;
 149                         compatible = "fsl-i2c";
 150                         reg = <0x3100 0x100>;
 151                         interrupts = <43 2>;
 152                         interrupt-parent = <&mpic>;
 153                         dfsrr;
 154                 };
 155
 156                 serial0: serial@4500 {
 157                         cell-index = <0>;
 158                         device_type = "serial";
 159                         compatible = "ns16550";
 160                         reg = <0x4500 0x100>;
 161                         clock-frequency = <0>;
 162                         interrupts = <42 2>;
 163                         interrupt-parent = <&mpic>;
 164                 };
 165
 166                 serial1: serial@4600 {
 167                         cell-index = <1>;
 168                         device_type = "serial";
 169                         compatible = "ns16550";
 170                         reg = <0x4600 0x100>;
 171                         clock-frequency = <0>;
 172                         interrupts = <42 2>;
 173                         interrupt-parent = <&mpic>;
 174                 };
 175
 176                 L2: l2-cache-controller@20000 {
 177                         compatible = "fsl,mpc8569-l2-cache-controller";
 178                         reg = <0x20000 0x1000>;
 179                         cache-line-size = <32>; // 32 bytes
 180                         cache-size = <0x80000>; // L2, 512K
 181                         interrupt-parent = <&mpic>;
 182                         interrupts = <16 2>;
 183                 };
 184
 185                 dma@21300 {
 186                         #address-cells = <1>;
 187                         #size-cells = <1>;
 188                         compatible = "fsl,mpc8569-dma", "fsl,eloplus-dma";
 189                         reg = <0x21300 0x4>;
 190                         ranges = <0x0 0x21100 0x200>;
 191                         cell-index = <0>;
 192                         dma-channel@0 {
 193                                 compatible = "fsl,mpc8569-dma-channel",
 194                                                 "fsl,eloplus-dma-channel";
 195                                 reg = <0x0 0x80>;
 196                                 cell-index = <0>;
 197                                 interrupt-parent = <&mpic>;
 198                                 interrupts = <20 2>;
 199                         };
 200                         dma-channel@80 {
 201                                 compatible = "fsl,mpc8569-dma-channel",
 202                                                 "fsl,eloplus-dma-channel";
 203                                 reg = <0x80 0x80>;
 204                                 cell-index = <1>;
 205                                 interrupt-parent = <&mpic>;
 206                                 interrupts = <21 2>;
 207                         };
 208                         dma-channel@100 {
 209                                 compatible = "fsl,mpc8569-dma-channel",
 210                                                 "fsl,eloplus-dma-channel";
 211                                 reg = <0x100 0x80>;
 212                                 cell-index = <2>;
 213                                 interrupt-parent = <&mpic>;
 214                                 interrupts = <22 2>;
 215                         };
 216                         dma-channel@180 {
 217                                 compatible = "fsl,mpc8569-dma-channel",
 218                                                 "fsl,eloplus-dma-channel";
 219                                 reg = <0x180 0x80>;
 220                                 cell-index = <3>;
 221                                 interrupt-parent = <&mpic>;
 222                                 interrupts = <23 2>;
 223                         };
 224                 };
 225
 226                 sdhci@2e000 {
 227                         compatible = "fsl,mpc8569-esdhc", "fsl,esdhc";
 228                         reg = <0x2e000 0x1000>;
 229                         interrupts = <72 0x8>;
 230                         interrupt-parent = <&mpic>;
 231                         /* Filled in by U-Boot */
 232                         clock-frequency = <0>;
 233                         status = "disabled";
 234                 };
 235
 236                 crypto@30000 {
 237                         compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
 238                                 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
 239                         reg = <0x30000 0x10000>;
 240                         interrupts = <45 2 58 2>;
 241                         interrupt-parent = <&mpic>;
 242                         fsl,num-channels = <4>;
 243                         fsl,channel-fifo-len = <24>;
 244                         fsl,exec-units-mask = <0xbfe>;
 245                         fsl,descriptor-types-mask = <0x3ab0ebf>;
 246                 };
 247
 248                 mpic: pic@40000 {
 249                         interrupt-controller;
 250                         #address-cells = <0>;
 251                         #interrupt-cells = <2>;
 252                         reg = <0x40000 0x40000>;
 253                         compatible = "chrp,open-pic";
 254                         device_type = "open-pic";
 255                 };
 256
 257                 msi@41600 {
 258                         compatible = "fsl,mpc8568-msi", "fsl,mpic-msi";
 259                         reg = <0x41600 0x80>;
 260                         msi-available-ranges = <0 0x100>;
 261                         interrupts = <
 262                                 0xe0 0
 263                                 0xe1 0
 264                                 0xe2 0
 265                                 0xe3 0
 266                                 0xe4 0
 267                                 0xe5 0
 268                                 0xe6 0
 269                                 0xe7 0>;
 270                         interrupt-parent = <&mpic>;
 271                 };
 272
 273                 global-utilities@e0000 {
 274                         compatible = "fsl,mpc8569-guts";
 275                         reg = <0xe0000 0x1000>;
 276                         fsl,has-rstcr;
 277                 };
 278
 279                 par_io@e0100 {
 280                         #address-cells = <1>;
 281                         #size-cells = <1>;
 282                         reg = <0xe0100 0x100>;
 283                         ranges = <0x0 0xe0100 0x100>;
 284                         device_type = "par_io";
 285                         num-ports = <7>;
 286
 287                         qe_pio_e: gpio-controller@80 {
 288                                 #gpio-cells = <2>;
 289                                 compatible = "fsl,mpc8569-qe-pario-bank",
 290                                              "fsl,mpc8323-qe-pario-bank";
 291                                 reg = <0x80 0x18>;
 292                                 gpio-controller;
 293                         };
 294
 295                         pio1: ucc_pin@01 {
 296                                 pio-map = <
 297                         /* port  pin  dir  open_drain  assignment  has_irq */
 298                                         0x2  0x1f 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
 299                                         0x2  0x1e 0x3  0x0  0x2  0x0    /* QE_MUX_MDIO */
 300                                         0x2  0x0b 0x2  0x0  0x1  0x0    /* CLK12*/
 301                                         0x0  0x0  0x1  0x0  0x3  0x0    /* ENET1_TXD0_SER1_TXD0 */
 302                                         0x0  0x1  0x1  0x0  0x3  0x0    /* ENET1_TXD1_SER1_TXD1 */
 303                                         0x0  0x2  0x1  0x0  0x1  0x0    /* ENET1_TXD2_SER1_TXD2 */
 304                                         0x0  0x3  0x1  0x0  0x2  0x0    /* ENET1_TXD3_SER1_TXD3 */
 305                                         0x0  0x6  0x2  0x0  0x3  0x0    /* ENET1_RXD0_SER1_RXD0 */
 306                                         0x0  0x7  0x2  0x0  0x1  0x0    /* ENET1_RXD1_SER1_RXD1 */
 307                                         0x0  0x8  0x2  0x0  0x2  0x0    /* ENET1_RXD2_SER1_RXD2 */
 308                                         0x0  0x9  0x2  0x0  0x2  0x0    /* ENET1_RXD3_SER1_RXD3 */
 309                                         0x0  0x4  0x1  0x0  0x2  0x0    /* ENET1_TX_EN_SER1_RTS_B */
 310                                         0x0  0xc  0x2  0x0  0x3  0x0    /* ENET1_RX_DV_SER1_CTS_B */
 311                                         0x2  0x8  0x2  0x0  0x1  0x0    /* ENET1_GRXCLK */
 312                                         0x2  0x14 0x1  0x0  0x2  0x0>;  /* ENET1_GTXCLK */
 313                         };
 314
 315                         pio2: ucc_pin@02 {
 316                                 pio-map = <
 317                         /* port  pin  dir  open_drain  assignment  has_irq */
 318                                         0x2  0x1f 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
 319                                         0x2  0x1e 0x3  0x0  0x2  0x0    /* QE_MUX_MDIO */
 320                                         0x2  0x10 0x2  0x0  0x3  0x0    /* CLK17 */
 321                                         0x0  0xe  0x1  0x0  0x2  0x0    /* ENET2_TXD0_SER2_TXD0 */
 322                                         0x0  0xf  0x1  0x0  0x2  0x0    /* ENET2_TXD1_SER2_TXD1 */
 323                                         0x0  0x10 0x1  0x0  0x1  0x0    /* ENET2_TXD2_SER2_TXD2 */
 324                                         0x0  0x11 0x1  0x0  0x1  0x0    /* ENET2_TXD3_SER2_TXD3 */
 325                                         0x0  0x14 0x2  0x0  0x2  0x0    /* ENET2_RXD0_SER2_RXD0 */
 326                                         0x0  0x15 0x2  0x0  0x1  0x0    /* ENET2_RXD1_SER2_RXD1 */
 327                                         0x0  0x16 0x2  0x0  0x1  0x0    /* ENET2_RXD2_SER2_RXD2 */
 328                                         0x0  0x17 0x2  0x0  0x1  0x0    /* ENET2_RXD3_SER2_RXD3 */
 329                                         0x0  0x12 0x1  0x0  0x2  0x0    /* ENET2_TX_EN_SER2_RTS_B */
 330                                         0x0  0x1a 0x2  0x0  0x3  0x0    /* ENET2_RX_DV_SER2_CTS_B */
 331                                         0x2  0x3  0x2  0x0  0x1  0x0    /* ENET2_GRXCLK */
 332                                         0x2  0x2 0x1  0x0  0x2  0x0>;   /* ENET2_GTXCLK */
 333                         };
 334
 335                         pio3: ucc_pin@03 {
 336                                 pio-map = <
 337                         /* port  pin  dir  open_drain  assignment  has_irq */
 338                                         0x2  0x1f 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
 339                                         0x2  0x1e 0x3  0x0  0x2  0x0    /* QE_MUX_MDIO */
 340                                         0x2  0x0b 0x2  0x0  0x1  0x0    /* CLK12*/
 341                                         0x0  0x1d 0x1  0x0  0x2  0x0    /* ENET3_TXD0_SER3_TXD0 */
 342                                         0x0  0x1e 0x1  0x0  0x3  0x0    /* ENET3_TXD1_SER3_TXD1 */
 343                                         0x0  0x1f 0x1  0x0  0x2  0x0    /* ENET3_TXD2_SER3_TXD2 */
 344                                         0x1  0x0  0x1  0x0  0x3  0x0    /* ENET3_TXD3_SER3_TXD3 */
 345                                         0x1  0x3  0x2  0x0  0x3  0x0    /* ENET3_RXD0_SER3_RXD0 */
 346                                         0x1  0x4  0x2  0x0  0x1  0x0    /* ENET3_RXD1_SER3_RXD1 */
 347                                         0x1  0x5  0x2  0x0  0x2  0x0    /* ENET3_RXD2_SER3_RXD2 */
 348                                         0x1  0x6  0x2  0x0  0x3  0x0    /* ENET3_RXD3_SER3_RXD3 */
 349                                         0x1  0x1  0x1  0x0  0x1  0x0    /* ENET3_TX_EN_SER3_RTS_B */
 350                                         0x1  0x9  0x2  0x0  0x3  0x0    /* ENET3_RX_DV_SER3_CTS_B */
 351                                         0x2  0x9  0x2  0x0  0x2  0x0    /* ENET3_GRXCLK */
 352                                         0x2  0x19 0x1  0x0  0x2  0x0>;  /* ENET3_GTXCLK */
 353                         };
 354
 355                         pio4: ucc_pin@04 {
 356                                 pio-map = <
 357                         /* port  pin  dir  open_drain  assignment  has_irq */
 358                                         0x2  0x1f 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
 359                                         0x2  0x1e 0x3  0x0  0x2  0x0    /* QE_MUX_MDIO */
 360                                         0x2  0x10 0x2  0x0  0x3  0x0    /* CLK17 */
 361                                         0x1  0xc  0x1  0x0  0x2  0x0    /* ENET4_TXD0_SER4_TXD0 */
 362                                         0x1  0xd  0x1  0x0  0x2  0x0    /* ENET4_TXD1_SER4_TXD1 */
 363                                         0x1  0xe  0x1  0x0  0x1  0x0    /* ENET4_TXD2_SER4_TXD2 */
 364                                         0x1  0xf  0x1  0x0  0x2  0x0    /* ENET4_TXD3_SER4_TXD3 */
 365                                         0x1  0x12 0x2  0x0  0x2  0x0    /* ENET4_RXD0_SER4_RXD0 */
 366                                         0x1  0x13 0x2  0x0  0x1  0x0    /* ENET4_RXD1_SER4_RXD1 */
 367                                         0x1  0x14 0x2  0x0  0x1  0x0    /* ENET4_RXD2_SER4_RXD2 */
 368                                         0x1  0x15 0x2  0x0  0x2  0x0    /* ENET4_RXD3_SER4_RXD3 */
 369                                         0x1  0x10 0x1  0x0  0x2  0x0    /* ENET4_TX_EN_SER4_RTS_B */
 370                                         0x1  0x18 0x2  0x0  0x3  0x0    /* ENET4_RX_DV_SER4_CTS_B */
 371                                         0x2  0x11 0x2  0x0  0x2  0x0    /* ENET4_GRXCLK */
 372                                         0x2  0x18 0x1  0x0  0x2  0x0>;  /* ENET4_GTXCLK */
 373                         };
 374                 };
 375         };
 376
 377         qe@e0080000 {
 378                 #address-cells = <1>;
 379                 #size-cells = <1>;
 380                 device_type = "qe";
 381                 compatible = "fsl,qe";
 382                 ranges = <0x0 0xe0080000 0x40000>;
 383                 reg = <0xe0080000 0x480>;
 384                 brg-frequency = <0>;
 385                 bus-frequency = <0>;
 386                 fsl,qe-num-riscs = <4>;
 387                 fsl,qe-num-snums = <46>;
 388
 389                 qeic: interrupt-controller@80 {
 390                         interrupt-controller;
 391                         compatible = "fsl,qe-ic";
 392                         #address-cells = <0>;
 393                         #interrupt-cells = <1>;
 394                         reg = <0x80 0x80>;
 395                         interrupts = <46 2 46 2>; //high:30 low:30
 396                         interrupt-parent = <&mpic>;
 397                 };
 398
 399                 spi@4c0 {
 400                         #address-cells = <1>;
 401                         #size-cells = <0>;
 402                         compatible = "fsl,mpc8569-qe-spi", "fsl,spi";
 403                         reg = <0x4c0 0x40>;
 404                         cell-index = <0>;
 405                         interrupts = <2>;
 406                         interrupt-parent = <&qeic>;
 407                         gpios = <&qe_pio_e 30 0>;
 408                         mode = "cpu-qe";
 409
 410                         serial-flash@0 {
 411                                 compatible = "stm,m25p40";
 412                                 reg = <0>;
 413                                 spi-max-frequency = <25000000>;
 414                         };
 415                 };
 416
 417                 spi@500 {
 418                         cell-index = <1>;
 419                         compatible = "fsl,spi";
 420                         reg = <0x500 0x40>;
 421                         interrupts = <1>;
 422                         interrupt-parent = <&qeic>;
 423                         mode = "cpu";
 424                 };
 425
 426                 enet0: ucc@2000 {
 427                         device_type = "network";
 428                         compatible = "ucc_geth";
 429                         cell-index = <1>;
 430                         reg = <0x2000 0x200>;
 431                         interrupts = <32>;
 432                         interrupt-parent = <&qeic>;
 433                         local-mac-address = [ 00 00 00 00 00 00 ];
 434                         rx-clock-name = "none";
 435                         tx-clock-name = "clk12";
 436                         pio-handle = <&pio1>;
 437                         phy-handle = <&qe_phy0>;
 438                         phy-connection-type = "rgmii-id";
 439                 };
 440
 441                 mdio@2120 {
 442                         #address-cells = <1>;
 443                         #size-cells = <0>;
 444                         reg = <0x2120 0x18>;
 445                         compatible = "fsl,ucc-mdio";
 446
 447                         qe_phy0: ethernet-phy@07 {
 448                                 interrupt-parent = <&mpic>;
 449                                 interrupts = <1 1>;
 450                                 reg = <0x7>;
 451                                 device_type = "ethernet-phy";
 452                         };
 453                         qe_phy1: ethernet-phy@01 {
 454                                 interrupt-parent = <&mpic>;
 455                                 interrupts = <2 1>;
 456                                 reg = <0x1>;
 457                                 device_type = "ethernet-phy";
 458                         };
 459                         qe_phy2: ethernet-phy@02 {
 460                                 interrupt-parent = <&mpic>;
 461                                 interrupts = <3 1>;
 462                                 reg = <0x2>;
 463                                 device_type = "ethernet-phy";
 464                         };
 465                         qe_phy3: ethernet-phy@03 {
 466                                 interrupt-parent = <&mpic>;
 467                                 interrupts = <4 1>;
 468                                 reg = <0x3>;
 469                                 device_type = "ethernet-phy";
 470                         };
 471                         qe_phy5: ethernet-phy@04 {
 472                                 interrupt-parent = <&mpic>;
 473                                 reg = <0x04>;
 474                                 device_type = "ethernet-phy";
 475                         };
 476                         qe_phy7: ethernet-phy@06 {
 477                                 interrupt-parent = <&mpic>;
 478                                 reg = <0x6>;
 479                                 device_type = "ethernet-phy";
 480                         };
 481                 };
 482                 mdio@3520 {
 483                         #address-cells = <1>;
 484                         #size-cells = <0>;
 485                         reg = <0x3520 0x18>;
 486                         compatible = "fsl,ucc-mdio";
 487
 488                         tbi0: tbi-phy@15 {
 489                         reg = <0x15>;
 490                         device_type = "tbi-phy";
 491                         };
 492                 };
 493                 mdio@3720 {
 494                         #address-cells = <1>;
 495                         #size-cells = <0>;
 496                         reg = <0x3720 0x38>;
 497                         compatible = "fsl,ucc-mdio";
 498                         tbi1: tbi-phy@17 {
 499                                 reg = <0x17>;
 500                                 device_type = "tbi-phy";
 501                         };
 502                 };
 503
 504                 enet2: ucc@2200 {
 505                         device_type = "network";
 506                         compatible = "ucc_geth";
 507                         cell-index = <3>;
 508                         reg = <0x2200 0x200>;
 509                         interrupts = <34>;
 510                         interrupt-parent = <&qeic>;
 511                         local-mac-address = [ 00 00 00 00 00 00 ];
 512                         rx-clock-name = "none";
 513                         tx-clock-name = "clk12";
 514                         pio-handle = <&pio3>;
 515                         phy-handle = <&qe_phy2>;
 516                         phy-connection-type = "rgmii-id";
 517                 };
 518
 519                 enet1: ucc@3000 {
 520                         device_type = "network";
 521                         compatible = "ucc_geth";
 522                         cell-index = <2>;
 523                         reg = <0x3000 0x200>;
 524                         interrupts = <33>;
 525                         interrupt-parent = <&qeic>;
 526                         local-mac-address = [ 00 00 00 00 00 00 ];
 527                         rx-clock-name = "none";
 528                         tx-clock-name = "clk17";
 529                         pio-handle = <&pio2>;
 530                         phy-handle = <&qe_phy1>;
 531                         phy-connection-type = "rgmii-id";
 532                 };
 533
 534                 enet3: ucc@3200 {
 535                         device_type = "network";
 536                         compatible = "ucc_geth";
 537                         cell-index = <4>;
 538                         reg = <0x3200 0x200>;
 539                         interrupts = <35>;
 540                         interrupt-parent = <&qeic>;
 541                         local-mac-address = [ 00 00 00 00 00 00 ];
 542                         rx-clock-name = "none";
 543                         tx-clock-name = "clk17";
 544                         pio-handle = <&pio4>;
 545                         phy-handle = <&qe_phy3>;
 546                         phy-connection-type = "rgmii-id";
 547                 };
 548
 549                 enet5: ucc@3400 {
 550                         device_type = "network";
 551                         compatible = "ucc_geth";
 552                         cell-index = <6>;
 553                         reg = <0x3400 0x200>;
 554                         interrupts = <41>;
 555                         interrupt-parent = <&qeic>;
 556                         local-mac-address = [ 00 00 00 00 00 00 ];
 557                         rx-clock-name = "none";
 558                         tx-clock-name = "none";
 559                         tbi-handle = <&tbi0>;
 560                         phy-handle = <&qe_phy5>;
 561                         phy-connection-type = "sgmii";
 562                 };
 563
 564                 enet7: ucc@3600 {
 565                         device_type = "network";
 566                         compatible = "ucc_geth";
 567                         cell-index = <8>;
 568                         reg = <0x3600 0x200>;
 569                         interrupts = <43>;
 570                         interrupt-parent = <&qeic>;
 571                         local-mac-address = [ 00 00 00 00 00 00 ];
 572                         rx-clock-name = "none";
 573                         tx-clock-name = "none";
 574                         tbi-handle = <&tbi1>;
 575                         phy-handle = <&qe_phy7>;
 576                         phy-connection-type = "sgmii";
 577                 };
 578
 579                 muram@10000 {
 580                         #address-cells = <1>;
 581                         #size-cells = <1>;
 582                         compatible = "fsl,qe-muram", "fsl,cpm-muram";
 583                         ranges = <0x0 0x10000 0x20000>;
 584
 585                         data-only@0 {
 586                                 compatible = "fsl,qe-muram-data",
 587                                              "fsl,cpm-muram-data";
 588                                 reg = <0x0 0x20000>;
 589                         };
 590                 };
 591
 592         };
 593
 594         /* PCI Express */
 595         pci1: pcie@e000a000 {
 596                 compatible = "fsl,mpc8548-pcie";
 597                 device_type = "pci";
 598                 #interrupt-cells = <1>;
 599                 #size-cells = <2>;
 600                 #address-cells = <3>;
 601                 reg = <0xe000a000 0x1000>;
 602                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 603                 interrupt-map = <
 604                         /* IDSEL 0x0 (PEX) */
 605                         00000 0x0 0x0 0x1 &mpic 0x0 0x1
 606                         00000 0x0 0x0 0x2 &mpic 0x1 0x1
 607                         00000 0x0 0x0 0x3 &mpic 0x2 0x1
 608                         00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 609
 610                 interrupt-parent = <&mpic>;
 611                 interrupts = <26 2>;
 612                 bus-range = <0 255>;
 613                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
 614                           0x1000000 0x0 0x00000000 0xe2800000 0x0 0x00800000>;
 615                 clock-frequency = <33333333>;
 616                 pcie@0 {
 617                         reg = <0x0 0x0 0x0 0x0 0x0>;
 618                         #size-cells = <2>;
 619                         #address-cells = <3>;
 620                         device_type = "pci";
 621                         ranges = <0x2000000 0x0 0xa0000000
 622                                   0x2000000 0x0 0xa0000000
 623                                   0x0 0x10000000
 624
 625                                   0x1000000 0x0 0x0
 626                                   0x1000000 0x0 0x0
 627                                   0x0 0x800000>;
 628                 };
 629         };
 630
 631         rio0: rapidio@e00c00000 {
 632                 #address-cells = <2>;
 633                 #size-cells = <2>;
 634                 compatible = "fsl,mpc8569-rapidio", "fsl,rapidio-delta";
 635                 reg = <0xe00c0000 0x20000>;
 636                 ranges = <0x0 0x0 0xc0000000 0x0 0x20000000>;
 637                 interrupts = <48 2 /* error     */
 638                               49 2 /* bell_outb */
 639                               50 2 /* bell_inb  */
 640                               53 2 /* msg1_tx   */
 641                               54 2 /* msg1_rx   */
 642                               55 2 /* msg2_tx   */
 643                               56 2 /* msg2_rx   */>;
 644                 interrupt-parent = <&mpic>;
 645         };
 646 };