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   1 /*
   2  * MPC8569E MDS Device Tree Source
   3  *
   4  * Copyright (C) 2009 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 / {
  15         model = "MPC8569EMDS";
  16         compatible = "fsl,MPC8569EMDS";
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         aliases {
  21                 serial0 = &serial0;
  22                 serial1 = &serial1;
  23                 ethernet0 = &enet0;
  24                 ethernet1 = &enet1;
  25                 ethernet2 = &enet2;
  26                 ethernet3 = &enet3;
  27                 pci1 = &pci1;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 PowerPC,8569@0 {
  35                         device_type = "cpu";
  36                         reg = <0x0>;
  37                         d-cache-line-size = <32>;       // 32 bytes
  38                         i-cache-line-size = <32>;       // 32 bytes
  39                         d-cache-size = <0x8000>;                // L1, 32K
  40                         i-cache-size = <0x8000>;                // L1, 32K
  41                         timebase-frequency = <0>;
  42                         bus-frequency = <0>;
  43                         clock-frequency = <0>;
  44                         next-level-cache = <&L2>;
  45                 };
  46         };
  47
  48         memory {
  49                 device_type = "memory";
  50         };
  51
  52         localbus@e0005000 {
  53                 #address-cells = <2>;
  54                 #size-cells = <1>;
  55                 compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus";
  56                 reg = <0xe0005000 0x1000>;
  57                 interrupts = <19 2>;
  58                 interrupt-parent = <&mpic>;
  59
  60                 ranges = <0x0 0x0 0xfe000000 0x02000000
  61                           0x1 0x0 0xf8000000 0x00008000
  62                           0x2 0x0 0xf0000000 0x04000000
  63                           0x3 0x0 0xfc000000 0x00008000
  64                           0x4 0x0 0xf8008000 0x00008000
  65                           0x5 0x0 0xf8010000 0x00008000>;
  66
  67                 nor@0,0 {
  68                         #address-cells = <1>;
  69                         #size-cells = <1>;
  70                         compatible = "cfi-flash";
  71                         reg = <0x0 0x0 0x02000000>;
  72                         bank-width = <2>;
  73                         device-width = <1>;
  74                 };
  75
  76                 bcsr@1,0 {
  77                         compatible = "fsl,mpc8569mds-bcsr";
  78                         reg = <1 0 0x8000>;
  79                 };
  80
  81                 nand@3,0 {
  82                         compatible = "fsl,mpc8569-fcm-nand",
  83                                      "fsl,elbc-fcm-nand";
  84                         reg = <3 0 0x8000>;
  85                 };
  86
  87                 pib@4,0 {
  88                         compatible = "fsl,mpc8569mds-pib";
  89                         reg = <4 0 0x8000>;
  90                 };
  91
  92                 pib@5,0 {
  93                         compatible = "fsl,mpc8569mds-pib";
  94                         reg = <5 0 0x8000>;
  95                 };
  96         };
  97
  98         soc@e0000000 {
  99                 #address-cells = <1>;
 100                 #size-cells = <1>;
 101                 device_type = "soc";
 102                 compatible = "fsl,mpc8569-immr", "simple-bus";
 103                 ranges = <0x0 0xe0000000 0x100000>;
 104                 bus-frequency = <0>;
 105
 106                 ecm-law@0 {
 107                         compatible = "fsl,ecm-law";
 108                         reg = <0x0 0x1000>;
 109                         fsl,num-laws = <10>;
 110                 };
 111
 112                 ecm@1000 {
 113                         compatible = "fsl,mpc8569-ecm", "fsl,ecm";
 114                         reg = <0x1000 0x1000>;
 115                         interrupts = <17 2>;
 116                         interrupt-parent = <&mpic>;
 117                 };
 118
 119                 memory-controller@2000 {
 120                         compatible = "fsl,mpc8569-memory-controller";
 121                         reg = <0x2000 0x1000>;
 122                         interrupt-parent = <&mpic>;
 123                         interrupts = <18 2>;
 124                 };
 125
 126                 i2c@3000 {
 127                         #address-cells = <1>;
 128                         #size-cells = <0>;
 129                         cell-index = <0>;
 130                         compatible = "fsl-i2c";
 131                         reg = <0x3000 0x100>;
 132                         interrupts = <43 2>;
 133                         interrupt-parent = <&mpic>;
 134                         dfsrr;
 135
 136                         rtc@68 {
 137                                 compatible = "dallas,ds1374";
 138                                 reg = <0x68>;
 139                         };
 140                 };
 141
 142                 i2c@3100 {
 143                         #address-cells = <1>;
 144                         #size-cells = <0>;
 145                         cell-index = <1>;
 146                         compatible = "fsl-i2c";
 147                         reg = <0x3100 0x100>;
 148                         interrupts = <43 2>;
 149                         interrupt-parent = <&mpic>;
 150                         dfsrr;
 151                 };
 152
 153                 serial0: serial@4500 {
 154                         cell-index = <0>;
 155                         device_type = "serial";
 156                         compatible = "ns16550";
 157                         reg = <0x4500 0x100>;
 158                         clock-frequency = <0>;
 159                         interrupts = <42 2>;
 160                         interrupt-parent = <&mpic>;
 161                 };
 162
 163                 serial1: serial@4600 {
 164                         cell-index = <1>;
 165                         device_type = "serial";
 166                         compatible = "ns16550";
 167                         reg = <0x4600 0x100>;
 168                         clock-frequency = <0>;
 169                         interrupts = <42 2>;
 170                         interrupt-parent = <&mpic>;
 171                 };
 172
 173                 L2: l2-cache-controller@20000 {
 174                         compatible = "fsl,mpc8569-l2-cache-controller";
 175                         reg = <0x20000 0x1000>;
 176                         cache-line-size = <32>; // 32 bytes
 177                         cache-size = <0x80000>; // L2, 512K
 178                         interrupt-parent = <&mpic>;
 179                         interrupts = <16 2>;
 180                 };
 181
 182                 dma@21300 {
 183                         #address-cells = <1>;
 184                         #size-cells = <1>;
 185                         compatible = "fsl,mpc8569-dma", "fsl,eloplus-dma";
 186                         reg = <0x21300 0x4>;
 187                         ranges = <0x0 0x21100 0x200>;
 188                         cell-index = <0>;
 189                         dma-channel@0 {
 190                                 compatible = "fsl,mpc8569-dma-channel",
 191                                                 "fsl,eloplus-dma-channel";
 192                                 reg = <0x0 0x80>;
 193                                 cell-index = <0>;
 194                                 interrupt-parent = <&mpic>;
 195                                 interrupts = <20 2>;
 196                         };
 197                         dma-channel@80 {
 198                                 compatible = "fsl,mpc8569-dma-channel",
 199                                                 "fsl,eloplus-dma-channel";
 200                                 reg = <0x80 0x80>;
 201                                 cell-index = <1>;
 202                                 interrupt-parent = <&mpic>;
 203                                 interrupts = <21 2>;
 204                         };
 205                         dma-channel@100 {
 206                                 compatible = "fsl,mpc8569-dma-channel",
 207                                                 "fsl,eloplus-dma-channel";
 208                                 reg = <0x100 0x80>;
 209                                 cell-index = <2>;
 210                                 interrupt-parent = <&mpic>;
 211                                 interrupts = <22 2>;
 212                         };
 213                         dma-channel@180 {
 214                                 compatible = "fsl,mpc8569-dma-channel",
 215                                                 "fsl,eloplus-dma-channel";
 216                                 reg = <0x180 0x80>;
 217                                 cell-index = <3>;
 218                                 interrupt-parent = <&mpic>;
 219                                 interrupts = <23 2>;
 220                         };
 221                 };
 222
 223                 sdhci@2e000 {
 224                         compatible = "fsl,mpc8569-esdhc", "fsl,esdhc";
 225                         reg = <0x2e000 0x1000>;
 226                         interrupts = <72 0x8>;
 227                         interrupt-parent = <&mpic>;
 228                         /* Filled in by U-Boot */
 229                         clock-frequency = <0>;
 230                         status = "disabled";
 231                 };
 232
 233                 crypto@30000 {
 234                         compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
 235                                 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
 236                         reg = <0x30000 0x10000>;
 237                         interrupts = <45 2 58 2>;
 238                         interrupt-parent = <&mpic>;
 239                         fsl,num-channels = <4>;
 240                         fsl,channel-fifo-len = <24>;
 241                         fsl,exec-units-mask = <0xbfe>;
 242                         fsl,descriptor-types-mask = <0x3ab0ebf>;
 243                 };
 244
 245                 mpic: pic@40000 {
 246                         interrupt-controller;
 247                         #address-cells = <0>;
 248                         #interrupt-cells = <2>;
 249                         reg = <0x40000 0x40000>;
 250                         compatible = "chrp,open-pic";
 251                         device_type = "open-pic";
 252                 };
 253
 254                 global-utilities@e0000 {
 255                         compatible = "fsl,mpc8569-guts";
 256                         reg = <0xe0000 0x1000>;
 257                         fsl,has-rstcr;
 258                 };
 259
 260                 par_io@e0100 {
 261                         reg = <0xe0100 0x100>;
 262                         device_type = "par_io";
 263                         num-ports = <7>;
 264
 265                         pio1: ucc_pin@01 {
 266                                 pio-map = <
 267                         /* port  pin  dir  open_drain  assignment  has_irq */
 268                                         0x2  0x1f 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
 269                                         0x2  0x1e 0x3  0x0  0x2  0x0    /* QE_MUX_MDIO */
 270                                         0x2  0x0b 0x2  0x0  0x1  0x0    /* CLK12*/
 271                                         0x0  0x0  0x1  0x0  0x3  0x0    /* ENET1_TXD0_SER1_TXD0 */
 272                                         0x0  0x1  0x1  0x0  0x3  0x0    /* ENET1_TXD1_SER1_TXD1 */
 273                                         0x0  0x2  0x1  0x0  0x1  0x0    /* ENET1_TXD2_SER1_TXD2 */
 274                                         0x0  0x3  0x1  0x0  0x2  0x0    /* ENET1_TXD3_SER1_TXD3 */
 275                                         0x0  0x6  0x2  0x0  0x3  0x0    /* ENET1_RXD0_SER1_RXD0 */
 276                                         0x0  0x7  0x2  0x0  0x1  0x0    /* ENET1_RXD1_SER1_RXD1 */
 277                                         0x0  0x8  0x2  0x0  0x2  0x0    /* ENET1_RXD2_SER1_RXD2 */
 278                                         0x0  0x9  0x2  0x0  0x2  0x0    /* ENET1_RXD3_SER1_RXD3 */
 279                                         0x0  0x4  0x1  0x0  0x2  0x0    /* ENET1_TX_EN_SER1_RTS_B */
 280                                         0x0  0xc  0x2  0x0  0x3  0x0    /* ENET1_RX_DV_SER1_CTS_B */
 281                                         0x2  0x8  0x2  0x0  0x1  0x0    /* ENET1_GRXCLK */
 282                                         0x2  0x14 0x1  0x0  0x2  0x0>;  /* ENET1_GTXCLK */
 283                         };
 284
 285                         pio2: ucc_pin@02 {
 286                                 pio-map = <
 287                         /* port  pin  dir  open_drain  assignment  has_irq */
 288                                         0x2  0x1f 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
 289                                         0x2  0x1e 0x3  0x0  0x2  0x0    /* QE_MUX_MDIO */
 290                                         0x2  0x10 0x2  0x0  0x3  0x0    /* CLK17 */
 291                                         0x0  0xe  0x1  0x0  0x2  0x0    /* ENET2_TXD0_SER2_TXD0 */
 292                                         0x0  0xf  0x1  0x0  0x2  0x0    /* ENET2_TXD1_SER2_TXD1 */
 293                                         0x0  0x10 0x1  0x0  0x1  0x0    /* ENET2_TXD2_SER2_TXD2 */
 294                                         0x0  0x11 0x1  0x0  0x1  0x0    /* ENET2_TXD3_SER2_TXD3 */
 295                                         0x0  0x14 0x2  0x0  0x2  0x0    /* ENET2_RXD0_SER2_RXD0 */
 296                                         0x0  0x15 0x2  0x0  0x1  0x0    /* ENET2_RXD1_SER2_RXD1 */
 297                                         0x0  0x16 0x2  0x0  0x1  0x0    /* ENET2_RXD2_SER2_RXD2 */
 298                                         0x0  0x17 0x2  0x0  0x1  0x0    /* ENET2_RXD3_SER2_RXD3 */
 299                                         0x0  0x12 0x1  0x0  0x2  0x0    /* ENET2_TX_EN_SER2_RTS_B */
 300                                         0x0  0x1a 0x2  0x0  0x3  0x0    /* ENET2_RX_DV_SER2_CTS_B */
 301                                         0x2  0x3  0x2  0x0  0x1  0x0    /* ENET2_GRXCLK */
 302                                         0x2  0x2 0x1  0x0  0x2  0x0>;   /* ENET2_GTXCLK */
 303                         };
 304
 305                         pio3: ucc_pin@03 {
 306                                 pio-map = <
 307                         /* port  pin  dir  open_drain  assignment  has_irq */
 308                                         0x2  0x1f 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
 309                                         0x2  0x1e 0x3  0x0  0x2  0x0    /* QE_MUX_MDIO */
 310                                         0x2  0x0b 0x2  0x0  0x1  0x0    /* CLK12*/
 311                                         0x0  0x1d 0x1  0x0  0x2  0x0    /* ENET3_TXD0_SER3_TXD0 */
 312                                         0x0  0x1e 0x1  0x0  0x3  0x0    /* ENET3_TXD1_SER3_TXD1 */
 313                                         0x0  0x1f 0x1  0x0  0x2  0x0    /* ENET3_TXD2_SER3_TXD2 */
 314                                         0x1  0x0  0x1  0x0  0x3  0x0    /* ENET3_TXD3_SER3_TXD3 */
 315                                         0x1  0x3  0x2  0x0  0x3  0x0    /* ENET3_RXD0_SER3_RXD0 */
 316                                         0x1  0x4  0x2  0x0  0x1  0x0    /* ENET3_RXD1_SER3_RXD1 */
 317                                         0x1  0x5  0x2  0x0  0x2  0x0    /* ENET3_RXD2_SER3_RXD2 */
 318                                         0x1  0x6  0x2  0x0  0x3  0x0    /* ENET3_RXD3_SER3_RXD3 */
 319                                         0x1  0x1  0x1  0x0  0x1  0x0    /* ENET3_TX_EN_SER3_RTS_B */
 320                                         0x1  0x9  0x2  0x0  0x3  0x0    /* ENET3_RX_DV_SER3_CTS_B */
 321                                         0x2  0x9  0x2  0x0  0x2  0x0    /* ENET3_GRXCLK */
 322                                         0x2  0x19 0x1  0x0  0x2  0x0>;  /* ENET3_GTXCLK */
 323                         };
 324
 325                         pio4: ucc_pin@04 {
 326                                 pio-map = <
 327                         /* port  pin  dir  open_drain  assignment  has_irq */
 328                                         0x2  0x1f 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
 329                                         0x2  0x1e 0x3  0x0  0x2  0x0    /* QE_MUX_MDIO */
 330                                         0x2  0x10 0x2  0x0  0x3  0x0    /* CLK17 */
 331                                         0x1  0xc  0x1  0x0  0x2  0x0    /* ENET4_TXD0_SER4_TXD0 */
 332                                         0x1  0xd  0x1  0x0  0x2  0x0    /* ENET4_TXD1_SER4_TXD1 */
 333                                         0x1  0xe  0x1  0x0  0x1  0x0    /* ENET4_TXD2_SER4_TXD2 */
 334                                         0x1  0xf  0x1  0x0  0x2  0x0    /* ENET4_TXD3_SER4_TXD3 */
 335                                         0x1  0x12 0x2  0x0  0x2  0x0    /* ENET4_RXD0_SER4_RXD0 */
 336                                         0x1  0x13 0x2  0x0  0x1  0x0    /* ENET4_RXD1_SER4_RXD1 */
 337                                         0x1  0x14 0x2  0x0  0x1  0x0    /* ENET4_RXD2_SER4_RXD2 */
 338                                         0x1  0x15 0x2  0x0  0x2  0x0    /* ENET4_RXD3_SER4_RXD3 */
 339                                         0x1  0x10 0x1  0x0  0x2  0x0    /* ENET4_TX_EN_SER4_RTS_B */
 340                                         0x1  0x18 0x2  0x0  0x3  0x0    /* ENET4_RX_DV_SER4_CTS_B */
 341                                         0x2  0x11 0x2  0x0  0x2  0x0    /* ENET4_GRXCLK */
 342                                         0x2  0x18 0x1  0x0  0x2  0x0>;  /* ENET4_GTXCLK */
 343                         };
 344                 };
 345         };
 346
 347         qe@e0080000 {
 348                 #address-cells = <1>;
 349                 #size-cells = <1>;
 350                 device_type = "qe";
 351                 compatible = "fsl,qe";
 352                 ranges = <0x0 0xe0080000 0x40000>;
 353                 reg = <0xe0080000 0x480>;
 354                 brg-frequency = <0>;
 355                 bus-frequency = <0>;
 356                 fsl,qe-num-riscs = <4>;
 357                 fsl,qe-num-snums = <46>;
 358
 359                 qeic: interrupt-controller@80 {
 360                         interrupt-controller;
 361                         compatible = "fsl,qe-ic";
 362                         #address-cells = <0>;
 363                         #interrupt-cells = <1>;
 364                         reg = <0x80 0x80>;
 365                         interrupts = <46 2 46 2>; //high:30 low:30
 366                         interrupt-parent = <&mpic>;
 367                 };
 368
 369                 spi@4c0 {
 370                         cell-index = <0>;
 371                         compatible = "fsl,spi";
 372                         reg = <0x4c0 0x40>;
 373                         interrupts = <2>;
 374                         interrupt-parent = <&qeic>;
 375                         mode = "cpu";
 376                 };
 377
 378                 spi@500 {
 379                         cell-index = <1>;
 380                         compatible = "fsl,spi";
 381                         reg = <0x500 0x40>;
 382                         interrupts = <1>;
 383                         interrupt-parent = <&qeic>;
 384                         mode = "cpu";
 385                 };
 386
 387                 enet0: ucc@2000 {
 388                         device_type = "network";
 389                         compatible = "ucc_geth";
 390                         cell-index = <1>;
 391                         reg = <0x2000 0x200>;
 392                         interrupts = <32>;
 393                         interrupt-parent = <&qeic>;
 394                         local-mac-address = [ 00 00 00 00 00 00 ];
 395                         rx-clock-name = "none";
 396                         tx-clock-name = "clk12";
 397                         pio-handle = <&pio1>;
 398                         phy-handle = <&qe_phy0>;
 399                         phy-connection-type = "rgmii-id";
 400                 };
 401
 402                 mdio@2120 {
 403                         #address-cells = <1>;
 404                         #size-cells = <0>;
 405                         reg = <0x2120 0x18>;
 406                         compatible = "fsl,ucc-mdio";
 407
 408                         qe_phy0: ethernet-phy@07 {
 409                                 interrupt-parent = <&mpic>;
 410                                 interrupts = <1 1>;
 411                                 reg = <0x7>;
 412                                 device_type = "ethernet-phy";
 413                         };
 414                         qe_phy1: ethernet-phy@01 {
 415                                 interrupt-parent = <&mpic>;
 416                                 interrupts = <2 1>;
 417                                 reg = <0x1>;
 418                                 device_type = "ethernet-phy";
 419                         };
 420                         qe_phy2: ethernet-phy@02 {
 421                                 interrupt-parent = <&mpic>;
 422                                 interrupts = <3 1>;
 423                                 reg = <0x2>;
 424                                 device_type = "ethernet-phy";
 425                         };
 426                         qe_phy3: ethernet-phy@03 {
 427                                 interrupt-parent = <&mpic>;
 428                                 interrupts = <4 1>;
 429                                 reg = <0x3>;
 430                                 device_type = "ethernet-phy";
 431                         };
 432                 };
 433
 434                 enet2: ucc@2200 {
 435                         device_type = "network";
 436                         compatible = "ucc_geth";
 437                         cell-index = <3>;
 438                         reg = <0x2200 0x200>;
 439                         interrupts = <34>;
 440                         interrupt-parent = <&qeic>;
 441                         local-mac-address = [ 00 00 00 00 00 00 ];
 442                         rx-clock-name = "none";
 443                         tx-clock-name = "clk12";
 444                         pio-handle = <&pio3>;
 445                         phy-handle = <&qe_phy2>;
 446                         phy-connection-type = "rgmii-id";
 447                 };
 448
 449                 enet1: ucc@3000 {
 450                         device_type = "network";
 451                         compatible = "ucc_geth";
 452                         cell-index = <2>;
 453                         reg = <0x3000 0x200>;
 454                         interrupts = <33>;
 455                         interrupt-parent = <&qeic>;
 456                         local-mac-address = [ 00 00 00 00 00 00 ];
 457                         rx-clock-name = "none";
 458                         tx-clock-name = "clk17";
 459                         pio-handle = <&pio2>;
 460                         phy-handle = <&qe_phy1>;
 461                         phy-connection-type = "rgmii-id";
 462                 };
 463
 464                 enet3: ucc@3200 {
 465                         device_type = "network";
 466                         compatible = "ucc_geth";
 467                         cell-index = <4>;
 468                         reg = <0x3200 0x200>;
 469                         interrupts = <35>;
 470                         interrupt-parent = <&qeic>;
 471                         local-mac-address = [ 00 00 00 00 00 00 ];
 472                         rx-clock-name = "none";
 473                         tx-clock-name = "clk17";
 474                         pio-handle = <&pio4>;
 475                         phy-handle = <&qe_phy3>;
 476                         phy-connection-type = "rgmii-id";
 477                 };
 478
 479                 muram@10000 {
 480                         #address-cells = <1>;
 481                         #size-cells = <1>;
 482                         compatible = "fsl,qe-muram", "fsl,cpm-muram";
 483                         ranges = <0x0 0x10000 0x20000>;
 484
 485                         data-only@0 {
 486                                 compatible = "fsl,qe-muram-data",
 487                                              "fsl,cpm-muram-data";
 488                                 reg = <0x0 0x20000>;
 489                         };
 490                 };
 491
 492         };
 493
 494         /* PCI Express */
 495         pci1: pcie@e000a000 {
 496                 compatible = "fsl,mpc8548-pcie";
 497                 device_type = "pci";
 498                 #interrupt-cells = <1>;
 499                 #size-cells = <2>;
 500                 #address-cells = <3>;
 501                 reg = <0xe000a000 0x1000>;
 502                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 503                 interrupt-map = <
 504                         /* IDSEL 0x0 (PEX) */
 505                         00000 0x0 0x0 0x1 &mpic 0x0 0x1
 506                         00000 0x0 0x0 0x2 &mpic 0x1 0x1
 507                         00000 0x0 0x0 0x3 &mpic 0x2 0x1
 508                         00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 509
 510                 interrupt-parent = <&mpic>;
 511                 interrupts = <26 2>;
 512                 bus-range = <0 255>;
 513                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
 514                           0x1000000 0x0 0x00000000 0xe2800000 0x0 0x00800000>;
 515                 clock-frequency = <33333333>;
 516                 pcie@0 {
 517                         reg = <0x0 0x0 0x0 0x0 0x0>;
 518                         #size-cells = <2>;
 519                         #address-cells = <3>;
 520                         device_type = "pci";
 521                         ranges = <0x2000000 0x0 0xa0000000
 522                                   0x2000000 0x0 0xa0000000
 523                                   0x0 0x10000000
 524
 525                                   0x1000000 0x0 0x0
 526                                   0x1000000 0x0 0x0
 527                                   0x0 0x800000>;
 528                 };
 529         };
 530 };